JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL. 22, NO. 5, OCTOBER, 2022
https://doi.org/10.5573/JSTS.2022.22.5.376
ISSN(Print) 1598-1657
ISSN(Online) 2233-4866
Investigation of p-type High Temperature Field Effect
Transistor for CMOS Logic Application
Tae-Woong Jeong1, Yun-Jae Oh1, Seo-Yeon Chun1, Dae Hwan Kim2,
Woojoo Lee3,*, and Il Hwan Cho1,*
Abstract—In this study, we propose a silicon-based
metal oxide semiconductor field effect transistor
(MOSFET) device for p-type that can operate at a
high temperature (at 573 K). This device can be
applied to logic circuits, and furthermore, used in
semiconductor chips operating in high temperature
environments. Through research, we selected 3C-SiC,
which can prevent off-current most effectively, as a
material to be applied to the device. After that,
technology computer aided design (TCAD) simulation
will be used to apply the interface characteristics
according to the physical properties of silicon and 3CSiC, and to optimize the current characteristics of
device as a logic element. In addition, we investigated
a complementary metal oxide semiconductor (CMOS)
logic circuit with simulation program with integrated
circuit emphasis (SPICE) and verify the inverting
characteristics in a high temperature environment of
573 K by applying the device of this study.
Index
Terms—Field
effect
transistor,
temperature operation, CMOS logic
high
Manuscript received Aug. 25, 2022; reviewed Sep. 23, 2022;
accepted Oct. 1, 2022
1
Department of Electronic Engineering, Myongji University, Yongin-si,
Gyeonggi-do 17058, Korea.
2
School of Electrical Engineering, Kookmin University, Seoul 02707,
Korea
3
School of Electrical and Electronics Engineering, Chung-Ang
University, Seoul, 06973, Korea
E-mail : space@cau.ac.kr; ihcho77@mju.ac.kr
I. INTRODUCTION
Many industries related to automotive, well logging,
aerospace, nuclear fuel power plants, and semiconductor
processing require electronic equipment to operate in a
variety of high temperature environments exceeding
200 °C [1, 2]. Particularly, in the growing electric vehicle
market, more than 1,000 semiconductor chips are used
per vehicle [3]. Among them, semiconductor chips for
engine control unit (ECU), power converter, etc. must
operate in a high temperature environment around
200 °C, so high temperature semiconductors with high
reliability are required [4, 5]. Moreover, interest in the
automation of well logging technology is growing these
days. Measuring and drilling equipment used inside wells
during well logging is exposed to environments up to
175-250 °C [6, 7]. The development of high temperature
semiconductors to be used in this environment is
essential for automation of the well logging industry.
Although the demand for semiconductor chips
operating at high temperatures has been increasing, there
is a problem that the conventional silicon-based metal
oxide semiconductor field effect transistor (MOSFET)
device cannot operate normally at high temperatures [8].
When the MOSFET is used in a high temperature
environment, a large amount of electron hole pair (EHP)
is generated, and excessive leakage current flows in the
off-state due to thermionic emission of the generated
carriers. As a result, the threshold voltage is reduced and
the subthreshold leakage is increased [9, 10].
Recently, high temperature semiconductors use a
substrate material composed of GaN or SiC with a large
bandgap to prevent leakage current [11, 12]. Since the
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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL. 22, NO. 5, OCTOBER, 2022
compound semiconductors have wider band gap than Si,
they can effectively inhibit excessive generation of EHPs
at high temperature. However, in the case of a high
temperature device process using a wide band gap
material as a substrate, a large-area wafer cannot be used
[13]. In particular, GaN substrates have a problem of
process suitability with silicon, so buffer materials must
be used during the process, hence the yield is low during
the mass production process and economic efficiency is
insufficient aspect due to the limitation of the area of the
substrate [14].
In order to improve those problems, the wide band gap
material is deposited on a silicon-based device in the
form of a trench between a source and a channel to
efficiently prevent thermionic emission. In a previous
paper, our group introduced the n-type of high
temperature field effect transistor (HTFET) [15]. It
maintains electrical advantages of semiconductor for
high temperature based on existing compound
semiconductor material and improves the fabrication
process. Also, we are able to maximize economic profits
because it can be fabricated with large wafers. In addition,
since the process is easier than those of devices having
various structures, there is an advantage of reducing costs.
All digital logic circuits consist of a pull-up network
and a pull-down network. In other words, in order to
manufacture a semiconductor chip composed of digital
logic circuits, it is essential to develop a p-type HTFET
that exhibits voltage-current characteristics similar to the
n-type HTFET in the previous study.
In this paper, we proposed and optimized HTFET for
the complementary metal oxide semiconductor (CMOS)
logic. The p-type HTFET is designed to have an
appropriate leakage current and on/off ratio in a high
temperature environment and applied to a circuit with
voltage-current characteristics to implement CMOS logic.
377
Fig. 1. P-type HTFET device structure.
channel and source in the form of nano trench. The nano
trench structure has a thickness of 30 nm and the depth is
200 nm. The type of wide bandgap material used in ptype is 3C-SiC. 3C-SiC is the most suitable material to
prevent off-current of p-type devices operating at high
temperatures. The gate length is 130 nm. We also design
the thickness of gate oxide as 2 nm because 2 nm is
enough to prevent gate leakage. Poly-gate doping
concentration is 4 × 1020 cm −3 to form a better ohmic
contact. Source and drain doping concentration is same
as poly-gate doping concentration. Finally, the doping
concentration of the body was determined to be
1× 1016 ?cm −3 for matching with threshold voltage of n-
type device. The high temperature operating device
simulations are performed on Synopsys Sentaurus
technology computer aided design (TCAD) simulator.
We simulated a high-temperature environment in TCAD
using a Thermode. In addition, we included basic physics
models of Shockley-Read-Hall recombination, high field
saturation, band to band tunneling, doping and electric
field dependent mobility.
II. DEVICE STRUCTURE
III. RESULT & DISCUSSION
The structure of this p-type HTFET device is shown in
Fig. 1. The device of this study used the silicon on
insulator (SOI) substrate structure to prevent leakage
from the body in a high temperature environment. The
thickness of the buried oxide (BOX) was 50 nm. In
addition, to effectively prevent thermionic emission by
EHP, the wide bandgap material was deposited between
1. Selecting wide Band Gap Material for p-type
HTFET
In contrast to conventional SOI MOSFETs, the
HTFET device with a nano trench structure on which a
wide band gap material is deposited forms a high energy
barrier between the source and the channel. The energy
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378
TAE-WOONG JEONG et al : INVESTIGATION OF p-type HIGH TEMPERATURE FIELD EFFECT TRANSISTOR FOR …
-2
10
Drain current (A/μm)
TEMP = 573 K, VD = 1.2 V
-4
10
-6
Conventional SOI
MOSFET
GaP
MoS2
-8
CdTe
WO3
10
10
3C-SiC
CeO2
-10
10
-5
-4
-3
-2
-1
0
1
Gate voltage (V)
(a)
Fig. 2. Energy band diagram for p-type HTFET.
band diagram of channel region contains narrow energy
barrier with wide band gap material as shown in Fig. 2.
This barrier suppresses EHP generated in large quantities
at high temperature and prevents excessive leakage
current flowing by thermionic emission in the off state
[16, 17]. Since the HTFET shows a lower off-current
than the conventional SOI MOSFET in a high
temperature environment, it is possible to obtain an
on/off ratio characteristic that classifies the logic level.
As a result, it can be applied to CMOS logic circuits [18,
19].
Fig. 3(a) is the transfer characteristics of p-type
HTFET device and p-type SOI MOSFET with the same
specifications. In the case of HTFET devices, simulations
were carried out by applying various wide band gap
materials to the nano trench region, respectively.
According to the results in Fig. 3(a), a conventional
SOI MOSFET showed a high off-current of
−1.23 × 10 −4 A / μm at 573 K. The on/off ratio value is
3.68, showing such small values that the logic values 0
and 1 cannot be distinguished in the digital logic circuit.
The p-type HTFETs with various wide band gap material
shows relatively large on/off ratio due to the blocking of
thermionic emission at a high temperature. These results
are similar with that of n-type HTFET in our previous
work [15]. When various wide band gap materials are
applied to the nano trench region of the HTFET, the
height of the barrier formed in the valance band can be
determined. As shown in Table 1, valance band barriers
of various materials were estimated and applied to the
Band energy (eV)
2
TEMP = 573 K, VD = 1.2 V
1
0
Conventional SOI
MOSFET
GaP
MoS2
-1
-2
CdTe
WO3
3C-SiC
CeO2
-0.1
0.0
0.1
Distance (μm)
(b)
Fig. 3. (a) Transfer characteristics; (b) channel energy band
diagram of p-type HTFET with various wide band gap
materials.
simulation Fig. 3(b). As a result of the simulation shown
in Fig. 3(a), it was confirmed that the off-current
decreased exponentially in inverse proportion to the
height of the barrier, as the thermionic emission equation
[20]. When the 3C-SiC is used, it has an off-current of
−3.87 × 10−10 A / μm , and the on/off ratio is 1.73 × 104 ,
which is sufficient to distinguish the logic of 0 and 1. The
measured value shows a improvement of nearly 5,000
times from the on/off ratio of 3.68, in which a high
temperature conventional SOI MOSFET was obtained.
However, in the case of a material having a valance band
barrier height higher than 3C-SiC, on-current decreases,
and off-current limitation occurs in which off-current
stays at a certain level without following the thermionic
emission equation. Considering the designed operating
range of CMOS logic ( VDD = 1.2 V ), there is a problem
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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL. 22, NO. 5, OCTOBER, 2022
379
Table 1. Properties of wide band gap materials
Electron Affinity
(eV)
Band Gap
(eV)
Valance band
Barrier Height (eV)
GaP
3.2
2.25
0.33
MoS2
4.2
1.4
0.48
CdTe
4.28
1.44
0.6
WO3
3.3
2.6
0.78
3C-SiC
3.8
2.36
1.04
CeO2
3.5
2.94
1.32
4
1.6x10
On/off ratio
Material
4
1.2x10
3
8.0x10
3
4.0x10
0.0
-2
10
11
Drain current (A/μm)
10
-4
10
-6
12
10
-2
5 x 10 cm
11
-2
1 x 10 cm
11
-2
5 x 10 cm
12
-2
1 x 10 cm
12
-2
5 x 10 cm
13
-2
1 x 10 cm
13
10
10
-2
Interface trap charge density (cm )
Fig. 5. Transfer characteristics with various interface trap
charge densities.
10
simulation was performed while changing the interface
trap charge density from 1× 1013 cm −2 to 5 × 1010 cm −2 .
-8
10
11
-2
3C-SiC/SiO2 = 1 x 10 cm
When the trap charge is reduced from 1 ×1013 cm −2 to
TEMP = 573 K, VD = 1.2 V
-10
10
-5
-4
-3
-2
-1
0
1
5 × 1011 cm −2 , the on/off ratio of the device increases. In
addition, when the trap charge is reduced from 5 ×1011 to
Gate voltage (V)
Fig. 4. Transfer characteristics with various interface trap
charge densities.
5 ×1010 cm −2 over 5 ×1011 cm −2 , the on/off ratio decreases,
as shown in Fig. 5. This simulation results shows that the
p-type device designed in this study for high-temperature
that CeO2 has a lower on-current in on state due to the
operation has the highest on/off ratio of 1.68 × 10 4 at
higher valance band barrier height than 3C-SiC. It shows
5 ×1011 cm −2 . Furthermore, it was found that the value of
on-current
of
−1.29 × 10−7 A / μm
−6.70 × 10−6 A / μm
for
3C-SiC.
for
CeO 2
Accordingly,
and
5 ×1011 cm −2 is the most suitable when considering the
the
margin that reflects realistic process limits for reaching
leakage current reduction by the barrier in the off state is
similar, but the on/off ratio is reduced by about 100 times
the maximum level of 5 ×1010 cm −2 .
to 4.26 × 102 compared to 3C-SiC with an on/off ratio
having an interface trap charge of about 5 × 1011 cm −2 at
of 1.73 × 10 4 due to the on-current difference. Thus 3C-
the 3C-SiC/Si interface and this value of 5 × 1011 cm −2
SiC would be more suitable as a wide band gap material.
Meanwhile, due to lattice mismatch and difference in
thermal expansion coefficient with silicon, 3C-SiC
requires a carbonization process of a silicon interface, a
chemical vapor deposition (CVD) process and an
annealing process in sequence in order to deposit 3C-SiC
in the nano trench structure of the HTFET device
proposed in this research [21]. Considering the
fabrication of p-type HTFET, the influence of the charges
at the interface between Si and 3C-SiC was investigated
with TCAD simulation. According to previous result, it is
possible to reduce the interface charge of 3C-SiC to
5 × 1010 cm −2
through annealing process [22]. The
Therefore, it is possible to process an HTFET device
was applied to device design in this study. The 3CSiC/SiO2 interface trap charge density values used in this
paper have almost the same range as those measured in
previous studies, 1× 1011 cm −2 [23].
2. Device Characterization and Optimization
We introduce improvement and optimization of p-type
HTFETs based on the previously determined materials
(3C-SiC) and interface conditions. The first optimization
parameter is the body doping concentration. Range of
body
doping
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variation
is
from
1× 1018 cm −3
to
TAE-WOONG JEONG et al : INVESTIGATION OF p-type HIGH TEMPERATURE FIELD EFFECT TRANSISTOR FOR …
-2
-2
10
10
10 cm
17
-3
10 cm
16
-3
10 cm
-4
10
-6
10
-8
10
TEMP = 573 K, VD = 1.2 V
-5
-4
10
-6
10
-8
10
TEMP = 573 K, VD = 1.2 V
-10
-10
10
10 nm
20 nm
30 nm
40 nm
-3
Drain current (A/μm)
Drain current (A/μm)
18
-4
-3
-2
-1
0
10
1
-5
-4
the off-current decreased as the doping concentration of
the body decreased. More specifically, the body doping
concentration of 1× 1018 cm −3 has an on/off ratio of
17
−3
has an on/off ratio of
6.57 × 102 , and 1× 10 cm
4.75 × 10 . When doped with a concentration of
3
1× 1016 cm −3 , the on/off ratio showed an improved on/off
carried out with the corresponding value. As the body
doping is lowered, the barrier of the hole existing
between the drain and the channel increases, so the off
current and on/off current ratio will be improved.
In the p-type HTFET device, a wide band gap material
to prevent thermionic emission was deposited in a nano
trench structure between the source and the channel. In
this study, the thickness of nano trench was changed to
check the leakage current caused by the horizontal
electric field. In Fig. 7(a), the off current and on/off ratio
improved as the thickness increased in the p-type HTFET
as in the n-type HTFET. In Fig. 7(b), when the thickness
of nano trench increased from 10 nm to 20 nm, the off−3.49 × 10
1
−8.93 × 10−10 A / μm
to
A / μm . We applied direct tunneling physics
to the simulation, and it was confirmed that the direct
tunneling phenomenon did not affect the leakage current
of the device even at the thickness of 10 nm. After that,
at a thickness of 20 nm or more, the decrease in offcurrent was insignificant even as the thickness increased.
However, while the on/off ratio increased from 10 nm to
-9
1.8x10
4
-10
1.6x10
-10
1.4x10
4
8.0x10
4
6.0x10
4
Off-current
On/off ratio
-10
4.0x10
1.2x10
4
1.0x10
-10
2.0x10
ratio value of 1.68 × 104 , and the device design was
−10
0
1.0x10
Off-current (A/μ m)
1× 1016 cm −3 as shown in Fig. 6. It was confirmed that
from
-1
(a)
Fig. 6. Transfer characteristics with various body doping
concentration.
decreased
-2
Gate voltage (V)
Gate voltage (V)
current
-3
On/off ratio
380
10
20
30
40
Distance (nm)
(b)
Fig. 7. (a) Transfer characteristics; (b) off current and on/off
current ratio with various wide band gap material thickness.
30 nm, the on-current decreased at 40 nm thickness, and
the on/off ratio decreased to 1.62 × 104 . Accordingly, it
was found that the nano trench thickness of 30 nm
showed an on/off ratio of 1.68 × 104 and was the
optimal thickness of the nano trench in the structure of
the p-type HTFET device.
In this study, we were able to obtain a hole barrier
height of 1.04 eV by applying a 3C-SiC material. Fig. 8
shows the effect of changing the hole barrier on the
device's operating characteristics. When the barrier
height is less than 1.04 eV, the leakage current is
exponentially increased as the barrier height reduces due
to the thermionic emission current characteristics.
However, when the barrier height is 1.04 eV or more, the
leakage current does not decrease significantly even
when the barrier height was increased Fig. 8. In order to
explain this off-current limiting phenomenon, a barrier
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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL. 22, NO. 5, OCTOBER, 2022
4
-4
10
0.44 eV
0.54 eV
0.64 eV
0.74 eV
0.84 eV
0.94 eV
1.04 eV
1.14 eV
1.24 eV
1.34 eV
Off-current (A/μ m)
-6
10
-7
10
-8
10
TEMP = 573 K, VD = 1.2 V
3
Band energy (eV)
-5
10
-9
10
-10
10
2
1
0
HB = 1.34, EB = 2.20
HB = 1.34, EB = 0.20
-1
* HB : Hole energy barrier height (eV)
* EB : Electron energy barrier height (eV)
-2
-11
10
0.4
0.6
0.8
1.0
1.2
-0.1
1.4
-4
-4
10
Total current
Hole current
Electron current
10
Drain current (A/μm)
Drain current (A/μm)
TEMP = 573 K, VD = 1.2 V
-6
-8
10
-10
10
-12
10
-14
10
-16
-5
-4
-3
-2
-1
0.1
Fig. 10. Energy band diagram with hole energy barrier height
and electron barrier height variation.
Fig. 8. Off-current with hole energy barrier height variation.
10
0.0
Distance (μm)
Barrier height (eV)
10
381
0
1
TEMP = 573 K, VD = 1.2 V
Total current
Hole current
Electron current
-6
10
-8
10
-10
10
-12
10
-14
10
-16
10
Gate voltage (V)
-5
-4
-3
-2
-1
0
1
Gate voltage (V)
Fig. 9. Transfer characteristics including hole current and
electron current with 1.34 eV hole energy barrier.
value larger than 1.04 eV was arbitrarily set (1.34 eV)
and the current characteristics were extracted. Fig. 9
shows the transfer characteristics of the device in which
only the hole barrier was changed to 1.34 eV with the
same other conditions.
In the high-temperature operation of the p-type
HTFET, the off current is determined by the minority
carrier electron. The energy band diagram in Fig. 10
explains why the leakage current is dominated by
electrons. In the energy band diagram of the off current
region indicated by the black line, electrons do not have
sufficient energy barrier, which causes leakage current to
flow. The red line in Fig. 10 is the simulation result of
artificially increasing the electron energy barrier to
2.20 eV. If the energy barrier of electrons is increased
with this value, the current component as shown in Fig.
11 can be obtained. If a better material other than 3C-SiC
Fig. 11. Transfer characteristics including hole current and
electron current when hole energy barrier is 1.34 eV and
electron energy barrier is 2.20 eV.
is applied to the p-type HTFET, it can be concluded that
the electron barrier should be considered first. The effect
of such a minority carrier has not been reported in the
study of n-type HTFETs. Also, this result will be applied
to the n-type HTFET as only the carrier type is changed.
3. Verification of CMOS Logic in High Temperature
The CMOS logic gate structure has the advantages of
higher control, lower power consumption, and improved
integration than a single transistor [24]. In this chapter,
we introduce the characteristics of CMOS inverter using
the p-type HTFET proposed and optimized. Fig. 12
shows the configuration and operating voltage of CMOS
inverter applied in this study. Based on the transfer curve
characteristics of the device, the parameter was fitted as
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382
TAE-WOONG JEONG et al : INVESTIGATION OF p-type HIGH TEMPERATURE FIELD EFFECT TRANSISTOR FOR …
Fig. 12. Schematic of CMOS logic inverter with HTFETs.
conventional MOSFET in a 573 K high temperature
environment, inverter characteristics for input signals is
not achieved as shown in the Fig. 13. However, as a
result of designing CMOS logic with the HTFET device
designed in this study, it was possible to confirm the
inverter characteristics for the input signal in a high
temperature environment of 573 K. According to the
result of Fig. 13(c), a pulse curve with delay is formed
when rising because the characteristics of devices applied
to logic circuits are influenced by the relatively small
on/off ratio compared to the current characteristics of
conventional MOSFETs operating at 300 K [25].
Nevertheless, through the verification of CMOS logic,
the proposed p-type HTFET device demonstrated the
switching characteristic that distinguish between logic 0
and 1 as a logic device during high temperature operation,
and suggested the feasibility of applying it to a more
complex logic circuit than CMOS logic.
IV. CONCLUSIONS
Fig. 13. Inverter logic simulation result: (a) input voltage; (b)
output voltage of conventional MOSFET at 573 K; (c) output
voltage of HTFET at 573 K.
the characteristics of HTFET usable on HSPICE. Also,
for configurating the CMOS logic, n-type HTFET which
is previously researched was optimized to match with the
p-type device studied in this study [15]. The fitting was
performed in the same way for this n-type device. The ntype HTFET device constituting CMOS logic together
with p-type has an off-current of 3.17 × 10−9 A / μm and
an on/off ratio of 1.50 × 104 . As for the input voltage of
CMOS logic, as shown in Fig. 13(a), a square wave with
a pulse width (PW) of 1.4 ns, time rise (TR) of 0.1 ns,
and down delay (TD) of 0.1 ns was applied with a period
of 3.0 ns. Fig. 13(b) is the output voltage in which
CMOS logic is configured with conventional MOSFET
at 573 K. Fig. 13(c) is the output voltage in which the
CMOS logic is configured with HTFET at 573 K. In the
case of CMOS logic, which is designed with a
In this study, we proposed a p-type HTFET device
with current characteristics that can operate as a logic
device even at high temperatures. 3C-SiC, a wide bang
gap material suitable for p-type devices, was applied
between the source and the channel in the form of nano
trench. This formed a barrier of sufficient height in the
valance band to appropriately suppress the leakage
current of the p-type device in the off state, thereby
obtaining the desired current characteristics. In addition,
the device design was carried out in consideration of the
trap charge density generated at the 3C-SiC/Si interface
during the actual process of the device. As a logic device,
the body doping concentration and the thickness of the
nano trench structure to which the wide band gap
material is applied were adjusted to have an optimal
on/off ratio. In this process, we were able to confirm the
off-current limitation phenomenon. A CMOS logic
circuit was performed with optimized p-type HTFET
device to confirm the CMOS operation in a hightemperature environment. This proves that the designed
p-type HTFET can be used in complex logic circuits
operating at high temperatures.
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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL. 22, NO. 5, OCTOBER, 2022
ACKNOWLEDGMENTS
[9]
This work was supported by the National Research
Foundation of Korea (NRF) grant funded by the Korean
government (MSIT) (No. 2021R1F1A1056255). This
work was also supported in part by the National Research
Foundation of Korea (NRF) grant funded by the Korea
Government (MSIT) (No. 2016R1A5A1012966) and
(2020R1F1A1066474). The EDA tool was supported by
the IC Design Education Center (IDEC), Korea.
[10]
[11]
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TAE-WOONG JEONG et al : INVESTIGATION OF p-type HIGH TEMPERATURE FIELD EFFECT TRANSISTOR FOR …
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Tae-Woong Jeong is currently
pursuing the B.S. degree in the
Department of Electronic Engineering from Myongji University,
Yong-In, South Korea. His interests
include Device design with TCAD
simulation and Neuromorphic device.
Yun-Jae Oh is currently pursuing the
B.S. degree in the Department of
Electronic
Engineering
from
Myongji University, Yong-In, South
Korea. Her research interests include
Device process with packaging and
Neuromorphic device.
is currently
Seo-Yeon Chun
pursuing the B.S. degree in the
Department of Electronic Engineering from Myongji University,
Yong-In, South Korea. Her research
interests include Device design with
TCAD simulation and Neuromorphic
device.
Dae Hwan Kim received the B.S.,
M.S., and Ph.D. degrees in electrical
engineering from Seoul National
University, Seoul, South Korea, in
1996, 1998, and 2002, respectively.
He is currently a Professor with the
School of Electrical Engineering,
Kookmin University, Seoul. His current research
interests include nano CMOS, oxide and organic thin
film transistors, biosensors, and neuromorphic devices.
Woojoo Lee received his B.S. (2007)
in electrical engineering from Seoul
National University, Seoul, Korea,
and his M.S. (2010) and Ph.D.
(2015)
degrees
in
electrical
engineering from University of
Southern California, Los Angeles,
CA. He was with Electronics and Telecommunications
Research Institute (2015-2016) as a senior researcher in
SoC Design Research Group, Department of Electrical
Engineering at Myongji University (2017-2018) as an
assistant professor. He is currently an associate professor
with the School of Electrical & Electronics Engineering,
Chung-Ang University, Seoul, Korea. His research
interest includes ultra-low power VLSI and SoC designs,
embedded system designs, and system-level power and
thermal management.
www.dbpia.co.kr
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL. 22, NO. 5, OCTOBER, 2022
Il Hwan Cho received the B.S. in
Electrical Engineering from Korea
Advanced Institute of Science and
Technology (KAIST), Daejon, Korea,
in 2000 and M.S., and Ph.D. degrees
in electrical engineering from Seoul
National University, Seoul, Korea, in
2002, 2007, respectively. From March 2007 to February
2008, he was a Postdoctoral Fellow at Seoul National
University, Seoul, Korea. In 2008, he joined the
Department of Electronic Engineering at Myongji
University, Yongin, where he is currently a Professor. His
current research interests include improvement,
characterization and measurement of non-volatile
memory devices and nano scale transistors including
tunneling field effect transistor.
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