FET
*In
the FET, current flows along a
semiconductor path called the channel.
At one end of the channel, there is an
electrode called the source (the end of
channel from which electrons flow) . At
the other end of the channel, there is an
electrode called the drain (other end
toward which they flow) .
FET
*The conductivity of the FET depends, at
any given instant in time, on the electrical
diameter of the channel. A small change
in gate voltage can cause a large
variation in the current from the source
to the drain.
Figure 6—1
A two-terminal nonlinear device: (a) biasing
circuit; (b) I–V characteristic and load line.
Figure 6—2
A three-terminal nonlinear device that can be controlled by the voltage at
the third terminal vG: (a) biasing circuit; (b) I–V characteristic and load line.
If vG = 0.5 V, the d-c values of ID and VD are as shown by the dashed lines.
FET
*The channel width can be controlled by controlling
the GATE VOLTAGE , that is why it is called FET
FET
JFET
Junction
Field Effect
Transistor
MOSFET
Metal Oxide
Semiconductor
Field Effect
Transistor
MESFET
Metal Oxide
Semiconductor Field
Effect Transistor
THE JUNCTION FET
Basic structure
Some facts about its operation
Characteristic curve
Depletion and enhancement FET
THE JUNCTION FET
Construction
.A solid bar, made either of N-type or P-type material,
forms the main body of the device.
Diffused into each side of this bar are two deposits of
material of the opposite type from the bar material,
which form the "gate."
The portion of the bar between the deposits of gate
material is of a smaller cross section than the rest of the
bar and forms a "channel" connecting the source and
the drain.
THE JUNCTION FET( Contd.)
General Structure
THE JUNCTION FET( Contd.)
Some facts about working
In JFET voltage variable depletion region width of a
junction is used to control the effective cross
sectional area of a conducting channel.
Resistivity of the channel is fixed by its doping, the
channel resistance varies with changes in the
effective cross sectional area.
THE JUNCTION FET( Contd.)
Some facts about working ( Contd.)
Since the conductivity of the heavily doped p+
regions is high, we can assume that the potential
is uniform through out each gate.
In the lightly doped channel material, however,
the potential varies with position
Figure 6—3
Simplified cross-sectional view of a junction FET: (a) transistor
geometry; (b) detail of the channel and voltage variation along the
channel with VG = 0 and small ID.
THE JUNCTION FET( Contd.)
THE JUNCTION FET( Contd.)
Some facts about working ( Contd.)
If the channel is considered as a distributed resistor
carrying a current ID, it is clear that he voltage from the
drain end of the channel ‘D’ to the source electrode ‘S’
must be greater than the voltage from a point near the
source end to ‘S’. For low values of current, we an
assume a linear variation of voltage Vx in the channel,
varying from VD at the drain end to zero at the source
end.
THE JUNCTION FET( Contd.)
Understanding the working of FET
Mainly, I need to understand the effect of two
main parameters i.e. Effect of Gate Source
Voltage ( i.e. VGS ) and Drain Source Voltage ( i.e.
VDS).
So let us first take VGS = 0 V and vary VDS
THE JUNCTION FET( Contd.)
Working of FET ( Contd.) ( Effect of VDS
alone)
THE JUNCTION FET( Contd.)
Working of FET ( Contd.) ( Effect of VDS
alone)
THE JUNCTION FET( Contd.)
Working of FET ( Contd.) ( Effect of VDS
alone)
THE JUNCTION FET( Contd.)
Working of FET ( Contd.) ( Effect of VDS
alone)
Why channel can not get completely blocked ?
Blocking of channel completely means that ID = 0.
The absence of drain current would remove the
possibility of differential potential levels through the n –
channel material to establish the varying levels of
reverse bias along the pn junction. The result would be a
loss of the depletion region distribution that caused
pinch off in the first place.
THE JUNCTION FET( Contd.)
Working of FET ( Contd.) ( Effect of VGS as
well)
THE JUNCTION FET( Contd.)
From here, we can learn the concept of
Depletion and Enhancement type of
Transistors :
A device in which the channel has to be created
by application of a suitable bias at the gate is
called the enhancement mode and the other one
as depletion mode.
Calculation of Pinch off voltage
Operation of JFETs
For a p+n junction in reverse bias,
2  Vr 
Vr  VDG  VDS  VGS  VD  VG
W 
qN d
assuming that contact potential V0 is negligible compared to Vr
At, x = 0
At, x = L,
2  VG 
W  y1 
qN d
2VD  VG 
W  y2 
qNd
Operation of JFETs
At, x = L,
2 VD  VG 
W  y2 
qN d
At, x = L,
W=a
and hence
VD – VG = VP ( Pinch off voltage ) = q a2 Nd / 2
Current-Voltage characteristics
Calculation of exact channel current is complicated.
Hence, we shall find the expression for ID just at pinch
off and then assume the saturation current beyond pinch
off remains fairly constant at this value.
Here in this
figure,
the
center of the
channel at the
source end is
taken as origin.
The length of
the channel in
the x- direction
is ‘L’
Current-Voltage characteristics ( Contd.)
We call the resistivity of the n – type channel material ,
valid only in the neutral ‘n’ material , outside the
depletion regions.
If we consider the differential volume of the neutral
channel material Z2h(x)dx, the resistance of the volume
element is
dx / Z2h(x)
Since the current does not change with distance along
the channel,
Current-Voltage characteristics ( Contd.)
ID is related to the differential voltage change in
the element dVx by the conductance of the
element :
Z 2h( x) dVx
ID 

dx
The term 2h(x) is the channel width at ‘x’.
Current-Voltage characteristics ( Contd.)
The half width of the channel at point ‘x’ depends on the
local reverse bias between gate and channel –VGX :
2
h( x )  a  W ( x )  a 
(VGX )
qN d
  (V  V ) 1/ 2 
G 

 h( x)  a 1   x
 
  V p
 

As VGX = VG – VX and
VP = q a2 Nd / 2 
Current-Voltage characteristics ( Contd.)
Implicit in above equation is the assumption that the
expression for W(x) can be obtained by a simple
extension to point ‘x’ in the channel of the below
mentioned eqn., which we had written earlier i.e.
W 
2  Vr
qN d

This is called the gradual channel approximation; it is
valid if h(x) does not vary abruptly in any element ‘dx’
Current-Voltage characteristics ( Contd.)
The voltage VGX will be negative, since the gate voltage
is chosen zero or negative.
Now, if we substitute the value of h(x) in equation for ID,
We get :
1/ 2

 (Vx  VG )  
2Za
  dVx
1  
I D dx 
   VP  


Solving this : -
Current-Voltage characteristics ( Contd.)
1/ 2




2Za   (Vx  VG )  
I D  dx 
1
dVx



 x 0   V p  
x 0


L
L
2Za
2 (Vx  VG )
or , I D L 
Vx 

3 V p1 / 2
3/ 2
xL
x 0
V 2  (V  V ) 3 / 2 2  V 3 / 2 
 I D  G0VP  D   D G     G  
3  VP  
 VP 3  VP 

Where
VG
is
negative and G0
= 2aZ /  L is the
conductance of
the channel for
negligible W(x),
i.e. with no gate
voltage and low
values of ID. This
eqn. is valid only
up to pinch off,
where VD – VG =
VP.
Current-Voltage characteristics ( Contd.)
3/ 2
3/ 2 
V
 (VD  VG ) 
 VG 
2
2
D
    
I D  G0VP   
 V  

3
 VP 3  V p
 P 


If we assume the saturation current remains essentially
constant at its value at pinch off, we have : -
Current-Voltage characteristics ( Contd.)
V
2 2  VG 
D
I D ( sat .)  G0VP      
 VP 3 3  VP 
3/ 2
V



V
1
2
 G0VP  G     G  
VP 3 3  VP  
Where,
VG
VD
 1
VP
VP
3/ 2



Current-Voltage characteristics ( Contd.)
V


V
1
2
G
G

I D ( sat.)  G0VP      
VP 3 3  VP 
3/ 2



Current-Voltage characteristics ( Contd.)
The resulting family of I – V curves for the channel
agrees with the results, we predicted qualitatively. The
saturation current is greatest, when VG is zero and
becomes smaller as VG is made negative.
Current-Voltage characteristics ( Contd.)
Device biased in the saturation region can be
represented by an equivalent circuit, where changes in
drain current are related to gate voltage changes by
dI D ( sat .)
gm 
dVGS
  V 1/ 2 
 GO 1    G  
  VP  
The quantity gm is the mutual transconductance with
units (A/V) . As a figure of merit for FET devices, it is
common to describe the transconductance per unit
channel width’Z’.
Current-Voltage characteristics ( Contd.)
Experimentally, it is found that ID(sat.) can be
approximated to the simpler expression,
 VG 
I D (sat.)  I DSS 1 

V

P 
2
where IDSS is the saturated drain current at VG = 0.
This gives,
dI D (sat.) 2I DSS  VG 
1  
gm 

dVG
Vp  VP 
The Metal – Semiconductor FET
*Consists of a conducting channel positioned between a
source and drain contact region.
•The carrier flow from source to drain is controlled by a
Schottky metal gate.
• The control of the channel is obtained by varying the
depletion layer width underneath the metal contact
which modulates the thickness of the conducting
channel and thereby the current.
MESFET Structure
HEMT
So, HEMT is a device using which you
can expect to get high values of
transconductance without actually any
need to have a high level of doping.
HEMT
Now, how it is achieved ?
By fabricating a special structure
Channel will
be along the
GaAs well
(perpendicular
to this figure)
Also Called MODFET
HEMT ( Basic working)
*Mobile Electrons generated by the Donors in the
AlGaAs diffuse into the small band gap GaAs.
•These electrons are prevented from returning to the
AlGaAs because of the Potential Barrier at the
AlGaAs/GaAs interface.
•This potential barrier is like a Triangular Well
•Electrons in this well form a Two-Dimensional Electron
Gas.
HEMT ( Basic working)
HEMT (Advantages)
•As a result Mobilities above 250,000 cm2/V-s at 77 k
and 2,000,000 cm2/V-s at 4 k can be achieved.
Higher mobility
•Maximum electron velocity in GaAs
•Smoother interfaces at AlGaAs / GaAs compared to
Si/SiO2 interface.
•Higher cutoff frequency
•Devices with fast acess times.
Short Channel Effects
When channel length is typically lesser
than 1 μm, some additional effects
come into play .
e.g. High field effects occur, when 1 V
appears across a channel length of
1μm ( 10-4cm) , giving an electric field of
10 KV / cm.
Short Channel Effects ( Contd.)
μ – Low field
mobility
Short Channel Effects ( Contd.)
If we assume that the electrons passing through
the channel drift with a constant saturation
velocity vs,
I D  qnvs A  qN d vs Zh
Because
vx
J  E  qn n .E  q.n. E
E
Short Channel Effects ( Contd.)
Saturated current follows the velocity saturation and
does not require the true pinch off in the sense of
depletion regions meeting at some point in the
channel.
In the saturated velocity case, the transconductance
gm is essentially constant. So, ID – VD curves are
more evenly spaced.
Short Channel Effects ( Contd.)
Velocity saturation effect
Pinch off
MISFET (Metal Insulator Semiconductor
Field Effect Transistor)
General Structure
Can U try to draw energy band diagram for n - MISFET
MISFET
Energy Band diagram
Figure 6—11
n-channel MOSFET cross-sections under different operating conditions: (a) linear
region for VG > VT and VD < (VG -VT); (b) onset of saturation at pinch-off, VG > VT and
VD = (VG -VT); (c) strong saturation, VG > VT and VD > (VG - VT ).
MISFET
Characteristic Curve
MISFET
Depletion mode
Always On
devices
Enhancement mode
Controlled
through gate
The Ideal MOS Capacitor
To draw the energy band
diagrams for MOS structure
under different conditions
Condition for strong
inversion
The Ideal MOS Capacitor ( Contd.)
# Surface effects in MOS capacitance are complicated.
We define a new term
Modified work function qφm for Metal Oxide interface .
From metal Fermi level to the oxide CB.
Same way, we define modified work function for SC as
well i.e. qφS
The Ideal MOS Capacitor ( Contd.)
Ideal MOS Structure, we assume that
m  SC
Can we try to draw the resulting energy
band diagram for a MOS capacitance ?
The Ideal MOS Capacitor ( Contd.)
Something important
We define a potential φ at any point ‘x’ measured
relative to the equilibrium position of Ei
Energy qφ tells us the extent of band bending at
‘x’ and qφS represents the band bending at the
surface.
The Ideal MOS Capacitor ( Contd.)
Band diagram for ideal MOS structure at equilibrium
Observation
C
No band
bending at the
surface .
Hence φS = 0
The Ideal MOS Capacitor ( Contd.)
Band diagram for ideal MOS structure at equilibrium
( along with application of negative voltage )
We effectively
deposit a – ve
charge on the metal
- ve voltage will
cause hole
accumulation in the
p – type carrier near
the surface.
Observation
Hence φS < 0
Band bending at the surface is away from Ei .
The Ideal MOS Capacitor ( Contd.)
Band diagram for ideal MOS structure at equilibrium
( along with application of positive voltage )
We effectively
deposit a + ve
charge on the metal
+ ve voltage will
cause electron
accumulation in the
p – type SC near
the surface.
Observation
Band bending at the surface is toward Ei. Leads
to depletion at the surface and Hence φS > 0
The Ideal MOS Capacitor ( Contd.)
Band diagram for ideal MOS structure at equilibrium
(along with application of large positive voltage)
We effectively
deposit a + ve
charge on the metal
Large + ve voltage
will cause large
electron
accumulation in the
p – type SC near
the surface.
Observation
Band bending at the surface is toward Ei . Here
φS > 0 and is larger than φF. Hence inversion happens.
The Ideal MOS Capacitor ( Contd.)
We effectively deposit a + ve charge on the
metal
Large + ve voltage will cause large electron
accumulation in the p – type SC near the
surface.
Region near the SC surface has conduction properties
typical of n –type material with an electron concentration
given by
( E  E ) / kT
no  ni e
F
i
The Ideal MOS Capacitor ( Contd.)
Best criterion for
strong inversion
is that the surface
should be
strongly n – type
as the substrate
is p type. That
means Ei should
lie as far below EF
at the surface as
it is above EF far
from the surface.
The Ideal MOS Capacitor ( Contd.)
Best criterion for strong inversion is that the surface
should be strongly n – type as the substrate is p
type. That means Ei should lie as far below EF at
the surface as it is above EF far from the surface.
And this occurs when
kT N a
 S (inv )  2 F  2 ln
q
ni
The Ideal MOS Capacitor ( Contd.)
Strong Inversion
kT N a
 S (inv )  2 F  2 ln
q
ni
It means that for getting strong inversion at less
amount of applied potential, we will need to start
with a basic material with less doping
concentration !
The Ideal MOS Capacitor ( Contd.)
The electron and hole concentrations are related to the
potential φ (x) .
Equilibrium electron concentration is
no  ni .e
( E F  Ei ) / kT
 ni .e
 q F / kT
Electron concentration at any point ‘x’ will be given by
n  ni .e
 q ( F  ) / kT
 no .e
q / kT
The Ideal MOS Capacitor ( Contd.)
Similarly for holes :
po  ni .e
( Ei  E F ) / kT
 ni .e
And
p  po .e
 q / kT
q F / kT
We combine all these equations with Poisson’s
equation and the usual charge density
expression to solve for φ(x)

 ( x)

2
x
s
2
 ( x )  q ( N  N  p  n)

d

a
We need to find the total integrated charge per unit area,
Qs , as a function of the surface potential, φs.
So using expressions for no, n, po and p in the above
equations ,we get :
 q
q


     
q
kT
kT



p
(
e

1
)

n
(
e
 1)
 
 o
o
2
x
x  x 
s 

2
Where


x
Is the electric field ‘E’ at depth x
Integrating above equation from the bulk ( where bands
are flat, the electric fields are zero and the carrier
concentrations are determined solely by the doping),
towards the surface, we get

x
(
0



q
q
q
)d ( )    [ p0 ( exp( 
)  1)  n0 (exp(
)  1)]d
x
x
s 0
kT
kT
After integration :
E (
2
2kTpo
s
no
q
q
q
q
)[(exp( 
)
 1) 
(exp(
)
 1)]
kT
kT
po
kT
kT
A particular important case : At the Surface (x=0) where
surface electric field is ,
Es 
q
q
n
q
q
2kT
[(exp  ( s )  s  1)  o (exp( s )  s  1)]1 / 2
qLD
kT
kT
p0
kT
kT
Where, LD is called Debye Screening Length and
defined as
 s kT
LD 
q 2 po
LD 
 s kT
q 2 po
*Debye Length gives an Idea of the distance Scale in
which charge imbalances are Screened or Smeared out.
LD depends inversely on doping because the higher the
carrier concentration, the more easily screening takes
place.
By Using Gauss’s Law , we relate the integrated space
charge per unit area to the electric displacement,
keeping in mind that the electric field or displacement
deep in the substrate is zero.
Qs= -εsEs
Here QS is the space charge density per unit area.
Variation of Space-charge Density with
At small value of
Surface Potential s
potential, the ratio
When
surface
potential is zero,
the
net
space
charge is zero.
This is because the
fixed
dopant
charges
are
cancelled by the
mobile
carrier
charges at the flat
band.
of minority to
majority carriers
is very small and
hence the charge
density increases
steadily, which is
case of weak
inversion,
but
after the +ve
potential
is
increased further,
strong inversion
occurs and hence
charge
density
rises sharply.
9
When the surface potential is –ve, it attracts and forms an accumulation layer of
the majority carrier holes at the surface. Accumulation space charge increases
very strongly with negative surface potential
Charge density distribution in the
ideal MOS capacitor in inversion
Using the
depletion
approximation
Electric Field and Charge Density
Using Gauss’ law,(The positive charge Qm on the
metal is balanced by negative charge Qs on the
S.C.)
Qm  Qs  Qd  Qn 
 qN aW  Qn
Qm and Qs are the surface charge per unit area on
the metal and semiconductor respectively. Qd and
Qn are Depletion layer charge and charge due to
inversion region respectively.
As obvious from the potential distribution diagram, an
applied voltage ‘V’ appears partially across the insulator
( Vi ) and partially across the depletion region of the
semiconductor
V= Vi + Φs , where Vi= -(Qs/Ci)
Vi
Qs / Ci
(Qd  Qn ) / Ci
Ei 


d
d
d
where Ci or Cox is the capacitor per unit area of the
insulator and is given by, Ci = i /d.
Also, the width of the depletion region, as in a n+p
junction, will extend entirely in the p-region and will be,
W 
2s
qN a
MOS with Rpermit 11.8 and Na 1016 gives Wmax as .301um as ΦS is
2ΦF
MOS with Rpermit 11.8 and Na 1016 gives W max as .301μm as ΦS
is 2ΦF
Max. Depletion width is Wm, beyond this further
increases in voltage result in stronger inversion rather
than in more depletion.
2s inv .
Wm 
2
qN a
Where
 kT  N a
 2  ln
 q N a  ni
kT N a
 S (inv )  2 F  2 ln
q
ni
ΦF is .347V for Na 1016 at 300K
The charge per unit area in the depletion
region Qd at strong inversion is given as :
Qd  qN aWm  2( s qN a F )
1/ 2
Threshold Voltage
For strong inversion to take place, the applied voltage
should be large enough to create the depletion charge
as above and also create surface potential, s(inv.) =
2F. This voltage called threshold voltage,VT is given by,
Qd
VT  
 2 F
Ci
Ideal Case
The threshold voltage represents the minimum voltage
required to achieve strong inversion.
Threshold Voltage ( contd.)
We assume here that the charge at the semiconductor
surface at inversion is mostly due to the depletion
charge Qd.
The capacitance of the MOS capacitor varies depending
on whether the MOS operates in the accumulation,
depletion or inversion regions.
Total MOS Capacitance
The total capacitance is a series combination of constant
insulator capacitance, Ci and voltage dependent
semiconductor capacitance, Cs where
Determined
 i . A and
dQ
s
from the slope
Ci 
Cs 
d
d s
of the Qs Vs Φs
plot.
Hence, overall MOS capacitance becomes Voltage
Dependent
Accumulation region
*In ACCUMULATION : The slope is very steep and
Hence Cs is Very High.
*Means the Series Capacitance in ACCUMULATION is
Basically the INSULATOR CAPACITANCE (Ci).
*The MOS structure appears almost like a parallel-plate
capacitor which is dominated by the insulator capacitor.
Depletion Region
*As the voltage becomes less negative i.e. surface of
S.C Depleted Means Depletion-Layer capacitor
Cd=(εs/W) is added in series with oxide capacitor.
Total capacitor C={(CiCd)/(Ci+Cd)}
*As W Increases, the Capacitance Decreases until
finally Inversion is reached at VT.
CV Curve for MOS Capacitance
Effect of High or Low frequency
measurements
After inversion is reached, the small signal capacitance
depends on whether the measurements were made at
high frequency ( typically 1MHz) or low frequencies (
typically ~ 1 – 100 Hz ), where high or low are with
respect to the generation – recombination rate of the
minority carriers in the inversion layer. If the gate voltage
is varied rapidly, the charge in the inversion layer can
not change in response, and thus does not contribute to
the small signal ac capacitance. Hence the
semiconductor capacitance is at a minimum,
corresponding to a maximum depletion width.
Effect of High or Low frequency
measurements
On the other hand, if the gate bias is changed slowly,
there is time for minority carriers to be generated in the
bulk, drift across the depletion region to the inversion
layer, or go back to the substrate and recombine.
Now the semiconductor capacitance using the same
eqn. for CS is very large, because we saw that the
inversion charge increases exponentially with φS.
Hence, the low frequency MOS series capacitance in
strong inversion is basically Ci once again.
Effect of High or Low frequency
measurements( accumulation)
We get a high capacitance both at high and low
frequencies, because the majority carriers in the
accumulation layer can respond much faster than
minority carriers.
Effect of High or Low frequency
measurements
In MOSFETs, high frequency capacitance is
high( = Ci ) in strong inversion,
Because, now the inversion charge can flow in readily
and very fast from the source / drain regions rather than
having to be created by generation – recombination in
the bulk.
MOS C – V Analysis
•Used to extract the various parameters of MOS
device
•Type of substrate
•Thickness
•Substrate doping
•Threshold voltage (VT)
•Fast interface state density (Dit)
Non Ideal MOS
• So far, we have discussed MOS characteristics
making some assumptions - calling it “ideal”.
– Assumed that the M = S , i.e. the bands are flat when no
voltage is applied.
– Assumed that the oxide and oxide-semiconductor interface
are free of charges.
• These assumptions do not hold good in an actual
MOS device, and we have to consider the deviations
from the ideal case. For the purpose of discussions,
we call these as “real”.
Effect of real surfaces
*Using POLYSILICON Instead of METAL , Gives
Departure from Ideal Case.
•Due to that threshold Voltage and other properties are
strongly affected.
•The difference in the work functions of Polysilicon and
Silicon depends on the Substrate Doping.
•Heavily Doped Polysilicon acts like a Metal gate and
there is inevitably charges at the silicon-silicon oxide
interface and within the oxide.
Work function difference
*We assumed in case of ideal MOS that m = s.
But, ms = m - s depends upon the kind of doping
used
Can U draw
the resulting
energy band
diagram ?
Resulting energy band diagram
Typical Observation
•If Φms is sufficiently negative, An Inversion Region can
exist with no external applied Voltage.
• In this case to obtain the Flat Band Condition , One
should apply a negative voltage to the Metal (VFB= Φms).
Qd
VT  
 2 F
Ci
Remind urself this
equation !
Interface Charge
Qm Mobile
ionic charge
Due to sodium ions ( +ve charges in Oxide
and hence – ve charges in SC). More
problematic due to their mobile nature.
Due to imperfections in the SiO2
Qot Oxide
trapped
charge
Qf Oxide
Near the interface is a transition layer
fixed charge (SiOx). This charge depends on oxidation
rate and orientation.
Qit Interface Due to sudden termination of SC crystal
trap charge lattice at the oxide interface
Interface Charge
Relief
For carefully treated Si – SiO2
interfaces, typical charge densities due
to Qit and Qf are about 1010 charges /
cm2 for samples with <100> surfaces.
With <111> surfaces, this density is
about a factor of 10 higher.
For simplicity, we include the various oxide and interface
charges in an effective positive charge at the interface
(Qi) ( C / cm2).
The effect of this charge is to induce an equivalent
negative charge in the semiconductor. Thus an
additional component must be added to the flat band
voltage.
VFB = ms – Qi / C i
Since the difference in work function and
the positive interface charge both tend to
bend the bands down at the semiconductor
surface, a negative voltage must be applied
to the metal relative to the semiconductor to
achieve the flat band condition.
Threshold Voltage
Earlier, we have written the equation for threshold
voltage to achieve a condition of strong inversion
as
( for ideal case)
Qd
VT  
 2 F
Ci
Threshold Voltage
Now, after these modifications and due to effect
of a real conditions, this equation will needed to
be modified with addition of new value of VFB.
Hence
VT = ms – Qi / C i - Qd / Ci + 2 F
Equation is valid for both n – type and p- type
substrates, if appropriate signs are included for each
term.
Sign of different terms in VT
Always - ve
Charge in depletion region is
–ve for ionized acceptors ( p
– type substrate , n – channel
device) and is +ve for ionized
donors ( n – type substrate, p
channel)
F , defined as ( Ei – EF) / q
in the neutral substrate can
be positive or negative
depending upon the
conductivity type of the
substrate
Negative threshold voltages for typical p –
channel devices. But for n channel devices, we
may have +ve or – ve threshold voltages
depending upon the relative values.
What + ve or -ve VT means essentially ?
In a p channel device, we expect to apply a negative
voltage from metal to SC in order to induce the + ve
charges in the channel. So, - ve voltage must be larger
than VT to get strong inversion.
In n channel, U apply a positive voltage to get strong
inversion.
Application of no voltage means channel is already there
and U need to apply –Ve voltage to make the device off!
Variation of VT with substrate
doping
MOS C – V Plot
MOS C – V Analysis
• Substrate type :
No problem
Just by having a look at the shape of CV
plot
p type substrate
n type substrate is
just mirror image of
this
MOS C – V Analysis
Thickness determination
Ci   i / d
*The oxide thickness can be determined in
ACCUMULATION or STRONG INVERSION from above
relation.
MOS C – V Analysis
Substrate doping
**Measurement of minimum MOS capacitance Cmin is
required to determine the Substrate Doping.
Cmin is series combination of Oxide Capacitance and the
minimum depletion capacitance (Cdmin=εs/Wm) where Wm
is maximum depletion width.
2s inv .
Wm 
2
qN a
 kT  N a
 2  ln
 q N a  ni
MOS C – V Analysis
What next ? Ultimate aim is find value of VT
** IF the Substrate doping is known the Flat Band
capacitance can be obtained. The SC capacitance at
flatband CFB is determined from the Debye Length
capacitance
Cdebye=
2
LD
s
Where Debye length depends on
Doping
LD 
 s kT
q 2 po
MOS C – V Analysis
*The overall MOS flatband Capacitance is the Series
Combination of Cdebye and Cox
•By knowing CFB we can determine the VFB.
•And hence all the terms required to find threshold
voltage is determined as
VT = ms – Qi / C i - Qd / Ci + 2 F
MOS C – V Analysis
The threshold voltage does not correspond to minimum
point on the C-V curve but slightly higher value than
Cmin. This particular Capacitor is equal to series
combination of Cox and 2Cdmin.rather than the series
combination of Cox and Cdmin
For simplicity, we include the various oxide and interface
charges in an effective positive charge at the interface
(Qi) ( C / cm2).
The effect of this charge is to induce an equivalent
negative charge in the semiconductor. Thus an
additional component must be added to the flat band
voltage.
VFB = ms – Qi / C i
Since the difference in work function and
the positive interface charge both tend to
bend the bands down at the semiconductor
surface, a negative voltage must be applied
to the metal relative to the semiconductor to
achieve the flat band condition.
Threshold Voltage
Earlier, we have written the equation for threshold
voltage to achieve a condition of strong inversion
as
( for ideal case)
Qd
VT  
 2 F
Ci
Threshold Voltage
Now, after these modifications and due to effect
of a real conditions, this equation will needed to
be modified with addition of new value of VFB.
Hence
VT = ms – Qi / C i - Qd / Ci + 2 F
Equation is valid for both n – type and p- type
substrates, if appropriate signs are included for each
term.
Sign of different terms in VT
Always - ve
Charge in depletion region is
–ve for ionized acceptors ( p
– type substrate , n – channel
device) and is +ve for ionized
donors ( n – type substrate, p
channel)
F , defined as ( Ei – EF) / q
in the neutral substrate can
be positive or negative
depending upon the
conductivity type of the
substrate
Negative threshold voltages for typical p –
channel devices. But for n channel devices, we
may have +ve or – ve threshold voltages
depending upon the relative values.
What + ve or -ve VT means essentially ?
In a p channel device, we expect to apply a negative
voltage from metal to SC in order to induce the + ve
charges in the channel. So, - ve voltage must be larger
than VT to get strong inversion.
In n channel, U apply a positive voltage to get strong
inversion.
Application of no voltage means channel is already there
and U need to apply –Ve voltage to make the device off!
MOS C – V Analysis
Determination of fast interface states
Term fast
interface state
refers to the fact
that these defects
can change their
charge state
relatively fast in
response to
changes of the
gate bias.
MOS C – V Analysis
Determination of fast interface states
Fast interface states give rise
to capacitance, which is in
parallel with the depletion
capacitance in the channel(
and hence is additive) and this
combination is in series with
the insulator capacitance Ci
Dit =
Ci .C HF
1  Ci C LF


q  Ci  C LF Ci  C HF
 2 1
cm eV

MOSFET Current
The applied gate voltage is given by,
Qs
Qd  Qn
VG  VFB    s  VFB 
 s
Ci
Ci
QS = Qd ( fixed charge in the depletion region ) + Qn (
mobile charge)
MOSFET Current
Solving for Qn , we get


Q d 
  Ci VG  VT 
Q n  Ci VG   VFB  s 
C i 


Where Qn is mobile charge.
MOSFET Current
Now, when a voltage VD is applied, then there is
voltage rise from the source to each pt. ‘x’ in the
channel. So, the potential s ( x) is that required
to achieve strong inversion plus the voltage Vx.
Hence we get modified eqn for Qn as:


1
Qn  Ci VG  VFB  2 F  Vx 
2q s N a 2 F  Vx 
Ci


MOSFET Current
Neglecting the variation of Qd with x, we get
Q n x   Ci VG  VT  Vx 
This equation describes the mobile charge in the
channel at point x
Conductance of small element of width dx,
 n Qn Z
Gx  
dx
Where Z is width of the channel and
n
is surface electron mobility, indicating the fact that
mobility in a thin region is not the same as in the bulk
material.
At point ‘x’ , we have
 I D dx  n ZQ n x dVx
Integrating from source to drain
L
VD
0
0


I
dx


ZC
V

V

V
dV
D
n
i
G
T
x
x


ID
n ZCi

L
Where
n
L
1 2

 VG  VT VD  VD 
2 

ZCi  k n
Determines the conductance and transconductance of the
n-channel MOSFET
I D Z
conductance g 
 nCi VG  VT 
VD L
For VD << VG VT
VD(sat.) = VG - VT
Saturation condition for MOSFET
n ZCi
2
VG  VT 
I D sat. 
2L
Drain Current in Saturation Region
Mutual transconductance
gm 
I D sat.
VG
Z
 n Ci VG  VT 
L
Drain I-V Characteristics plots
Transfer characteristics
This decrease is due to two factors (i)
Degradation of the effective channel mobility as a
function of increasing transverse electric field
across the gate oxide (ii) Source / drain
resistance.
The eqn. for ID (sat.) shows a quadratic dependence of ID on VG, we get a linear behavior by
plotting not the drain current, but rather the square root of ID as a function of VG. In this case the
intercept gives us the threshold voltage in the saturation region, VT ( sat). Due to effects like
DIBL for short channel MOSFETs, the VT (sat) can be lower than VT (lin), while the long channel
values are similar.
Short channel MOSFET I – V
characteristics
The effective channel mobility decreases with
increasing
transverse
electric
field
perpendicular to the gate oxide. Furthermore,
for very high longitudinal electric fields in the
pinch off region, the carrier velocity saturates.
Short channel MOSFET I – V
characteristics (Contd.)
For short channel lengths, the carriers travel
at the saturation velocity over most of the
channel. In that case the drain current is given
by the width times the channel charge per unit
area times the saturation velocity.
ID (sat ) ~ Z Ci ( VG - V
T
) vs
Short channel MOSFET I – V
characteristics (Contd.)
ID (sat ) ~ Z Ci ( VG - V
T)
vs
As a result, the saturation drain current does not
increase quadratically with (VG _- V T ), , but rather
shows a linear dependence.
Due to the advances in Si device processing,
particularly photolithography, MOSFETs used in
modern integrated circuits tend to have short
channels and are commonly described by above eqn.
Figure 6—30
Inversion layer electron mobility versus effective transverse field,
at various temperatures. The triangles, circles and squares refer to
different MOSFETs with different gate oxide thicknesses and
channel dopings. (After Sabnis and Clemens, IEEE IEDM, 1979).
Figure 6—31
Determination of effective transverse field. Idealized charge distribution and
transverse electric field in the inversion layer and depletion layer, as a function
of depth in the channel of a MOSFET. The region to which we apply Gauss’s
law is shown in color.
Figure 6—34
Thin oxide in the gate region and thick oxide in the
field between transistors for VT control (not to scale).
Control of threshold voltage
Threshold voltage can be controlled by manipulating
all the terms involved in expression for VT up to
some extent. Mainly , we can do so by
(i) Choice of suitable gate electrode
(ii) Control of Ci
(iii)Threshold adjustment by ion implantation.
Control of threshold voltage
*Since Ci=(εi / d) and Hence A
THIN – OXIDE Layer in the Gate
Region is used to increase Ci. .
*The Value of Ci can also be
controlled by controlling εi.
Control of threshold voltage
*Precise Control of Threshold Voltage is
Possible By Ion Implantation Because By
Ion Implantation precise amount of
impurities can be introduced.
*The
Negatively Charged Boron
Acceptors Serve to reduce the effects of
the Positive Depletion Charge (Qd) in nsubstrate.As a result, threshold Voltage
Becomes less negative.
.
*A Shallow Boron Implant into the p-substrate
of n-channel transistor can make threshold
voltage positive.
Implantation Energy required for Shallow
threshold
Voltage adjustment is 50-100Kev (low) and
low Dose and typically implantation time of 10
sec for each wafer.
Figure 6—35
Adjustment of VT in a p-channel transistor by boron implantation: (a) boron ions
are implanted through the thin gate oxide but are absorbed within the thick oxide
regions; (b) variation of implanted boron concentration in the gate region — here
the peak of the boron distribution lies just below the Si surface.
Typical variation of VT for a p channel device with
increased implanted boron dose
Substrate bias effects
Till now, we have assumed that the
source and the bulk of the transistor
were tied to ground. But, what happens, if
the bulk voltage of an n channel FET
drops below the source voltage.
Substrate bias effects
To understand the effect, suppose VS = VD =
0 and VG is some what less than the
threshold voltage, so that a depletion region
is formed under the gate, but no inversion
layer exists. As VB becomes more negative,
more holes are attracted to the substrate
connection, leaving a large negative charge
behind, Hence the depletion region becomes
wider.
Substrate bias effects
Now we very well know that the threshold
voltage is some what a function of the total
charge in the depletion region because the
gate charge must mirror Qd before an
inversion layer is formed. Thus as VB drops,
Qd increases and hence threshold voltage
also increases. This is called the body effect
and some of the parameters have to modified
so as to include this effect.
Threshold voltage dependence on substrate bias resulting from
application of a voltage VB from the substrate to the source.
Subthreshold Characteristics
If we look at the drain current expression,
it appears that the current abruptly goes to
zero as soon as VG is reduced to VT. In
reality, there is still some drain conduction
below threshold and this is known as the
subthrehold conduction.
Subthreshold Characteristics
This current is due to the week inversion
in the channel between flat band and
threshold ( for band bending between
zero and 2F ), which leads to a diffusion
current from source to drain.
Subthreshold Characteristics
From the modified equation for ID , we see
that it depends exponentially on gate bias
VG. So, if we plot ln ID as function of gate
bias, we should get a linear behavior in the
subthreshold regime. The slope of this line is
known as the subthreshold slope, S, which
has typical values of ~ 70 mV / decade at
room temperature.
Semi log plot
of ID vs VG
Consequences to be
taken care of
For a very small gate voltage, the subthreshold
voltage, the subthreshold current is reduced to the
leakage current of the source / drain junctions. This
determines the off state leakage current.
It highlights the significance of having high quality
Source and drain junctions.
Consequences to be
taken care of
If V T is too low , then the transistor can not
be turned off fully at VG = 0.
If VT is too high, then one sacrifices drain
current, which depends upon the difference
between the power supply voltage and the VT.
Equivalent Circuit of a MOSFET
When we attempt to draw an equivalent circuit
of a MOSFET in addition to the intrinsic
MOSFET itself, there are a variety of parasitic
elements associated with it.
Equivalent Circuit of a MOSFET
Figure 6—40
Determination of length reduction and source/drain series resistance in a
MOSFET. The overall resistance of a MOSFET in the linear region is
plotted as a function of channel length, for various substrate biases. The x
mark data points for three different physical gate lengths L.
The gate capacitance Ci is the sum of the
distributed capacitances from gate to the source
end of the channel (CGS) and the drain end ( CGD ).
In addition , we have an overlap capacitance from
the gate to source ( COS) and gate to drain (COD).
COD is also known as the Miller capacitance. Besides
this, there are p-n junction depletion capacitances
associated with the source ( CjS ) and drain (CjD).
*COS AND COD are Miller-Overlap Capacitance Due
to Overlap between the Gate and Source/Drain
regions.
*This Capacitance (COD) is particularly problematic
because it provides the Feedback path between
output drain terminal and input gate terminals.
*Miller capacitance can be measured at high
frequency keeping gate voltage=0 so that an
inversion layer is not formed in the channel.Thereby
most of the measured capacitance between gate and
drain is due to the miller capacitance, rather than the
gate capacitance Ci.
MOSFET Scaling and Hot
electron effects
If lateral dimensions such as the channel length and
width are reduced by a factor of ‘K’, so should the
vertical dimensions such as source/drain junction
depths (xj) and the gate insulator thickness.
Scaling in MOSFET
•
•
•
•
•
•
•
•
•
L,Z
d, xj
Impurity concent
I ,V
Current density
Ci
Transconductance
Ckt delay time
Power dissipation
1/K
1/K
K
1/K
K
K
1
1/K
1/K2
MOSFET Scaling and Hot
electron effects (Contd.)
If we simply reduce the dimensions of the device
and keep the power supply voltages the same, the
internal electric fields in the device would increase.
For ideal scaling , the power supply voltages should
also be reduced to keep the internal electric fields
reasonably constant from one technology generation
to the next.
MOSFET Scaling and Hot
electron effects (Contd.)
Scaling means, u might be needing to reduce the
depletion layer widths as well !!
Can u suggest any methodology???
Scaling of depletion widths can be achieved
indirectly by scaling up doping concentrations.
MOSFET Scaling and Hot
electron effects (Contd.)
Unfortunately, in practice, power supply
voltages are not scaled hand in hand with the
device dimensions partly because of the other
system related constraints. A variety of
problems then arise which are generically
known as hot electron effects and short
channel effects.
MOSFET Scaling and Hot
electron effects (Contd.)
Unfortunately, in
practice, power
supply voltages
are not scaled
hand in hand with
the device
dimensions partly
because of the
other system
related constraints.
A variety of
problems then
arise which are
generically known
as hot electron
effects and short
channel effects.
MOSFET Scaling and Hot
electron effects (Contd.)
When an electron travels from the source to the
drain along the channel, it gains kinetic energy at the
expense of electrostatic potential energy in the
pinch off region and becomes ‘hot’ electron. At the
conduction band edge, the electron has potential
energy only; as it gains more kinetic energy, it
moves higher up in the conduction band.
MOSFET Scaling and Hot electron
effects (Contd.)
A few of the electrons can become energetic enough to
surmount the 3.1 eV potential barrier between the Si
channel and the gate oxide. Some of these injected hot
electrons can go through the gate oxide and be
collected as the gate current, there by reducing the
input impedance. More importantly some of these
electrons can be trapped in the gate oxide as fixed
oxide charges. According to eqn for threshold voltage,
this increases the flat band voltage and hence the
threshold voltage.
MOSFET Scaling and Hot electron
effects (Contd.)
The solution to this problem is to use what is known
as a lightly doped drain (LDD). This way, the
depletion width at the reverse biased drain channel
junction is increased and the electric field is
reduced.
Figure 6—42
Hot carrier degradation in MOSFETs. The linear region transfer
characteristics before and after hot carrier stress indicate an increase of VT
and decrease of transconductance (or channel mobility) due to hot
electron damage. The damage can be due to hot electron injection into the
gate oxide which increases the fixed oxide charge, and increasing fast
interface state densities at the oxide-silicon interface (indicated by x).
Figure 6—43
Substrate current in a MOSFET. The substrate current in n-channel MOSFETs due to impact-generated
holes in the pinch-off region, as a function of gate bias. The substrate current initially increases with VG
because of the corresponding increase of ID. However, for even higher VG, the MOSFET goes from the
saturation to the linear region, and the high electric fields in the pinch-off region decrease, causing less
impact ionization. (After Kamata, et. al. , Jpn. J. Appl. Phys., 15 (1976), 1127.)
MOSFET Scaling and Hot electron
effects (Contd.)
Hot carrier effects are less problematic for holes in
the p-channel MOSFETs than for electrons in the n
– channel devices for two reasons.
MOSFET Scaling and Hot electron
effects (Contd.)
The channel mobility of holes is approximately half of that
of electrons, hence for the same electric field, there are
fewer hot holes than hot electrons. Unfortunately, the lower
hole mobility is also responsible for lower drive currents in
p-channel than in n – channel. Also the barrier for hole
injection in the valence band between silicon and oxide is
higher (5eV) than for electrons in the conduction band.
Hence , while LDD is mandatory for n – channel, it is not
often used for p – channel devices.
Drain Induced
Barrier
lowering
Drain Induced Barrier lowering
(Contd.)
If small channel length MOSFETs are not scaled
properly, and the source/drain junctions are too
deep or the channel doping is tooo low, there can
be unintended electrostatic interactions between
the source and the drain known as Drain Induced
Barrier Lowering ( DIBL). This leads to the punch
through leakage or breakdown between the source
and the drain, and loss of gate control.
Drain Induced Barrier lowering (Contd.)
As the drain bias is increased, the conduction band
edge in the drain is pulled down, and the drain channel
depletion width expands. For a long channel MOSFET,
the drain bias does not affect the source to channel
potential barrier, which corresponds to the built in
potential of the source channel p-n junction. Hence
unless, the gate bias is increased to lower this potential
barrier, there is little drain current. On the other hand
for short channel MOSFET, as the drain bias is raised
and the conduction band edge in the drain is pulled
down, the source channel potential is lowered due to
DIBL.
Drain Induced Barrier lowering
(Contd.)
Solutions to DIBL :
The source drain junctions must be made
sufficiently shallow (i.e scaled properly) as the
channel lengths are reduced, to prevent DIBL.
Drain Induced Barrier lowering
(Contd.)
Secondly channel doping must be made sufficiently
high to prevent the drain from being able to control
the source junction. This is achieved by what is
known as an anti – punchthrough implant in the
channel. ( which can have undesirable consequences
such as raising the VT or the body effect), a localized
implant is done only near the source / drains. These
are known as halo/ pocket implants. The higher
doping reduces the source/ drain depletion widths
and prevents their interaction.
Gate Induced drain leakage
As the gate voltage is reduced below VT, the
subthreshold current drops and then bottoms out
at a level determined by the source/drain diode
leakage. However, for even more negative gate
biases, we find that the off state leakage current
actually goes up as we try to turn off the
MOSFET more for high VD. This is known as Gate
induced Drain leakage.In the diagram, we show
the band diagram as a function of depth in the
region, where the gate overlaps the drain junction.
Gate Induced drain leakage
As the gate is
more –ve, a
depletion region
forms in the n –
type drain. Since
the drain doping
is high, the
depletion widths
.
tend to be
narrow.
Gate Induced drain leakage
If the band bending is more than the bandgap Eg
across a narrow depletion region, the conditions are
conducive for band to band tunneling in this region,
thereby creating electron hole pairs. The electrons
then go to the drain as GIDL. It must be emphasized
that this tunneling is not through the gate oxide, but
entirely in the silicon region.
Short channel and narrow width effect
If we plot the threshold voltage as a function of
channel length in MOSFETs, we find that VT
decreases with ‘L’ for very small geometries. This
effect is called the short channel effect. And is
some what similar to DIBL.
Short channel and narrow
width effect (Contd.)
The mechanism is due to something called Charge
sharing between the source / drain and the gate.
From the equation for the threshold voltage, we
notice that one of terms is the depletion charge
under the gate.
Short channel and narrow
width effect (Contd.)
As the channel lengths are reduced, the
shared charge becomes a larger fraction of the
total and this results in a VT roll off as a
function of ‘L’. This is important, because it
is hard to control the channel lengths
precisely in manufacturing. The channel length
variations then lead to problems with VT
control.
Roll – off of VT with decreasing channel length ,
and increase of VT with decreasing width
Narrow width effect in a MOSFET
Gate Induced drain leakage
For GIDL to occur, the drain doping level should be
moderate ( ~ 1018 cm-3 ) . If it is much lower than
this, the depletion widths and tunneling barriers are
too wide. On the other hand, if the doping in the
drain is very high, most of the voltage drops in the
gate oxide , and the band bending in the Si drain
region drops below the value Eg.