Microelectronics Reliability 127 (2021) 114412
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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel
Review paper
Development of low temperature Cu–Cu bonding and hybrid bonding for
three-dimensional integrated circuits (3D IC)
Han-Wen Hu, Kuan-Neng Chen *
Department of Electronics Engineering, National Yang Ming Chiao Tung University, Hsinchu 300, Taiwan
A R T I C L E I N F O
A B S T R A C T
Keywords:
3D integration
Low temperature bonding
Cu bonding
Hybrid bonding
Thermal-compression bonding (TCB) is the key technology to ensure vertical chip (or wafer) stacking in threedimensional (3D) integration with higher I/O density than conventional soldering technology. For different TCB
approaches, copper (Cu) to Cu bonding has always been the preferred candidate due to the excellent electrical
and thermal properties of Cu, high mechanical strength of bonding interface, as well as compatibility and cost
consideration in the packaging fabrication. However, high thermal budget of the bonding process caused by
oxidation of Cu leads to issue of wafer warpage, bonding misalignment, and compatibility with back-end-of-line
process. Therefore, this review paper first presents an extensive survey on the advance of low temperature Cubased bonding technologies. In addition, the feasibility of Cu–Cu bonding in the fine pitch applications is
challenged by coplanarity issue of Cu pillars and insufficient gaps for filling. Accordingly, based on the progress
of low temperature Cu–Cu bonding, low temperature Cu/SiO2 hybrid bonding will be introduced as an emerging
bonding technology to solve the coplanarity and filling issue, which can provide the great potential for 3D
integration with ultra-high density of interconnection.
1. Introduction
During the decades, miniaturization of integrated circuits (ICs) is
dominated by the scaling of transistors following Moore's law, and the
feature size of transistors has approached to physical limits [1]. At the
same time, the continuous scaling of transistors drives the explosive
growth in the density of metal layers, inducing a great increase of in­
terconnects delay [2,3]. Thus, scaling down transistor dimensions to
promote IC performance introduces challenges in recent years due to the
presence of physical limits and interconnect bottleneck. As a result,
three-dimensional integrated circuit (3D IC), the prominent alternative
technology to solve the issues above, has attracted lots of attention and
been studied extensively [4–8]. By vertically integrating IC layers in the
same package, 3D IC technology is expected to provide short wire-length
of interconnects, small form factor, low power consumption, and ability
of heterogenous integration.
Bonding is the key to vertical stacking of chips or wafers in 3D IC, and
solder interconnect is the most commonly used bonding technique due
to its low cost and high throughput [9]. However, solder interconnect is
difficult to meet the extremely high requirement for I/O density and
reliability, which is induced by the rise of emerging industry, such as
artificial intelligence, autonomous driving, internet of things, and 5G
network [10]. Thus, the search for bonding schemes continues, and
Cu–Cu is regarded as the more promising bonding approach for in­
terconnects with higher density and reliability [11–15]. The rigid nature
of Cu prevents bridging of neighbor pads compared to solder joints,
allowing interconnect with finer pitch. In addition, Cu has always been
the most preferred metal as the bonding medium because of its excellent
properties, including impressive electromigration resistance, high elec­
trical and thermal conductivity, low cost, and high compatibility for the
packaging fabrication [16]. Despite the advantages of Cu–Cu bonding,
high thermal budget of the bonding process restricts the range of ap­
plications in the industry. Furthermore, for the fine pitch interconnect
structure, coplanarity of Cu pillars is challenged to meet the requirement
of Cu bonding, and narrow gaps are difficult for injection of underfill
resin. Therefore, this review paper presents an extensive survey on the
advance of low temperature Cu–Cu bonding and low temperature Cu/
SiO2 hybrid bonding in recent years, which has significant efforts for the
development of Cu-based bonding from the perspective of low thermal
budget, high reliability, fine pitch interconnects, and volume
manufacturing.
* Corresponding author.
E-mail address: knchen@mail.nctu.edu.tw (K.-N. Chen).
https://doi.org/10.1016/j.microrel.2021.114412
Received 5 June 2021; Received in revised form 14 October 2021; Accepted 17 October 2021
Available online 10 November 2021
0026-2714/© 2021 Elsevier Ltd. All rights reserved.
H.-W. Hu and K.-N. Chen
Microelectronics Reliability 127 (2021) 114412
2. Development of low temperature Cu–Cu bonding
Cu–Cu TCB is based on the applications of temperature and pressure
during the bonding process to force interdiffusion of Cu at the bonding
interface [17]. However, Cu is easily oxidized by ambient oxygen, and
hence induces a high requirement for bonding temperature about 400 ◦ C
to achieve interdiffusion of Cu [18]. The high thermal budget of the
bonding process may negatively affect performance and reliability of IC
devices, as well as lead to other thermal issues, including wafer warpage,
bonding misalignment, and compatibility with back-end-of-line process
[19]. Consequently, there is the strong motivation to explore methods to
alleviate bonding temperature of Cu–Cu bonding.
2.1. Surface activated Cu–Cu bonding
The surface-activated bonding (SAB) method has been proposed by
Suga's group, which can achieve Cu–Cu bonding with high bonding
strength at room temperature without any annealing steps [20–23]. In
the SAB scheme, ions or fast atom beams (e.g. Ar-FAB) are applied to
activate the bonding surface in an ultra-high vacuum (UHV) environ­
ment, forming chemical bonds for Cu–Cu bonding at room temperature.
Fig. 1 shows the machine developed for the SAB process, involving a
transfer chamber surrounded by chambers with different functions in
the UHV environment (~10− 8 Torr) [20]. After surface activation in the
process chamber, two wafers are brought into contact under a small load
in the preliminary bonding chamber. Then, the prebonded wafers are
bonded by a larger load in the bonding chamber. Using the SAB method,
wafer-level Cu–Cu bonding has been demonstrated to be achieved at
room temperature by an Ar ion beam. In addition to wafer-level Cu
bonding, bumpless Cu electrodes with 6 μm pitch have been successfully
bonded by the SAB method at room temperature, as shown in Fig. 2
[23]. There is no obvious gap observed at the bonding interface between
Cu electrodes in the cross sectional Scanning Electron Microscopy (SEM)
image, and the bonding strength greater than 20 MPa can be obtained.
In spite of the advantages of room bonding temperature and high
bonding strength, manufacturing of SAB in the industry has been chal­
lenged by its high cost and low throughput due to critical requirements
of the UHV environment.
Fig. 2. Cross sectional SEM images of the bumpless Cu electrodes with 6 μm
pitch bonded by SAB at room temperature. [23].
2.2. Cu–Cu bonding with chemical pretreatments
Since the oxidation of Cu accounts for the high bonding temperature,
different chemical pretreatments for removal of oxides before bonding
have been studied to reduce bonding temperature, including hydro­
chloric acid [24,25], citric acid [26], sulfuric acid [27], and acetic acid
[28]. The effects of these four kinds of acid on Cu- Cu bonding have been
analyzed and compared by K. N. Chen's group, showing that citric acid is
the most preferred wet pretreatment to enable successful bonding at
300 ◦ C [29]. In addition, the bonding temperature is shown to be further
reduced to 250 ◦ C by immersion of Cu interface inside composition of
acidic solution, such as HF/H2SO4 and HCl/H2O [30]. In this demon­
stration, the analyses of Focused Ion Beam (FIB) images, as shown in
Fig. 3, indicate that the bonding interface of sample with chemical
pretreatment has the significant improvement, while there are still some
voids observed at the bonding interface. Fig. 3d shows that interfacial
adhesion energy of Cu–Cu direct bond is increased by the different
chemical pretreatment, which can further verify the removal of native
oxides on Cu to assist Cu bonding. Although chemical pretreatment as a
low cost and high throughput process is much more compatible with the
industrial fabrication than the SAB method, achieving high quality
bonding at a lower bonding temperature by chemical pretreatments
faces bottlenecks. It is reasonable because chemical pretreatments may
increase surface roughness of Cu, and the oxidation of Cu is inevitable
during the process from pretreatments to bonding.
2.3. Cu–Cu bonding by creep on (111) surfaces of nanotwinned Cu
The behavior of Cu diffusion on different crystal orientations has
been evaluated, indicating that Cu surface diffusion on (111) surface is
the most beneficial for Cu–Cu bonding [31,32]. Accordingly, electro­
deposition of nanotwinned Cu (nt-Cu) has been developed to form a Cu
film with majority of (111) oriented grains, achieving Cu–Cu bonding
below 250 ◦ C because of the fastest surface diffusivity [33,34]. In Fig. 4,
the corresponding plan-view Electron Backscatter Diffraction (EBSD)
orientation image map and X-ray diffraction (XRD) pattern provide
evidences for the great enhancement of (111) oriented surface. The
(111) oriented grains are observed to occupy about 100% of the surface
area on the nt-Cu film. Furthermore, based on nt-Cu structures, arrays of
ECD Cu bumps with 30 μm in diameter and 80 μm in pitch have been
Fig. 1. Schematic illustration of SAB instruments, involving a transfer chamber
surrounded by chambers with different functions in the UHV environ­
ment. [20].
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Microelectronics Reliability 127 (2021) 114412
Fig. 3. Cross-sectional FIB images of Cu–Cu bonding interface of samples with chemical pretreatment: (a) without wet pretreatment, (b) pretreatment with HF/
H2SO4 for 30 s, and (c) pretreatment with HCl:H2O for 30 s. (d) Effects of different chemical pretreatments on interfacial adhesion energy of Cu–Cu direct
bonds. [30].
Fig. 4. (a) Plan-view EBSD orientation image map of the randomly oriented Cu film, and (b) the image shows only (111) oriented grains. (c) XRD analysis of the
randomly oriented Cu film. (d) Plan-view EBSD orientation image map of the (111) nt-Cu film, and (e) the image shows only (111) oriented grains. (f) XRD analysis of
the (111) nt-Cu film. [34].
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Microelectronics Reliability 127 (2021) 114412
bonded on chip-level successfully at 300 ◦ C for 10 s [35]. However, the
microstructure of the nt-Cu bump structures and results of EBSD ana­
lyses shown in Fig. 5 indicate that the ratio of (111) oriented surface is
only about 40% and mostly locating at the edge of bumps. Thus,
enhancement of (111) oriented surface of Cu structures with fine pitch is
the critical issue to be studied for the feasibility of nt-Cu bonding in
industrial applications.
2.4. Plastic deformation for Cu–Cu bonding
In the crystalline scale, plastic deformation induced by an external
high stress can break the arrangements of atoms, causing dislocation and
friction of crystals to generate internal energy. Based on this mechanism,
the pillar-concave structures have been designed by K. N. Chen's group
to realize low temperature Cu–Cu bonding [36–38]. Schematic illus­
trations of the designed structures and mechanism are shown in Fig. 6.
At the beginning of the bonding process, only corners of Cu pillars can
contact with Cu concaves, inducing a large stress. When Cu pillars
gradually fill up Cu concaves by the large stress, strong plastic defor­
mation occurs and generate internal energy to enhance diffusion of Cu,
reducing the required bonding temperature of Cu–Cu bonding. In the
studies, pillar-concave Cu–Cu bonding can be achieved on chip-level at
150 ◦ C for one minute with a 500 MPa bonding pressure. Moreover, the
resistance of the bonding structures can maintain with negligible dete­
rioration after temperature cycling test (TCT) for 1000 loops and unbi­
ased highly accelerated stress test (unbiased HAST) for 96 h, showing
the excellent stability of the bonded structures. Because bonding is
achieved by deformation of the pillar-concave structures, tolerance on
the bump height variation is much larger than other bonding methods.
Therefore, Fig. 7 has demonstrated successful chips bonding on the
panel-level RDL substrate, which usually has a high surface roughness,
by gang bonding with the plastic deformation scheme.
2.5. Cu–Cu bonding by passivation scheme
In addition to clean the oxides on Cu surface before bonding, at­
tempts have been made to prevent surface oxidation of Cu directly by
the passivation scheme. Tan's group has applied self-assembled mono­
layer (SAM) on Cu surface to retard oxidation during exposure in the
ambient, followed by a desorption process near to 250 ◦ C in inert N2
ambient before bonding [39]. With the SAM scheme, wafer-level Cu–Cu
bonding achieved at 250 ◦ C for one hour has been demonstrated, while
the bonding temperature is difficult to be lower due to the constraint of
the desorption process. Thus, Shiv Govind Singh's group has developed
the technique of Non-Thermal Plasma (NTP) desorption, which provides
removal of SAM at room temperature and enable Cu–Cu bonding with
high quality at 200 ◦ C [40]. However, the formation of SAM by ab­
sorption of linear alkane-thiol atoms is incompatible with the semi­
conductor fabrication and difficult to protect Cu from oxidation
completely. Accordingly, passivation schemes using deposition of a thin
metal passivation layer on Cu surface have been proposed for low
temperature Cu bonding without these drawbacks.
A thin layer of Ti has been firstly developed as metal passivation by
K. N. Chen's group's to realize Cu–Cu bonding at low temperature [41].
By consecutive sputtering of Cu and Ti in a vacuum chamber, the thin
layer of Ti and Ti oxides can effectively protect entire inner Cu region
from oxidation. After the TCB process, Cu is observed to diffuse through
Ti passivation into the bonding interface despite formation of the ultrathin Ti oxide layer, achieving wafer-level Cu–Cu bonding at 180 ◦ C for
30–50 min. Evaluation of the interdiffusion and the bonding results are
shown in Fig. 8. In addition, contact resistance measurements of the
Fig. 5. (a) SEM image of nt-Cu microbump arrays after CMP, and the inset
image shows an as-deposited nt-Cu microbump. (b) Focused Ion Beam analysis
of a microbump. (c) EBSD analysis of surface orientation of an nt-Cu micro­
bump. [35].
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Microelectronics Reliability 127 (2021) 114412
Fig. 6. (a) Illustration of the mechanism of plastic deformation in crystalline scale. (b) Schematic of the designed pillar–concave structure for Cu–Cu bonding. [38].
bonded structure demonstrate the good structural and electrical stabil­
ity, as shown in Fig. 9.
Next, Pd metal has been developed as another passivation material
for the Cu–Cu bonding structure with lower thermal budget and much
lower specific contact resistance, broadening possible applications [42].
The EDX analyses of Pd passivation structures shown in Fig. 10 validate
that oxides can be prevented in total region of the bonded structures.
Accordingly, with the bonding temperature of 150 ◦ C, high uniformity
of wafer-level Cu–Cu bonding results can be obtained and verified by
analyses of Scanning Acoustic Tomograph (SAT). Furthermore, elec­
trical measurements as well as reliability assessments have been per­
formed, as shown in Fig. 11. Because the contact resistance of Ti
passivation structures is increased due to the formation of Ti oxidation
inside the bonded structure, the Pd passivation structures with oxides
can show much better electrical characteristics.
After development of Pd passivation, the Cr/Au layer has been
investigated as metal passivation in the following studies by K. N. Chen's
group, which can enable Cu–Cu bonding on wafer-level at 100 ◦ C for
15 min and on chip-level at 70 ◦ C for 180 s [43]. Compared with only a
10 nm layer of Au on Cu surface, the bonding structure with a 2 nm Cr
wetting layer and a 8 nm Au passivation layer shows the lower surface
roughness, which is beneficial for bonding. Thus, high quality Cu–Cu
bonding with Cr/Au passivation can be achieved at the ultra-low
bonding temperature, which has been verified by the analyses of SAT
and SEM, as shown in Fig. 12.
In addition to Pd or Au, Ag as relatively cheaper noble metal has been
evaluated for metal passivation to accomplish chip-level Cu–Cu
bonding at 180 ◦ C for 3 min [44]. In this work, mechanism of interdiffusion between Cu and passivation at low temperature has been
first explained by grain boundary diffusion, indicating smaller grain size
of passivation layer can enhance diffusion of Cu due to more diffusion
paths. For smaller grain size of Ag passivation, which is controlled by
sputtering parameters, better bonding results of Cu–Cu bonding can be
obtained, including electrical properties and reliability. Fig. 13 shows
the TEM and EDX analyses of the bonding structure, providing evidence
for the bonded interface and diffusion behavior.
In the passivation studies mentioned above, consecutively sputtering
Cu and passivation metal in the vacuum chamber can prevent oxidation
of Cu effectively, assist diffusion of Cu, and have compatibility with
packaging fabrication. Despite such advantages, mass production of this
process has been challenged owing to the sputtering process, which has
a low deposition rate. In pursuit of high throughput, Cu interconnects
are commonly fabricated by electrochemical deposition (ECD) in the
industry, while the high roughness of ECD Cu induces difficulty for
Cu–Cu bonding. Though a planarize process can be conducted to flatten
the surface of ECD Cu, this process is very expensive. In order to solve
the problems, K. N. Chen's group has developed the passivation scheme
to realize low temperature bonding of ECD Cu pillar without planari­
zation [45]. After fabrication of ECD Cu pillars, a higher surface
roughness about 7.69 nm is measured, while sputtered Cu pads show
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Microelectronics Reliability 127 (2021) 114412
Fig. 9. Contact resistance measurement of the Ti passivation bonding structure.
(a) Schematic diagram and top view of the contact resistance measurement. (b)
contact resistance of the bonding structure before current cycling, and (c) after
1000 current cycling. [41].
Fig. 7. (a) Multichips bonding on the small size panel-level RDL glass substrate.
(b) Cross-sectional SEM image of the bonded structure by the plastic defor­
mation scheme. [38].
Fig. 8. TEM image and the corresponding EDX analysis of Cu–Cu bonding
with Ti passivation. [41].
Fig. 10. Cu–Cu bonding with Pd passivation at 150 ◦ C. (a) TEM image and
EDX scanning position of the bonding structure. (b) Corresponding composition
profile. (c) Wafer-level SAT analysis. [42].
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Microelectronics Reliability 127 (2021) 114412
Fig. 11. Comparison of electrical characteristics of Cu–Cu bonding structures with Pd and Ti passivation under TCT and unbiased HAST. [42].
Fig. 12. (a) SAT image of the bonding structure with Cr/Au passivation bonded at 100 ◦ C (b) SAT image of the bonding structure without passivation bonded at
250 ◦ C, (c) SAT image of the bonding structure with Au passivation bonded at 150 ◦ C. (d) SEM image of the bonding structure with Cr/Au passivation bonded at
100 ◦ C. [43].
addition, a higher bonding force of 330 MPa is applied to ensure the
contact of Cu pillars during the bonding process. The high bonding
qualities have been validated by analyses of TEM, shear test, electrical
measurements, and reliability tests, showing high feasibility of the
passivation bonding scheme to meet the industrial demands due to its
low thermal budget, compatibility with high volume manufacturing,
surface roughness lower than 1 nm in previous passivation studies. In
spite of the higher surface roughness, ECD Cu pillars with 10 nm Pd
passivation can be bonded well on chip-level at 180 ◦ C for 15 s under the
atmosphere. The schematic of process flow is shown in Fig. 14. In this
scheme, a chemical pretreatment of diluted sulfuric acid is necessary to
remove oxides on Cu surface before deposition of passivation. In
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Microelectronics Reliability 127 (2021) 114412
Fig. 13. (a) TEM image of the bonding structure with Ag passivation and (b) corresponding EDX composition profile by line scanning of the bonding structure with
Ag passivation. (c) TEM image of the bonding structure with Ag passivation and the corresponding EDX composition with map scanning of (d) Ti, (e) Cu, and (f)
Ag. [44].
Fig. 14. Schematic of the Process flow for ECD Cu pillars to Cu pillars bonding with Pd passivation. [45].
and saving time.
Metal passivation of Ti, Pd, Au, Cr/Au, Ag have been developed for
Cu bonding, which can realize high quality bonding at the lower tem­
perature comparing to other methods. In addition, the high electrical
properties and reliabilities of the metal passivated bonding structures
have been validated. Furthermore, the compatibility of metal passiv­
ation scheme with ECD Cu process has been demonstrated. The shortcoming of metal passivation is the requirement for additional lithog­
raphy process to deposit metal passivation on Cu surface.
micro bumps, protruded Cu pillars from the dielectric surface bonded by
the Cu–Cu TCB process are the alternative structures. Nevertheless, the
fine pillar structures are difficult to be fabricated with total thickness
variation meeting the requirement of Cu–Cu bonding, which is much
less that of traditional solder joints. Furthermore, injection of underfill
resin into the narrow gaps in the fine pitch structure is challenged
because of issues of flux residues and surface tension morphology, while
injected underfill can ensure the reliability of the structure. Accordingly,
hybrid bonding structures have been developed with the precise control
of height variation of Cu pads by optimized chemical mechanical pol­
ishing (CMP), realizing bump-less Cu–Cu bonding. Eliminating the
need for bumps and pillars, hybrid bonding paves the way towards nextgeneration 3D IC technology.
3. Low temperature Cu/SiO2 hybrid bonding
Since the interconnect density and bonding yield loss of conventional
solder bumps faces bottleneck due to its high required volume and the
formation of intermetallic layers, Cu–Cu bonding has become the most
desirable bonding technology due to the excellent properties of Cu as
above mentioned. For the pursuit of interconnects with finer pitch than
3.1. Direct bonding interconnect technology for Cu/SiO2 Hybrid Bonding
The bump-less Cu/SiO2 interconnect, which is the most promising
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Microelectronics Reliability 127 (2021) 114412
Fig. 15. Schematic illustration of the two-step process of DBI technology. (a)
Oxide to oxide bonding at room temperature. (b) Annealing process for metal to
metal interconnect. [52].
hybrid bonding structure for fine-pitch applications, can be realized
through direct bonding interconnect (DBI) technology or TCB technol­
ogy. DBI technology has been invented by Ziptronix, Inc. for scalable
hybrid bonding process [46–50], followed by studies to demonstrating
that DBI technology can enable interconnect pitch scaling to 10 μm and
below [51–53]. Hybrid bonding by DBI technology involves a two-step
process, as shown in Fig. 15. At first, with hydrophilic surface modifi­
cation of bonding surface, SiO2 to SiO2 bonding can be achieved at room
temperature. Next, Cu–Cu bonding is established by a batch annealing
process at 200 ◦ C to 400 ◦ C. This bonding approach is high throughput,
while quality of SiO2 bonding interface is challenged because of the
stress effect from trapping of excess H2O and Cu thermal expansion
during the annealing process [54].
Fig. 16. EBSD orientation image maps of the (a) Cu seed layer and (b) nt-Cu
blanket film. SEM images of (c) as-fabricated dish-shaped nt-Cu by conformal
plating and (d) pad-shaped nt-Cu after CMP. (e) SEM and (f) EBSD images of the
dish-shaped nt-Cu surface. (g) SEM and (h) EBSD images of pad-shaped nt-Cu
surface. [55].
about 75.1% and 99% (111) oriented grains of Cu for dish-like and padlike, respectively. Thus, pad-like nt-Cu/SiO2 hybrid structure is expected
to show potential for hybrid bonding at 250 ◦ C, while results of nt-Cu/
SiO2 hybrid bonding have not been demonstrated yet.
3.2. Nanotwinned Cu structure for potential Cu/SiO2 hybrid bonding
Because the (111) oriented Cu has the highest diffusion rate, suc­
cessful bonding between nt-Cu films has been demonstrated at 200 ◦ C
for 1 h [33,34]. Accordingly, hybrid structure of nt-Cu and SiO2 has been
explored for low temperature Cu/SiO2 hybrid bonding by W. L. Chiu's
group [55]. In this study, nt-Cu blanket film, hybrid nt-Cu/SiO2 dish
shape, and hybrid nt-Cu/SiO2, are fabricated and investigated, as shown
in Fig. 16. The nt-Cu blanket films with the (111) orientations of Cu
grains near 99% can be bonded well at 250 ◦ C for 1 h, which is validated
by analyses of SAT and SEM. With the control of CMP process, dish-like
and pad-like nt-Cu/SiO2 hybrid structure can be obtained, displaying
3.3. Cu/SiO2 hybrid bonding with metal passivation
In TCB technology, Cu and SiO2 can be bonded simultaneously under
external compression, showing the potential for higher bonding me­
chanical strength than DBI technology. Thermal budget of this scheme is
mainly dominated by the TCB process of Cu–Cu bonding. Therefore,
based on the development of aforementioned passivation schemes, low
temperature Cu/SiO2 thermal-compressive hybrid bonding has been
studied by K.N. Chen's group [56], which is beneficial for the
advancement of heterogeneous integration technology with demands of
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Microelectronics Reliability 127 (2021) 114412
H.-W. Hu and K.-N. Chen
Fig. 17. SEM images of the Cu/SiO2 hybrid bonding structures with passivation (a)(b)(c)(d) Pd, (e) Metal A, (f) Au. [56].
shown in Fig. 17. The comparison of capability of different passivation
metal for hybrid bonding has been shown in Fig. 18. The excellent
hybrid bonding qualities have been further validated by shear tests,
electrical measurements, and reliability tests. In the hybrid bonding
structure, a passivation layer can prevent formation of Cu oxides and
enhance diffusion of Cu atoms, as well as compensate CMP dishing.
Therefore, the passivation hybrid bonding scheme enables low thermal
budget (120 ◦ C), good electrical characteristics (over 15 K daisy chain
and 10− 8 Ω-cm2 specific contact resistance), high bonding mechanical
strength (>15 kgf), and high reliability (pass TCT and un-Biased HAST),
showing the great potential for fine-pitch 3D integration technology
with a wide range of applications.
4. Conclusion
Lower thermal budget of Cu-based bonding, as the key to improve
reliability and extend range of applications, has been developed by
different methodologies, including SAB, chemical pretreatments, nt-Cu,
plastic deformation, SAM passivation, and metal passivation. The ad­
vantages and disadvantages of these techniques are compared in
Table 1. Based on the progress of low temperature Cu bonding tech­
nologies, passivation scheme has been applied for Cu/SiO2 thermal
compressive hybrid bonding to realize bump-less Cu bonding at low
temperature, which is promising for heterogenous integration with finepitch applications.
Fig. 18. Comparison of capability of different passivation metal for Cu/SiO2
hybrid bonding. [56].
high I/O density, low thermal budgets, and high reliability. In this
demonstration, the Cu/SiO2 hybrid bonding structures with different
metal passivation have been successfully bonded on chip-level at 120 ◦ C
to 250 ◦ C, including passivation materials of Pd, Au, and metal A, as
Table 1
Comparison of different low temperature Cu–Cu bonding technologies.
Technology
Bonding
temperature
SAB
Room temperature
Chemical
Pretreatment
Nt-Cu
Plastic Deformation
250 ◦ C to 350 ◦ C
SAM
200 ◦ C to 250 ◦ C
Metal Passivation
120 ◦ C to 250 ◦ C
250 ◦ C to 300 ◦ C
150 ◦ C
Advantage
Disadvantage
Reference
Ultra-low thermal budget.
High bonding quality.
Low cost.
High throughput.
High CMOS-compatibility.
Lower thermal budget.
High tolerance on the bump height
variation.
High bonding quality.
UHV environment.
High cost & Low throughput.
Lower bonding quality.
[20–23]
Limitation in fine pitch Cu bump structure.
Additional lithography process to fabricate pillar-concave structure.
[33–35]
[36–38]
Incompatible with industrial fabrication.
Residues of monolayer.
Additional lithography process to deposit metal passivation on Cu
surface.
[39–40]
Lower bonding temperature.
High bonding quality.
High electrical performance and reliability.
10
[24–30]
[42–45]
H.-W. Hu and K.-N. Chen
Microelectronics Reliability 127 (2021) 114412
Declaration of competing interest
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The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
Acknowledgements
This work was financially supported by the “Center for the Semi­
conductor Technology Research” from The Featured Areas Research
Center Program within the framework of the Higher Education Sprout
Project by the Ministry of Education (MOE) in Taiwan. Also supported in
part by the Ministry of Science and Technology, Taiwan, under Grant
MOST 110-2634-F-009-027-, MOST 109-2221-E-009-023-MY3, and
MOST 110-2221-E-A49-086-MY3.
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