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Library Names:
tphn28hpmgv18
tphn28hpgv18
tphn28hplgv18
tphn28lpgv18
tphn28hpcpgv18
tphn28hpmgv2od3
tphn28hplgv2od3
tphn28lpgv2od3
tphn28hpcgv2od3
Version 1.4
Nov. 6, 2015
TSMC N28 General I/O Library Application Note
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TSMC N28 GENERAL I/O LIBRARY
APPLICATION NOTE
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Copyright 2015, Taiwan Semiconductor Manufacturing Company, Ltd. All Rights Reserved.
No part of this publication may be reproduced in whole or in part by any means without prior written consent.
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Taiwan Semiconductor Manufacturing Company Ltd. reserves the right to make changes in the contents of this
document without notice. No responsibility is assumed by Taiwan Semiconductor Manufacturing Company Ltd.
for any infringements of patents or other rights of the third parties that may result from its use. Taiwan
Semiconductor Manufacturing Company Ltd. assumes no responsibility for any error that appears in this
document.
TSMC N28 General I/O Library Application Note
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NOTICE
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Revision History
Version
Date
Special Notes and Changes
Correct the typo on page.5 from “錯誤! 找不到參照來源。” to
“Section3.3”.
1.3
2015-07-06
Add statements in Section 1.6 for Latch-Up Prevention
1.2
2015-06-18
1. This document is applicable to some of N28 libraries which are
listed on the front cover.
2. Mention that the priority of library release note is higher than the
application note, if any conflict, in Section 1.2.
3. Rename Chapter 3 from “The Power-On-Control Cell” to
“Power-Up/Down” and update the contents.
4. Remind of leakage when V(PAD) > V(VDDPST) when
VDDPST is ON, in Section 4.1
5. Add a rule “It is required to disable the pull function when PAD
is driven by external voltage that is greater than VDDPST” in
Section 4.2
6. Since PADxxGAU/PADxxNAU was removed and replaced by
PADxxGU/PADxxNU starting from tpbn28v_130a, update this
document accordingly.
7. Update PENDCAP_G/PENDCAPA_G related rules to refer to a
separate file “ApplicationGuide_N28_AAIO”
8. Update double I/O ring related rules to refer to a separate file
“ApplicationGuide_N28_AAIO”
9. Add a section for “AAIO Application”
10. Add a chapter for “TSMC9000 Overview”
1.10
2012-04-20
1.00
2010-01-22
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2015-11-06
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1.4
To revise typo and update application requirements in Chapter 1, 2,
3, 6, 8, 9, 10, 11, 12, 14, 18.
The first released version of general application note for TSMC N28
I/O Library.
TSMC N28 General I/O Library Application Note
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Table of Contents
Chapter 1
1.2
Related Documentation ........................................................................................... 1
1.3
N28 Hybrid I/O Library & Cell Naming Convention.............................................. 1
1.4
N28 I/O Application ................................................................................................ 2
1.5
ESD Target .............................................................................................................. 3
1.6
Latch-Up Prevention................................................................................................ 3
1.7
Document Content ................................................................................................... 3
1.8
Terms ....................................................................................................................... 3
The Digital Power/Ground Cells & LVS Consideration ......................................... 4
2.3
The Analog Power / Ground Cells Compatible with Digital I/O............................. 6
2.3.1
The Analog Power PVDD1ANA_V/H_G & PVDD2ANA_V/H_G to
Internal Macro ............................................................................................ 6
2.3.2
Analog Signal Transmission ....................................................................... 7
2.3.3
The Analog Ground PVSS1ANA_V/H_G & PVSS2ANA_V/H_G to
Internal Macro ............................................................................................ 9
2.3.4
Application Example ................................................................................ 10
Power-Up/Down ............................................................................................................ 11
Power-Up ............................................................................................................... 11
3.1.1
Ramp-Up Time Restriction ...................................................................... 11
3.1.2
Power-Up Sequence in Digital Domain ................................................... 11
3.2
Power-Down Sequence in Digital Domain............................................................ 11
3.3
Power On Control (POC) ...................................................................................... 12
3.4
POC Implementation ............................................................................................. 13
3.5
Chapter 5
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2.2
3.1
Chapter 4
The Digital I/O Power/Ground Rail ........................................................................ 4
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2.1
Chapter 3
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The Power Arrangement for N28 Digital I/O............................................................... 4
3.4.1
When There Is No Digital Function I/O in the Domain ........................... 13
3.4.2
LVS Consideration for the POC Signal .................................................... 14
The Stand-By Leakage Current of PVDD2POC_V/H_G...................................... 14
The N28 Function I/O ................................................................................................... 15
4.1
DGZ_V/H_G Cell Name Suffix ............................................................................ 15
4.2
Programmable Pins ................................................................................................ 16
4.3
Open Drain Emulation ........................................................................................... 17
The N28 Oscillator I/O ................................................................................................. 18
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Purpose .................................................................................................................... 1
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1.1
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Chapter 2
Introduction..................................................................................................................... 1
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5.1
Chapter 6
5.1.1
Tank Circuit .............................................................................................. 19
5.1.2
Pin Order .................................................................................................. 19
5.1.3
Back Annotation ....................................................................................... 20
5.1.4
Staggered CUP Bond Pads for the Oscillator I/O ..................................... 20
5.1.5
Clock Input Buffer .................................................................................... 20
Accessory Cells for N28 Digital I/Os ........................................................................... 22
The PFILLERx_G Filler Cell ................................................................................ 22
6.2
The PCORNER_G Corner Cell ............................................................................. 23
6.3
The PRCUT_G Power-Cut Cell for Digital Domain Separation ........................... 23
6.4
The PENDCAP_G Guard-Band Closure Cell ....................................................... 24
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Simultaneously Switching Output Considerations .................................................... 26
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7.1
Terminology and Definition .................................................................................. 26
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7.1.1
Chapter 8
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7.1.2
Simultaneously Switching Output ............................................................ 26
Simultaneously Switching Noise .............................................................. 26
7.1.3
Driving Index ............................................................................................ 26
7.1.4
Driving Factor........................................................................................... 26
7.1.5
Sum of Driving Factors ............................................................................ 26
7.2
SSO Simulation Model .......................................................................................... 27
7.3
Calculate the Required Number of I/O Power/Ground Cell .................................. 27
7.4
How to Reduce SSN .............................................................................................. 28
The ESD & Latch-Up Considerations for N28 Digital I/Os ...................................... 29
8.1
The ESD Network ................................................................................................. 29
8.2
The Global ESD Bus ............................................................................................. 29
8.3
The Dummy Power / Ground Cell ......................................................................... 30
8.4
The ESD Power / Ground Metal Bus Resistance Requirement ............................. 31
8.5
The 20pF Requirement .......................................................................................... 32
8.6
The Required Power / Ground Cell Number ......................................................... 33
8.7
The ESD Clamp Macro ......................................................................................... 34
8.7.1
PCLAMPC_V/H_G ESD Core-Clamp Macro ......................................... 34
8.7.2
PCLAMP_G ESD I/O-Clamp Macro ....................................................... 34
8.7.3
Implement PCLAMPC_V/H_G / PCLAMP_G Macro on the Core Side 34
8.8
The PCORNER_G Corner Cell ............................................................................. 35
8.9
The PRCUT_G Power-Cut Cell for Digital Domain Separation ........................... 35
8.10 The PENDCAP_G Guard-Band Closure Cell ....................................................... 35
8.11 How to Integrate TSMC I/O with Other IP ........................................................... 35
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Chapter 7
Oscillator I/O Introduction .................................................................................... 18
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Chapter 9
The N28 Analog I/O ...................................................................................................... 38
9.2
PDB3A_V/H_G, PDB3AC_V/H_G Analog Signal Cell ...................................... 38
9.3
PVDD3A_V/H_G / PVDD3AC_V/H_G Analog Power Cell ............................... 41
9.4
PVSS3A_V/H_G, PVSS3AC_V/H_G Analog Ground Cell ................................. 42
9.5
PVDD1A_V/H_G / PVDD1AC_V/H_G Analog Power Cell ............................... 43
9.6
PVSS1A_V/H_G, PVSS1AC_V/H_G Analog Ground Cell ................................. 43
9.7
PVSS2A_V/H_G, PVSS2AC_V/H_G Global ESD Ground Bus VSS Supply ..... 45
9.8
PFILLERxA_G, PCORNERA_G, PRCUTA_G, PENDCAPA_G Accessory Cell
............................................................................................................................... 46
9.8.1
The PFILLERxA_G Filler Cell ................................................................ 46
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The PCORNERA_G Corner Cell ............................................................. 47
9.8.3
The PRCUTA_G Power-Cut Cell for Analog-Digital I/O Domain
Separation or Analog-Analog I/O Domain Separation ............................. 47
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9.8.2
9.8.4
The PENDCAPA_G Guard-Band Closure Cell ....................................... 48
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Chapter 10 The ESD & Latch-Up Considerations for N28 Analog I/O....................................... 50
10.1 The ESD Network ................................................................................................. 50
10.2 The Global ESD Bus ............................................................................................. 51
10.3 The Dummy Analog Power/Ground Cell Insertion ............................................... 52
10.4 The ESD Analog Power / Ground Metal Bus Resistance Requirement ................ 53
10.5 The 20pF Requirement .......................................................................................... 54
10.6 The Required Analog Power / Ground Cell Number ............................................ 55
10.7 The ESD Clamp Macro ......................................................................................... 56
10.7.1 PCLAMPC_V/H_G ESD Core-Clamp Macro ......................................... 56
10.7.2 PCLAMP_G ESD I/O-Clamp Macro ....................................................... 56
10.7.3 Implement PCLAMPC_V/H_G, PCLAMP_G ESD Clamp Macro on the
Core Side .................................................................................................. 56
10.8 The PRCUTA_G Power-Cut Cell for Analog-Analog or Analog-Digital Domain
Separation .............................................................................................................. 56
10.9 The PCORNERA_G Corner Cell .......................................................................... 56
10.10 The PENDCAPA_G Guard-Band Closure Cell .................................................... 56
10.11 How to Integrate TSMC I/O with Other IP ........................................................... 56
Chapter 11 The Bond Pad for N28 I/O ........................................................................................... 58
11.1 The Bond Pad Library ........................................................................................... 58
11.2 The Naming Convention for the Bond Pad ........................................................... 58
11.3 The Library Hierarchy ........................................................................................... 59
11.4 CUP Bond Pad Type.............................................................................................. 59
11.4.1 The Staggered CUP Pads for I/O .............................................................. 59
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Analog I/O Power / Ground Rail ........................................................................... 38
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Chapter 12 Applications ................................................................................................................... 61
12.1 The Back-End Kit Directory .................................................................................. 61
12.2 CUP (Circuit under Pad) Wire Bond ..................................................................... 61
12.3 RDL (Re-Distribution Layer) Flip Chip ................................................................ 62
12.3.1 PCLAMP_G/PCLAMPC_V/H_G usage as ESD clamp cell for RDL flip
chip ........................................................................................................... 63
12.4 Double I/O Rings ................................................................................................... 63
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Chapter 13 Electromigration (EM) Consideration ........................................................................ 67
13.1 EM Capacity of the Power/Ground Cell ................................................................ 67
13.1.1 Determine the Maximum Allowable Current ........................................... 67
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13.1.2 Determine the Required Number of Power/ Ground Cells ....................... 67
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13.1.3 Locate the EM Critical Point .................................................................... 67
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13.1.4 EM vs. Temperature ................................................................................. 67
13.2 EM Capacity of the Bond Pad ............................................................................... 67
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13.3 EM Capacity Enhancement ................................................................................... 68
13.3.1 Double/Triple Bonds ................................................................................ 68
13.3.2 Connect Top Two Metal Lines from the CUP Pad to Core ...................... 68
Chapter 14 Library Integration Notes ............................................................................................ 72
14.1 GDSII Number Mapping ....................................................................................... 72
14.2 ESD Mask .............................................................................................................. 72
14.3 GDSII Change to Mask Revision .......................................................................... 72
Chapter 15 Simulation Notes ........................................................................................................... 73
15.1 LPE Netlist ............................................................................................................ 73
15.2 Characterization Conditions .................................................................................. 73
15.3 Power / Ground Pin Information ........................................................................... 74
Chapter 16 Layout Considerations ................................................................................................. 76
Chapter 17 The Absolute Maximum Rating .................................................................................. 77
Chapter 18 N28 I/O Usage Checklist............................................................................................... 78
18.1 Review Checklist ................................................................................................... 78
Chapter 19 Contact Us ..................................................................................................................... 85
Chapter 20 TSMC9000 Overview ................................................................................................... 86
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12.5 AAIO (Area Array I/O) Application ..................................................................... 66
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Chapter 1
1.1
Introduction
Purpose
This General Application Note provides information on I/O features, usage instruction, and general
application guideline for the TSMC N28 I/O Libraries. In addition to this document, it is mandatory
to refer to the library release note to check if there is any more stringent application requirement in
particular for the library in use.
Related Documentation
Table 1.1: N28 I/O Library Documents
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This application note provides general usage guidelines for the N28 libraries listed on the front cover.
For library–dependent information, please refer to the library release note, databook, and silicon
report (if applicable) as indicated in Table 1.1.
Note:
This application note is for general cases, while the library release note is specific for that library.
In case there is a conflict between the application note and a library release note, the priority of the
library release note is higher than the application note, and please follow the rules in the release
note.
Type
Information Coverage
Library
Release
Note









Library information
Update history
Design kit version dependency table
Characterization conditions
Known problems & limitations
Special notes (application guide)
EM table
Library contents
The required tape-out layers




Physical information
Electrical characteristics
Cell description
SSO DF (Simultaneously Switching
Output Noise Driving Factors) for
the digital output drivers
Data sheets
Library
Databook

How to Access




Packed within the library rln kit
(e.g.
tphn28hpgv18_100a_rln.tar.gz)
After unzip & untar the rln kit,
look for the file name with prefix
RN, where RN stands for release
note
Packed within the library doc kit
(e.g.
tphn28hpgv18_100a_doc.tar.gz)
After unzip & untar the doc kit,
look for the file name with prefix
DB, where DB stands for databook
Library
Silicon
Report

Silicon characterization results (For
the library that is silicon proven)

Download from Design Portal at
TSMC Online
General
Application
Note

General usage instruction &
application guideline

Download from Design Portal at
TSMC Online
1.3
N28 Hybrid I/O Library & Cell Naming Convention
The TSMC N28 hybrid I/O library naming follows the conventions below:
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[Category] – [Geometry] – [Process node] – [Layout style] – [Process voltage]
Category:

TPH: the library provides both digital and analog I/O cells.
Geometry:

N28: For TSMC N28 process.
Process node:
defines the TSMC process flavor (for example, HP or HPL or HPM)
Layout style:
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
GV - staggered layout style.
Process voltage:
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18: For 1.8V process

25: for 2.5V process

25OD3: for 2.5V process but following the overdrive rules.

25UD18: for 2.5V process but following the underdrive rules.
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
For example: TPHN28HPGV18 can be decomposed as TPH-N28-HP-GV-18, which indicates TSMC
analog and digital I/O library in 28nm HP process with staggered layout style, designed for 1.8V
process.
The following indicates suffix of I/O cell naming convention:
[Cell name] – [Usage] – [_Orientation] – [_Layout style]
Usage:

A/AC: analog I/O cell

All the letters except A and AC: digital I/O cell, or cells that can be used for analog and
digital
Orientation:

V: for vertical placement

H: for horizontal placement

none: cells that can be used for both vertical and horizontal placement
Layout style:

G: staggered layout style
For example:

PDB3A_V_G: analog I/O cell for vertical placement with staggered layout style

PDUW08DGZ_H_G: digital I/O cell for horizontal placement with staggered layout style
1.4
N28 I/O Application
TSMC N28 I/O can support CUP (Circuit Under Pad) wire bond and RDL (Re-Distribution Layer)
flip chip applications. For non-CUP wire bond, please contact TSMC in request for customization
service.
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1.5
ESD Target
The guidelines/rules mentioned in this Application Note are for HBM 2KV and MM 100V. For the
cases with CDM spec, please contact us.
1.6
Latch-Up Prevention
For latch-up prevention, please make sure the I/O placement meets all the latch-up rules defined in
DRM. DRC might not be able to cover all latch-up rule checks, please use DRC and PERC for
complete latch-up rule check.
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Some recommendations of filler cell insertion can be found in the library release note, however, note
that those are not hard rules and they do not cover all combinations of I/O placements. To prevent
from latch-up, please pass DRC+PERC check for sign-off.
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1.7
Document Content
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The document is organized with the following chapters:
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Chapter 2 to Chapter 8: Dedicated to the digital I/O and the analog power & ground cell compatible
with the digital I/O.
Chapter 9 to Chapter 10: Dedicated to the analog I/O and its integration with the digital I/O.
Chapter 1, Chapter 11 to Chapter 19: Applicable to both digital and analog I/O cells.
1.8
Terms
Terms in this document:
1. Bonded: connected to wire-bond pad/package or connected to flip chip bump/package
2. Dummy: not-bonded
3. DRM: TSMC Design Rule Manual
4. N/A: Not Applicable
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To let DRC and PERC perform the correct latch-up rule check, it is required to set the correct pin text
name in the run deck.
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Chapter 2
The Power Arrangement for N28
Digital I/O
This Chapter covers the following topics:
The Digital I/O Power/Ground Rail

The Digital Power/Ground Cells & LVS Consideration

The Analog Power/Ground Cells Compatible with the Digital I/O

The PVDD2ANA_V/H_G Analog Signal Transmission
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2.1
The Digital I/O Power/Ground Rail
(2)
(3)
(4)
(7)
(4)
(1) Internal control and signal pins to the core logics
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This section provides information on the digital I/O power/ground rail configuration. Please make
sure that the power & ground rail(s) of each I/O cell is connected by abutting with another I/O cell /
the P&R cells (Filler Cells, Corner Cells) / the guard-band closure cell (PENDCAP_V/H_G) / the
power-cut cell (PRCUT_V/H_G). Figure 2.1 presents a typical TSMC I/O layout.
(2) Power rail VDD: connects to the core power ring & the predriver
(3) Ground rail VSS: connects to the core ground ring & the predriver
(4) Power rail VDDPST: connects to the I/O power ring for levelshifters and post-driver
(5) Guard ring
(5)
(6)
(6) Ground rail VSSPST: connects to the I/O ground ring for the
post-driver
(7) Connection to the bond pad
Figure 2.1: I/O layout example
2.2
The Digital Power/Ground Cells & LVS Consideration
The TSMC N28 I/O libraries include power and ground cells that supply different voltages to the core,
pre-drivers, and post-drivers. The text is attached to the pad to separate multi-power / ground routing,
and is used for Layout vs. Schematic (LVS) purposes. Table 2.1 describes the route pin to the core
side and the attached pad text for LVS.
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Table 2.1: Pin Information for Digital Power/Ground Cells
Default pin to core
Default label in
gds and lvs netlist
PVDD1DGZ_V/H_G
core cells +
pre-drivers
VDD
VDD
PVDD2DGZ_V/H_G
PVDD2POC_V/H_G
post-drivers
None
VDDPST
PVSS1DGZ_V/H_G
core cells +
pre-drivers
VSS
VSS
post-drivers
None
VSSPST
all the transistors
VSS
VSS
PVSS2DGZ_V/H_G
PVSS3DGZ_V/H_G
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There are two ground schemes that can be chosen when using TSMC N28 I/O library. It is required to
use the specific ground cell along with the corresponding LVS netlist for LVS check.
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The separate ground scheme separates (the core & the pre-drivers) VSS ground from (the
post-driver) VSSPST for noise consideration. As shown in Table 2.1, PVSS1DGZ_V/H_G &
PVSS2DGZ_V/H_G are the separate ground cells for this scheme.

The common ground scheme provides only one VSS ground source to all transistors.
PVSS3DGZ_V/H_G is the digital ground cell that supplies the core, pre-drivers, and postdrivers.
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
It is suggested to use the separate ground scheme for a less-noisy ground source, as core and I/O
grounds are separate from each other. The common ground scheme is for when the ground noise is
less critical or when the pad-limited design is required.
In regard to power, it is required to implement both digital core power cell and digital I/O power cell
in each digital domain. Specifically for the PVDD2POC_V/H_G usage guide, please refer to Section
3.3 for details.
For each of these ground schemes, Table 2.2 indicates the necessary power and ground I/O cells
needed. For each I/O, the sub-circuit contains both VSS and VSSPST pins, for example:
.SUBCKT PRDW04DGZ_H_G C PAD I OEN REN VDD VDDPST VSS VSSPST POC
In a separate ground scheme environment, this example would be called as:
X1 C1 PAD1 I1 OEN1 REN1 VDD1 VDDPST18 VSS VSSPST18 POC1 PRDW04DGZ_H_G
Where:
VDD1 is the core power supplied by PVDD1DGZ_V/H_G
VDDPST18 is the I/O power supplied by PVDD2DGZ_V/H_G
VSS is the core ground supplied by PVSS1DGZ_V/H_G
VSSPST18 is the I/O ground supplied by PVSS2DGZ_V/H_G
POC1 is the POC signal generated by PVDD2POC_V/H_G
While a common ground scheme would be:
X1 C1 PAD1 I1 OEN1 REN1 VDD1 VDDPST18 VSS1 VSS1 POC2 PRDW04DGZ_H_G
Where:
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Power/Ground Cells
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VDD1 is the core power supplied by PVDD1DGZ_V/H_G
VDDPST18 is the I/O power supplied by PVDD2DGZ_V/H_G
VSS is the shared I/O and core ground supplied by PVSS3DGZ_V/H_G
POC2 is the POC signal generated by PVDD2POC_V/H_G
Table 2.2: The Power/Ground Scheme
Power Supply
Separate Ground Scheme
Core + Pre-drivers
PVDD1DGZ_V/H_G
PVSS1DGZ_V/H_G
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1. The purpose of I/O power & ground cells (PVDD2DGZ_V/H_G) & (PVSS2DGZ_V/H_G)
is to supply the I/O pad ring. In the phantom view of I/O power/ground cell, there is no pin
on the core side. However, there exists a pin for bond pad connection.
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2. Since the VSS rail is used as the global ESD rail, and has to be continued through the
whole I/O ring, all of I/Os supplying this rail must share the same label.
2.3
The Analog Power / Ground Cells Compatible with Digital
I/O
The I/O library contains the analog power (PVDD1ANA_V/H_G, PVDD2ANA_V/H_G) & analog
ground cell (PVSS1ANA_V/H_G, PVSS2ANA_V/H_G) that can be placed right next to the digital
I/O for PLL/RAM/Voltage-Island applications, with no need to implement the power-cut cell
(PRCUT_G) in between. In other words, this type of analog power/ground cell can share a common
domain with the digital I/O. Please refer to Figure 2. for illustration.
2.3.1
The Analog Power PVDD1ANA_V/H_G & PVDD2ANA_V/H_G to
Internal Macro

PVDD1ANA_V/H_G: The analog power supply to internal macro with core voltage.

PVDD2ANA_V/H_G: The analog power supply to internal macro with I/O voltage.
Note
1. It is not necessary to place a power-cut cell (PRCUT_G) in between the
(PVDDxANA_V/H_G, PVSSxANA_V/H_G) and the digital I/O. Please refer to Figure 2.,
as well as Section 6.3 for PRCUT_G usage information.
2. When PVDD1ANA_V/H_G cell is in use, it is required to implement the
PCLAMPC_V/H_G ESD core-clamp macro for ESD robustness. Please refer to the
Section 8.7 for details.
3. When PVDD2ANA_V/H_G cell is in use, it is required to implement the PCLAMP_G
ESD I/O-clamp macro for ESD robustness. Please refer to Section 8.7 for details.
4. It is required to comply with the 1-ohm rule for PVDD2ANA_V/H_G implementation.
Please refer to Section 8.4 for details.
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Attention
PVDD1DGZ_V/H_G
PVDD2DGZ_V/H_G
(PVDD2POC_V/H_G)
PVSS3DGZ_V/H_G
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PVDD2DGZ_V/H_G
(PVDD2POC_V/H_G)
PVSS2DGZ_V/H_G
Post-drivers
Common Ground Scheme
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2.3.2
Analog Signal Transmission
The design of (PVDD1ANA_V/H_G, PVDD2ANA_V/H_G) is optimized for analog power supply
rather than analog signal transmission, where PVDD1ANA_V/H_G is the core-voltage analog power
supply, and PVDD2ANA_V/H_G is the I/O-voltage analog power supply.
For analog signal transmission:

PVDD2ANA_V/H_G is designed as analog power cell. It might be used as the I/O-voltage
analog signal cell only under certain conditions, but can never be used as the core-voltage
analog signal cell.

When using PVDD2ANA_V/H_G as signal, please pay attention on the latch-up rule
check. Please refer to Section 1.6 for details.
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The following are the conditions where the PVDD2ANA_V/H_G can be used as the I/O-voltage
analog signal cell.
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Condition 1: Connect the PVDD2ANA_V/H_G signal pin to the gate of I/O device
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As illustrated in Figure 2.2, it is required to implement your own secondary ESD protection device
(with proper dimensions) as specified in the ESD guidelines of TSMC Design Rule Manual. Also, it
is a must to ensure that PVDD2ANA_V/H_G is connected to internal I/O device following the
allowed analog victim type in Figure 2.3.
Added secondary
ESD devices
AVDD
PAD
ESD
NMOS
Signal Input Output
PVDD2ANA_V/H_G
Figure 2.2: The Secondary ESD Protection to the Gate of I/O Device
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PVDD1ANA_V/H_G can NEVER be used as the core-voltage analog signal cell or the
I/O-voltage analog signal cell.
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Passive load or active load
(note: for active load, the
“stacked” devices is needed
Analog Signal Out to
internal circuitry
Analog Signal Out to
internal circuitry
Analog Signal In from
PVDD2ANA
Analog Signal In from
PVDD2ANA
Analog Signal Out to
internal circuitry
The Prohibited Analog Victim Type
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The Allowed Analog Victim Type
Analog Signal In from
PVDD2ANA
Figure 2.3: The Allowed Analog Victim Type
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Condition 2: Connect the PVDD2ANA_V/H_G signal pin to the drain side of internal I/O device
It is required to implement your own secondary ESD protection device (with proper dimensions)
specified in the ESD guidelines of TSMC Design Rule Manual, as illustrated in Figure 2.4.
Reminder: The node A cannot be directly connected to power; the node B cannot be directly
connected to ground.
Added secondary
ESD devices
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AVDD
PAD
Signal Input Output
I/O voltage
ESD
Post driver ground
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B
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Figure 2.4: The Secondary ESD Protection Device to the Drain Side of Internal I/O Device
However, just in case the secondary ESD protection device cannot be implemented in your
application, it is a must to ensure that the internal P & N transistors (marked in yellow) of Figure 2.5
with drain side connected to the analog signal pin closely follow the ESD guidelines of TSMC Design
Rule Manual. Under this condition, the node A can be directly connected to power, and the node B
can be directly connected to ground.
A
AVDD
PAD
Signal Input Output
PVDD2ANA_V/H_G
I/O voltage
Post driver ground
B
Figure 2.5: The Internal P & N Transistor Need to Follow ESD Guidelines
2.3.3
The Analog Ground PVSS1ANA_V/H_G & PVSS2ANA_V/H_G to
Internal Macro

PVSS1ANA_V/H_G: The analog ground supply corresponding to PVDD1ANA_V/H_G.

PVSS2ANA_V/H_G: The analog ground supply corresponding to PVDD2ANA_V/H_G.
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2.3.4
Application Example
The PVDDxANA_V/H_G and PVSSxANA_V/H_G analog power & ground cells can be placed in
the digital domain without having to use the PRCUT_V/H_G / PRCUT power cut cell to save the pin
count, as shown in the below Figure.
…
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Figure 2.6: Implement PVDDxANA_V/H_G & PVSSxANA_V/H_G without the Power-Cut Cell
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If the coupling noise of digital I/O cell is a critical concern for analog power/ground, it is preferred to
create a pure analog domain without digital I/O cells. Please refer to Chapter 9 for more information
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Digital I/O
Digital I/O
PVSS2ANA_V/H_G
PVDD2ANA_V/H_G
PVSS1ANA_V/H_G
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PVDD1ANA_V/H_G
Digital I/O
Digital I/O
…
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Chapter 3
Power-Up/Down
This chapter covers the following topics:

Power-down sequence in digital domain

Power On Control (POC)

PVDD2POC_V/H_G cell implementation

LVS consideration for the POC signal

The stand-by leakage of PVDD2POC_V/H_G
Power-Up
3.1.1
Ramp-Up Time Restriction
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3.1
3.1.2
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For the powers supplied by the power cells or connected to power clamp macro cells from the TSMC
N28 I/O libraries, the ramp-up must be longer than 10us.
Power-Up Sequence in Digital Domain
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There are 3 options for the power-up sequence in digital domain:

Option 1: Preferred
Power up the I/O power (VDDPST) first and then the core power (VDD)
(PVDD2POC_V/H_G cell would generate Power-On-Control signal to have the post-driver
NMOS and PMOS off, so that the crowbar current would not occur in the post-driver fingers
when the I/O voltage is on while the core voltage remains off.)

Option 2: Acceptable
Power up I/O power and core power simultaneously

Option 3: Not recommended
Power up the core power first and then the I/O power
(Although this is not preferred, turning on the core power prior to the I/O power is also
allowed. However, note that ~uA core power leakage current may occur when VDD on and
VDDPST off. P.S. “~uA” is based on “all input control pins, e.g. OEN, set to a fixed state”.)
Note:
1. If PVDD2ANA_V/H_G is in use, ensure that the PVDD2ANA_V/H_G is powered up after the
digital I/O power PVDD2DGZ_V/H_G (or PVDD2POC_V/H_G) cell is on.
2. The VDD/VDDPST power must be fully on before the input signals of digital I/O cells toggle,
e.g. I, OEN, etc.
3. Note that PAD might have unknown state during power ramp-up.
3.2
Power-Down Sequence in Digital Domain
It’s the reverse of power-up sequence
If PVDD2ANA_V/H_G is in use, ensure that the PVDD2ANA_V/H_G is powered down before the
digital I/O power PVDD2DGZ_V/H_G (or PVDD2POC_V/H_G) cell is off.
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3.3
Power On Control (POC)
The Power-On-Control is to avoid I/O crowbar current or bus contention when the I/O voltage is up
before the core voltage.

In addition to POC signal generation, the bonded PVDD2POC_V/H_G plays the same role as
PVDD2DGZ_V/H_G digital I/O power supply that contains the I/O ESD power clamp
between VDDPST and VSSPST.

The POC signal is transmitted to I/Os through cell abutment. Therefore, no POC routing is
required. Note that the POC signal would be cut if inserting a power-cut (PRCUTx_G) cell.

When the I/O power is on while the core power remains off, the POC signal can turn off the
N- and P-MOS in the post-driver fingers. As such, I/O cell would be in the Hi-Z state during
power-up.

When POC is on, the pull-up/down resistor is disabled.
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1.8 V
Vdd
0.85 V
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Vddpst
0
0
1.8 V
POC
0
PAD
Don’t care
Hi-Z
Normal behavior
Figure 3.1: Signal Waveforms (Example for Vddpst=1.8 V; Vdd=0.85 V)
Details on the relationship among VDD, VDDPST, and POC:

POC fully turns on when VDDPST reaches around 0.5V (This value varies, depending on the
process technology.)

POC goes off when VDD reaches its threshold point around 0.7V (This value varies,
depending on process technology.)

If VDD stays off when VDDPST is on first, the POC stays on, such that there is NO crowbar
leakage current.

In case VDDPST powers up first at "slow" rate, and VDD powers up afterwards at "fast" rate,
our POC circuit can still work as long as VDDPST is greater than (pre-driver voltage VDD +
one diode voltage) during power-up.

POC is always on until VDD reaches its threshold point.
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The POC circuitry is implemented within the PVDD2POC_V/H_G cell to detect the
VDDPST-then-VDD power-up sequence, so that PVDD2POC_V/H_G would transmit the
POC signal to every digital I/O cell in the same domain.
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
Once VDD reaches its threshold point, POC turns off. Then, the state of the pad is controlled
by "I" (signal pin on the output path) and “OEN” (output enable) pin.
VDDPST
POC
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Figure 3.2: An Example of How PVDD2POC_V/H_G Cell Functions
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3.4
POC Implementation
It is mandatory to use ONE-and-Only-One PVDD2POC_V/H_G in each digital domain that contains
digital function I/O cell as illustrated in Figure 3.3. Implementation of POC cell can be achieved by
replacing one PVDD2DGZ_V/H_G with one PVDD2POC_V/H_G in each digital I/O domain.
The PVDD2POC_V/H_G cell can be either bonded out (as a POC signal generator and the post-driver
power supply), or not (as a POC signal generator only).
3.4.1
When There Is No Digital Function I/O in the Domain
When there is no digital function I/O cell in the I/O domain, it is not required to implement the
PVDD2POC_V/H_G cell. To prevent POC rail from floating, it is required to tie the POC rail to
ground.
POC1
Digital domain 1
PVDD2POC_H_G
Power cut
Analog
domain
Power cut
Power cut
POC2
PVDD2POC_V_G
Digital domain 2
ANA cells
Figure 3.3: Example of PVDD2POC_V/H_G Implementation
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VDD
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3.4.2
LVS Consideration for the POC Signal
For LVS purpose, it is necessary to put a label (for example: POC1) on the top level of POC rail. The
number of added label texts should be the same as the number of PVDD2POC_V/H_G cell
implemented on the chip, which has to be done before LVS check.
If there were no PVDD2POC_V/H_G cell implemented per digital domain as instructed, it would lead
to the floating POC node. In general, the POC rail is located in the pre-driver area.
3.5
The Stand-By Leakage Current of PVDD2POC_V/H_G
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In N28 technology, the stand-by leakage current of PVDD2POC_V/H_G cell is around ~μA level.
Please refer to the library datasheet packed in “doc” kit for the value in different PVT conditions.
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Chapter 4
The N28 Function I/O
The N28 I/O library contains digital bidirectional I/Os. The digital function I/O is named according to
the following naming convention:
P - [Slew rate] - [Pull select] - [Drive] - [Interface] - [Orientation]_G
Where:
Slew rate: defines if the I/O is with slew rate control or not.

R: with slew rate
Pull select:
DW: pull-down selectable

UW pull-up selectable
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Drive: the I/O output driving capability, it is a 2-digit number
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Interface: defines the PAD type
CDG: regular

DGZ: fail-safe

DGH: high voltage tolerant
Orientation:
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

_V: for vertical placement

_H: for horizontal placement
For example: PDDW04DGZ_V_G is a bidirectional I/O with non-slew-rate-control, programmable
pull-down, 4mA driving strength, failsafe and for vertical use.
4.1
DGZ_V/H_G Cell Name Suffix
The fail-safe digital I/O cell name has DGZ_V/H_G suffix, where DGZ_V/H_G indicates the fail safe
with staggered aspect ratio.
For example:

PDDW04DGZ_V/H_G: The fail-safe digital I/O with staggered aspect ratio indicated by the
“gv” type of I/O library (e.g. tphn28hpmgv18).
The design of TSMC fail-safe digital I/O is in particular for the “fail-safe” application that requires
I/O pad to sustain voltage without current flowing from bus to the chip, when both VDDPST (IO /
post-driver power) and VDD (core / pre-driver power) are off.
As illustrated in Figure 4.1, both chip A and C stay on while chip B is off. In this case, if Chip B is
not implemented with fail-safe I/O, current would thus flow from bus to chip B.
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Chip B
(OFF)
If there were no fail-safe digital
I/O in Chip B interface, current
would flow from Bus into Chip B
Bus
Chip C
(ON)
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Figure 4.1: Illustration of Non-Fail-Safe Scenario
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Note:
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1. The oscillator I/O cells available from the N28 hybrid library cannot be fail-safe.
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2. “Fail-safe” means “no leakage current” when power is off. When power is on, there might be a
leakage if the PAD voltage is higher than the VDDPST voltage, e.g. V(PAD)=1.98V,
V(VDDPST)=1.8V, which is similar to Regular I/O.
4.2
Programmable Pins
The programmable pins for the fail-safe digital I/O include:

OEN: To enable /disable the output path from I  PAD

REN: To enable/disable the internal Pull-up/Pull-down Resistor
Please refer to the truth table in the library databook for logic information.
Figure 4.2: An Example to Illustrate The Programmable Pins
Note:
1. It is required to disable the “pull” functions when PAD is driven by external voltage that is
greater than VDDPST.
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Chip A
(ON)
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4.3
Open Drain Emulation
TSMC digital I/O does not feature open drain. However, open drain can be emulated using the tristate output buffer.

An open drain terminal is connected to ground at the logic “0” state, but has high impedance at
the logic “1” state.

“Open drain” requires an external pull-up resistor connected to the positive voltage rail (logic
1).
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Tri-state Output Buffer
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Bus
PAD
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External PullUp Resistor
OEN
Figure 4.3: The Open Drain Emulation Diagram
As shown in Figure 4.3, the port “I” is tied to ground “0”:

When OEN=”0," the output is enabled, I = “0” would be transmitted, and the PAD turns “0”.

When OEN=”1”, the output is disabled (Hi-Z), and the PAD is pulled high by the external
pull-up resistor.
Note: Do not use the tri-state output buffer with regular input (i.e. non-fail-safe / non-high-voltinput tolerance) for open drain emulation, unless the pull-up voltage (Vpull-up) is less than the I/O
voltage (VDDPST)
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Vpull-up
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Chapter 5
The N28 Oscillator I/O
The N28 oscillator I/O cell is designed to oscillate with crystal samples from 2MHz to 30MHz in the
fundamental mode, but not designed to work in the KHz band or in overtone oscillation.
The tank circuit provided herein for fundamental oscillation is for your reference.
This section covers the following topics:

Tank circuit

Pin order

Back annotation

CUP bond pads for the oscillator I/O cells
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5.1
Oscillator I/O Introduction
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There is one type of oscillator cell: PDXOEDG_V/H_G.
The oscillator I/O comes with an enabling signal ‘E’, active high.

It contains two pins (DS0 and DS1) to control the driving strength and signal gain (gm) level.

To ensure the oscillation start-up, the negative resistance (-Re) of tank circuit must be at least
five times greater than the equivalent series resistance (ESR) of the crystal model. The greater
the negative resistance is, the faster the crystal starts to oscillate.

For the same capacitive load (CL), the higher gm leads to more negative resistance, and thus,
the oscillation can start up easier. However, the power consumption would be greater.

To select the proper oscillator I/O, a pre-check on the specification of the crystal model would
be crucial.

The key parameters for oscillation start-up are CL and the maximum ESR at the target
frequency. Reducing the CL would help to increase the negative resistance of the tank circuit.
However, if CL is too small, the deviation from the target frequency would get increased.
Therefore, there is a trade-off between the start-up time and frequency deviation in deciding
the CL.
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
Once the CL and ESR are chosen, please refer to Table 5.1 for selection guide on the oscillator I/O
cell. Note that this table is for reference only, and can only be applicable to the typical condition. If
the start-up time is less critical, the smaller gm is preferred for less power consumption. Some
conditions might require a high gm set. According to that table, if you have a 14.31818MHz
crystal part with CL=12 pF and the maximum ESR=80 Ohm, set (II) would be the first choice.
However, if CL=20pF, then set (IV) is recommended, especially when the start-up time is also a
consideration.
Table 5.1: Selection Guide for the PDXOEDG_V/H_G
Target Freq (Hz)
2M ~ 3M
3M ~ 6M
6M ~ 10M
10M ~ 20M
20M ~ 30M
CL (pF)
25
20
16
12
8
Maximum ESR (Ohm)
1K
400
100
80
40
(I)~(IV)
(I)~(IV)
(I)~(IV)
(II)~(IV)
(II)~(IV)
Selection
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(I) DS1=0, DS0=0
(II) DS1=0, DS0=1
(III) DS1=1, DS0=0
(IV) DS1=1, DS0=1
5.1.1
Tank Circuit
A reference tank circuit suitable for crystal model that oscillates in the fundamental mode is shown in
Figure 5.1. The tank circuit is composed of the oscillator I/O together with external components (Rf,
Rd, C1, C2) to ensure the oscillation start-up and stability.
DS1
DS0
E
XC
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Rf
C1
Rd
Crystal
C2
Figure 5.1: Tank Circuit for the Fundamental-Mode Oscillation

Rf represents the feedback resistor to bias the inverter in the high gain region. Rf cannot be too
low, or the loop might fail to oscillate. In general, an Rf of 1M Ohm is sufficient for MHz
band application.

Rd represents the damping resistor that helps to increase stability, save power, and suppress
gain at high frequency. The trade-off of Rd is the reduction of negative resistance. As such, Rd
cannot be too large, or the loop could fail to oscillate.

C1 and C2 can be chosen based on the crystal model or resonator CL specification. In the
steady state of oscillation, CL is defined as (C1 x C2)/(C1+C2). But since the I/O ports, bond
pad, and package pins all contribute the parasitic capacitance to C1 and C2, we can rewrite CL
to be (C1* x C2*) / (C1*+C2*), where C1* = (C1+Cin, parasitic) and C2* = (C2+Cout, parasitic). In
this example, the required C1 and C2 can be reduced.

The tank circuit is for parallel resonance rather than series resonance. As C1, C2, Rd, and Rf
depend on the crystal specification and the type of oscillator I/O in use, there is no single set of
components that can be applicable for a wide range of oscillation frequency.
5.1.2
Pin Order
There are two pins labeled “XIN” and “XOUT” for each oscillator I/O, and the layout is symmetrical.
The cell can be mirrored, so that the pin order of “XIN” and “XOUT” is reversed. Although the
mirrored oscillator I/O is functionally equivalent, problems could occur in the test mode (bypass mode)
because the external clock signal is supposed to trigger “XIN,” but not “XOUT”. To avoid this
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N28 Oscillator I/O
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problem, it is required to check the pin order carefully while dropping text onto the corresponding I/O
pin
5.1.3
Back Annotation
The XC output is derived from the XOUT through an inverter as Figure 5.1 shows. Hence, the delay
path is characterized for
(A) XIN  XOUT and (B) XOUT  XC
Here is an example of Standard Delay Format (SDF) output by Synopsys:
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IOPATH XIN XOUT (A1:A1:A1) (A2:A2:A2)
IOPATH XOUT XC (B1:B1:B1) (B2:B2:B2)
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The XIN  XC path delay would be (A2+B1:A2+B1:A2+B1) (A1+B2:A1+B2: A1+B2) when back
annotated to Synopsys.
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Verilog cannot specify delays from output to output. All delay paths must be from input to output.
Therefore, the timing path in Verilog is modeled as XIN  XC instead of XOUT  XC. This causes
a back-annotation problem when annotating Synopsys SDF in Verilog. An error message, "SDFA
Error: Could not find path XOUT to XC", would show up. The workaround is to modify the Synopsys
SDF output as follows:
IOPATH XIN XOUT (A1:A1:A1) (A2:A2:A2)
IOPATH XIN XC (A2+B1:A2+B1:A2+B1) (A1+B2:A1+B2:A1+B2)
5.1.4
Staggered CUP Bond Pads for the Oscillator I/O
For the CUP-wire-bond application, it is required to connect the PADxNU and PADxGU to the
staggered oscillator I/O as illustrated in Figure 5.2. Both pads are available from the bond pad library.
5.1.5
Clock Input Buffer
The oscillator I/O is designed for oscillation using crystal model, but NOT for the clock input buffer.
To use the oscillator I/O as an input buffer, it is required to drive the clock directly to XIN pin and
measure at XC, leaving XOUT "unloaded". The input speed would depend on the load at XC. Since
the DC characteristic (e.g. Vt, Vil, etc.) of the oscillator I/O would be different from that of the digital
I/O cell, it is required to run simulation your own to determine the DC characteristic.
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Obviously, the delay from XIN  XC is the sum of (A) and (B), which is required since the XIN 
XC delay depends on both the XOUT load and the XC load, and the Synopsys tool is operated using
this model. XIN  XOUT has one timing table and XOUT  XC has another one. If only one table
(XIN  XC) is in use, the delay would only depend on the XC load, which is certainly not the reality.
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PADxNU
Oscillator I/O
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PADxGU
Figure 5.2: The Staggered Oscillator I/O
Note:
The oscillator I/O cell available from the fail-safe library cannot be fail-safe.
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Chapter 6
Accessory Cells for N28 Digital I/Os
The accessory cells, such as filler cell (PFILLERx_G), power-cut cell (PRCUT_G), guard-band
closure cell (PENDCAP_G), and corner cell (PCORNER_G), are included in the front-end design kits,
such as Verilog and Synopsys, but no behavior is defined.
They are included in the back-end design kits, such as Apollo, Silicon Ensemble, and GDSII, where
these cells have power/ground bus connections, but no transistors nor functions.
This chapter covers the following topics:

The PCORNER_G Corner Cell

The PRCUT_G Power-Cut Cell for Digital Domain Separation

The PENDCAP_G Guard-Band Closure Cell
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The PFILLERx_G Filler Cell
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The filler cell is named PFILLERx_G, where x is related to the pr-boundary width. For example the
PFILLER1_G is 1 μm wide; PFILLER05_G is 0.5 μm wide.
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It is required to insert the wide fillers first and then the narrow fillers afterwards. To avoid the metalslot-rule violation, do not only use narrow filler cells to fill the large I/O space.
For example, to fill 30μm space between two digital I/O cells, use one 20μm pitch filler cell
(PFILLER20_G) and one 10μm pitch filler cell (PFILLER10_G) instead of using 6 “5μm pitch” filler
cells (PFILLER5_G).
PAD60NU
PFILLER
x
PAD60GU
Figure 6.1: The Filler-Cell Implementation
For ESD robustness, if the empty space is longer than one digital I/O cell width, we strongly
recommend to implement the dummy digital core power cell (PVDD1DGZ_V/H_G) or the dummy
digital I/O power cell (PVDD2DGZ_V/H_G) together with the filler cells to fill the gap, where
dummy means “not-bonded”, but used as filler cell.
However, doing so would increase the stand-by leakage current that results from the digital power
cells. Please justify it based on your leakage spec.
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The PFILLERx_G Filler Cell
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I/O
Filler
cells
I/O
I/O
Dummy
digital
power
I/O
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6.2
The PCORNER_G Corner Cell
The N28 corner cell is named PCORNER_G. It is needed to implement the PCORNER_G corner cell
available from the I/O library in the digital domain that spans two sides of the chip.
Note: It is required to implement the bonded digital I/O ground cell (PVSS2DGZ_V/H_G,
PVSS3DGZ_V/H_G) right next to each side of the corner cell for ESD consideration.
6.3
The PRCUT_G Power-Cut Cell for Digital Domain
Separation
The N28 power cut cell for domain separation is named PRCUT_G. The PRCUT_G power-cut cell
contains no device. The power (VDD, VDDPST), POC rail, and the ground (VSSPST) bus are open
within the PRCUT_G cell, while only the VSS bus (i.e. global ESD bus) stays connected through the
power-cut cell.
In addition, the PRCUT_G contains the N-well guard ring in order to close up the guard bands of the
adjacent digital I/O domains as illustrated in Figure 6.3, which can safeguard the cross-domain latchup protection.
Please refer to the top of the following page for the power-cut cell usage requirement.
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Figure 6.2: The Dummy Digital Power Cell Implementation. Filler cells (left) are replaced with
dummy digital power (right)
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POC1
VDD1 (e.g. 0.85V)
POC2
VDD2 (e.g. 0.8V)
VSS
VSS
VDDPST1 (e.g. 1.8V)
VDDPST (e.g. 1.5V)
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Digital Domain I
PRCUT_G
PRCUT_G
Digital Domain II
Figure 6.3: The PRCUT Cell Scheme & Layout
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Guard band closure
on both sides
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Note
1. It is required to implement the PRCUT_G cell between two digital I/O domains implemented
with the I/O cells that belong to the same I/O library but are operated at different domain
voltage.
2. For the robust cross-domain ESD & latch-up protection, it is required to implement the digital
ground (PVSS1DGZ_V/H_G / PVSS3DGZ_V/H_G) right next to the power-cut cell. Doing
so can shorten the ESD discharge path across domains.
6.4
The PENDCAP_G Guard-Band Closure Cell
The guard band closure cell is named PENDCAP_G. When digital I/O cells are not implemented in a
ring (e.g. L shape), it is required to implement the PENDCAP_G guard-band-closure cell on the
domain edge for latch-up protection. Different from the PRCUT_G power-cut cell that can close the
guard bands on both sides of PRCUT_G, the PENDCAP_G can close the guard band on one side.
In other words, it is required to mirror PENDCAP_G horizontally to close the guard band on the other
side of the domain edge.
The mirrored
PENDCAP_G
N28 digital I/Os
PENDCAP_G
It is required to implement either
digital Power or digital Ground cell
right beside the PENDCAP_G cell
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VSSPST
VSSPST
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Note
1. When using PENDCAP_G cell, please fulfill the rules described in a separate file named
“ApplicationGuide_N28_AAIO”, which is available on tsmc online.
2. Please make sure that the N-Well /P-Sub in the circuit layout around the PENDCAP_G cell
is connected to power/ground solidly. It is recommended to have the connection resistance
within 1 ohm.
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Figure 6.4: The PENDCAP_G Cell Implementation
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3. The I/O library design uses VSS as global ESD bus. Therefore, VSS bus of all the I/O cells
must be connected together for ESD robustness even if PENDCAP_G is in use. It is
required to have VSS connection complied with the "Maximum ESD Current Density for
Via, and Metal" table in DRM.
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Chapter 7
Simultaneously Switching Output
Considerations
This chapter provides information about the following topics:
Terminology and Definition

SSO Simulation Model

Calculation for the Required Number of I/O Power & Ground cells

Time to Valid State
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Terminology and Definition
7.1.1
Simultaneously Switching Output
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Simultaneously Switching Noise
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The Simultaneously Switching Output (SSO) effect occurs when I/O output buffers are switching
simultaneously in the same direction (H  L, HZ L or L  H, LZ  H), resulting in noise on the
I/O power & ground bus.
The Simultaneously Switching Noise (SSN) is the noise produced by simultaneously switching output
buffers. SSN changes the voltage levels of power/ground nodes, creating the so-called “Ground
Bounce Effect”, which is tested at the device output by keeping one stable output at low “0” or high
“1,” while all the other output device are switching simultaneously. The noise that occurs at the stable
output node is called “Quiet Output Switching” (QOS). If the input low voltage is defined as Vil, the
QOS of Vil is considered the maximum noise that the system can endure.
7.1.3
Driving Index
The Driving Index (DI) is the maximum number of I/O output drivers switching from high to low
simultaneously without making the voltage on the quiet output “0” higher than a threshold value “Vil”
when a single I/O ground cell is applied.
7.1.4
Driving Factor
The Driving Factor (DF) is the SSN amount that the output buffer contributes to at the I/O power &
ground rails. The DF value of an output buffer is proportional to dI/dt, the derivative of the current on
the output buffer. DF can be obtained by:
DF = 1/DI
7.1.5
Sum of Driving Factors
The Sum of Driving Factors (SDF) is the sum of DF values of all the digital output drivers in a single
I/O domain, which can be used to determine the required number of “bonded” I/O power & “bonded”
I/O ground cells in this particular domain to avoid the ground-bounced noise effect (SSN).

For the SSO case (i.e. the I/O cell is used as an output driver)
The required number of “bonded” digital I/O ground cell = SDF
The required number of “bonded” digital I/O power cell = SDF / 1.1
Reminder: As for the required number of “bonded” digital I/O power & “bonded” digital I/O
ground cells, it is required to meet the SSO requirement as well as the VDDPST & VSSPST
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metal-bus resistance requirement (i.e. 1 ohm), which can be found in Section 8.4.

For the non-SSO case (i.e. the I/O cell is used as an input buffer)
If all the digital I/O cells in the I/O domain function as input buffers, to determine the required
number of “bonded” digital I/O power and “bonded” digital I/O ground cells, it is a must to take the
VDDPST (I/O power) and VSSPST (I/O ground) metal bus resistance requirement into account.
Please refer to Section 8.4 for details.
SSO Simulation Model
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As Figure 7.1 shows, each I/O power/ground net and output node are modeled with individual RLC
circuit based on the package type.
Rvdd
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Lvdd
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Vi
Lpin
Quiet
I/O cell
Rpin
Cpin
Vin
Vo
Cload
Lpin
A
SSO I/O
cells
Rpin
Cpin
Vout
Cload
Lvss
Cvss
Rvss
Figure 7.1: The Model for SSO Simulation
Vin represents the input node of SSO I/O cells. When Vin toggles, all the SSO I/O cells are switching
simultaneously and the change of the current (I) on Lvss could be high. Therefore, the noise of [Lvss
* (dI/dt)] would be generated at node A.
Meanwhile, another quiet I/O cell grounded to node A is transmitting a “0” through Vo at the same
time. The “0” could be recognized as “1” if the noise at Vo is greater than Vil at node A. DI is the
minimal number of SSO I/O cells that contribute noise of Vil at Vo. DF can be calculated from DI:
1/DI = DF
The worst SSN happens in the Fast-Fast process corner with + 10% pre-driver & + 10% post-driver
power at low temperature. As such, the DF is characterized in the low-temp process condition, and
available in the library databook.
7.3
Calculate the Required Number of I/O Power/Ground Cell
By referring to the DF table in the library databook, we can calculate the required number of bonded
I/O power/ground cell to avoid SSN in each digital domain, if there is any I/O cell used as the output
driver.
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For example,
1. Check the DF value for a specific output driving strength:
If four copies of the SSO I/O cell with one ground cell (Lvss) cause noise “Vil,” the DI is 4 and
the DF is 1/4 = 0.25. You can check the DF table in the library databook corresponding to the
package bond wire inductance (Lvdd, Lvss, Lpin) and different capacitive loads. Below is an example.
e\
SDF can be obtained by summing up the total DF values applicable to each digital I/O domain.
For example, consider the design with ten 8 mA output buffers, six 12 mA output buffers, and
twelve 16 mA slew-rate-controlled output buffers. If the DF value (based on 7.8 nH bond-wire
inductance and 15 pF capacitive load) corresponding to 8 mA, 12 mA, and 16 mA output driving
strength are 0.352, 0.556, and 0.649, respectively, the SDF can be calculated as:
10 x 0.352 + 6 x 0.556 + 12 x 0.649 = 14.644
3. Obtain the required number of “bonded” digital I/O power & “bonded” digital I/O ground
cells for SSO case:
The required number of bonded digital I/O ground cell = 14.644  15
The required number of bonded digital I/O power cell = 14.644 / 1.1 = 13.31  14
As calculated above, to avoid SSN effect, the required number of bonded digital I/O ground cell is 15;
the required number of bonded digital I/O power cell is 14.
7.4
How to Reduce SSN

Use the output driver with small driving strength.

Use the output driver with slew-rate control, if possible.

Insert sufficient number of bonded digital I/O power and bonded digital I/O ground cells.

Place the noise-sensitive cells away from the SSO I/Os.

Apply double bonds to 2 identical digital I/O power or 2 identical digital I/O ground cells to
reduce bond-wire inductance.
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2. Calculate the SDF in each digital I/O domain:
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Chapter 8
The ESD & Latch-Up Considerations
for N28 Digital I/Os
This chapter provides information about the following topics:

The Global ESD bus

The Dummy Power/Ground Cell Insertion

The Power/Ground Metal Bus Resistance Requirement

The 20pF Requirement

The Required Power/Ground Cell Number

The ESD Clamp Macro

The PRCUT_G Power-Cut Cell and PENDCAP_G Guard-Band Closure Cell

How to Integrate TSMC I/O with the 3rd Party IP
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8.1
The ESD Network
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The digital I/O, Power, Ground cells of TSMC I/O library contain the ESD clamping circuitry to
To internal macro
To digital core
PCLAMPC_V/H_G
PCLAMP_G
VDD
AVSS
AVDD
AVSS
C
AVDD
VSS
VDD
ESD clamp
ESD clamp
ESD clamp
ESD clamp
ESD clamp
ESD clamp
ESD clamp
ESD clamp
ESD clamp
VSS
VDDPST
ESD clamp
ESD clamp
ESD clamp
ESD clamp ESD clamp
ESD clamp
ESD clamp ESD clamp
ESD clamp
ESD clamp
VSSPST
PVSS1ANA_V/H_G
PVSS2ANA_V/H_G
PVDD1ANA_V/H_G
PVDD1DGZ_V/H_G
PVDD2ANA_V/H_G
PVSS1DGZ_V/H_G
PVDD2DGZ_V/H_G
I/O
PVDD2POC_V/H_G
PVSS2DGZ_V/H_G
construct the ESD protection network as illustrated in Figure 8.1.
Figure 8.1: ESD Protection Scheme for Power/Ground/IO Cells
8.2
The Global ESD Bus
TSMC I/O design is using VSS as global ESD bus.
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VSS global
ESD bus
I/O ring
Core
Figure 8.2: Global ESD Bus – VSS
To achieve robust ESD protection, it is required to have VSS pin of PVSS1DGZ_G or
PVSS3DGZ_G connected to VSS core ground mesh to make the VSS as chip-level global.
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
L-Shape I/O Placement
U-Shape I/O Placement
Core P/G Mesh
Core P/G Mesh
Figure 8.2: I/O Implementation in L Shape / U Shape

When the I/O cell placement does not form a ring (e.g. L shape), it is required to have VSS
connection from the I/O domain to the 3rd party IP nearby.

All the connections mentioned above must comply with "Maximum ESD Current Density for
Via, and Metal" table in DRM.
8.3
The Dummy Power / Ground Cell
To achieve short ESD discharge path, it is strongly suggested to replace some of the filler cells with
the dummy power or ground cells if space is allowed, where dummy means “not bonded”, simply
used as the filler cells. Please refer to Figure 8.3 for illustration.
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Die edge
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Note that the power/ground cells contain ESD clamp circuitry; whereas the filler cells do not. At the
package phase, dummy power/ground is not bonded, so that the total pin count would not get
impacted. However, the only trade-off is increase in the stand-by leakage current of the dummy
power/ground cell. Please judge it based on the total stand-by leakage spec.
I/O
I/O
I/O
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Dummy
digital
power
Filler cells
Filler cells
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Figure 8.3: Replace Filler Cells with Dummy Power Cells
8.4
The ESD Power / Ground Metal Bus Resistance
Requirement
The ESD power/ground metal bus resistance “R” from cell A to cell B can be calculated as illustrated
in Figure 8.4.
R = Rsheet x L/W, where Rsheet is available from the spice model card.
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Filler
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I/O
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Core
W
Bus
Line
L
Cell B
Cell A
“Bonded” pad
“Bonded” pad
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Within the same digital domain, it is required to ensure that the metal bus resistance CANNOT be
greater than the value listed in the Table 8.1.
M
PVSS2DGZ_V/H_G
PVDD1ANA_V/H_G
PVSS1ANA_V/H_G
PVDD2ANA_V/H_G
PVSS2ANA_V/H_G
PVDD2DGZ_V/H_G
PVDD2POC_V/H_G
PVSS1DGZ_V/H_G
PVDD1DGZ_V/H_G
PVDD2DGZ_V/H_G
PVDD2POC_V/H_G
Function I/O
PVDD1DGZ_V/H_G
Function I/O
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Table 8.1: The max resistance between different I/O types
3
1
3
1
N/A
N/A
N/A
N/A
3
1
3
1
1
N/A
N/A
1
1
N/A
N/A
1
3
3
1
1
3
3
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
3
1
3
3
1
1
1
3
1
3
PVDD1ANA_V/H_G
N/A
1
N/A
1
N/A
PVSS1ANA_V/H_G
N/A
1
N/A
1
N/A
1
PVDD2ANA_V/H_G
N/A
N/A
1
3
N/A
N/A
N/A
PVSS2ANA_V/H_G
N/A
N/A
3
3
N/A
N/A
N/A
PVSS1DGZ_V/H_G
PVSS2DGZ_V/H_G
8.5
1
1
The 20pF Requirement
The minimal capacitive load between the “AVDD” pin on the core side of (PVDD1ANA_V/H_G,
PVDD2ANA_V/H_G) and the “AVSS” pin on the core side of (PVSS1ANA_V/H_G,
PVSS2ANA_V/H_G) is 20pF.
If insufficient, it is required to insert the decoupling capacitor. Please refer to Figure 8.5 for
illustration.
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Figure 8.4: Illustration of Bus Resistance Calculation
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AVSS
AVDD
AVSS
AVDD
> 20 pF
> 20 pF
VDD
ESD Clamp
ESD Clamp
ESD Clamp
ESD Clamp
VSS
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ESD Clamp
ESD Clamp
ESD Clamp
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ESD Clamp
ESD Clamp
VSSPST
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PVSS2ANA_V/H_G
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PVDD1ANA_V/H_G
PVDD2ANA_V/H_G
Figure 8.5: The 20pF Requirement
8.6
The Required Power / Ground Cell Number
To achieve robust ESD/latch-up protection, it is required to meet the cell-number requirement in each
power domain as mentioned below:

PVDD1DGZ_V/H_G digital core power cell: “At least” 3 bonded ones.

PVDD2DGZ_V/H_G digital I/O power cell: “At least” 2 bonded ones. The total number of the
bonded cells must meet the SSO requirement as well as the 1-ohm or 3-ohm VDDPST bus
resistance requirement.

PVDD2POC_V/H_G Power-on-Control cell: It is required to implement “one and only one”
POC cell, which can be either bonded or not. When POC cell is bonded, it can function as a
digital I/O power supply and POC signal generator. When POC cell is not bonded, it simply
functions as a POC signal generator.

PVSS1DGZ_V/H_G, PVSS3DGZ_V/H_G digital core ground cell: “At least” 1 bonded one.
The total number of the bonded cells must meet the 1-ohm or 3-ohm VSS bus resistance
requirement.

PVSS2DGZ_V/H_G, PVSS3DGZ_V/H_G digital I/O ground cell: “At least” 1 bonded one.
The total number of the bonded cells must meet the SSO requirement as well as the 1-ohm or
3-ohm VSSPST/ VSS bus resistance requirement.

PVDD1ANA_V/H_G core-voltage analog power cell: When core-voltage analog power cell is
needed, PVDD1ANA_V/H_G can be an option. The minimal required cell number for bonded
PVDD1ANA_V/H_G is 3 for ESD robustness. For instance, place three PVDD1ANA cells
together and triple bond them.

PVDD2ANA_V/H_G IO-voltage analog power cell: When IO-voltage analog power cell is
needed, PVDD2ANA_V/H_G can be an option. The minimal required cell number for bonded
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PVDD2ANA_V/H_G is 2 for ESD robustness. For instance, place two PVDD2ANA cells
together and double bond them.

PVSS1ANA_V/H_G, PVSS2ANA_V/H_G analog ground cell: When analog ground cell is
needed, PVSSxANA_V/H_G can be an option. It can be used in pair with
PVDDxANA_V/H_G analog power.
Note: PVDDxANA_V/H_G/PVSSxANA_V/H_G cannot be implemented alone in a single domain
without bonded digital power and bonded digital ground cells. Please refer to Chapter 2 for details.
8.7.1
PCLAMPC_V/H_G ESD Core-Clamp Macro
When to use it: While using PVDD1ANA_V/H_G (core-voltage analog power), it is required
to use at least one PCLAMPC_V/H_G together with PVDD1ANA_V/H_G analog power and
PVSS1ANA_V/H_G analog ground pair.
PCLAMP_G ESD I/O-Clamp Macro
e\

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
When to use it: While using PVDD2ANA_V/H_G (IO-voltage analog power), it is required
to use at least one PCLAMP_G together with PVDD2ANA_V/H_G analog power and
PVSS2ANA_V/H_G analog ground pair.
Note: The PCLAMP_G can be implemented together with PVDD2ANA_V/H_G and
PVSS2ANA_V/H_G, only if PVDD2ANA_V/H_G is used as the I/O-voltage analog power cell. It
is prohibited to use PCLAMP_G if PVDD2ANA_V/H_G is used as the I/O-voltage analog signal
cell.
8.7.3
Implement PCLAMPC_V/H_G / PCLAMP_G Macro on the Core
Side
The procedure to implement PCLAMPC_V/H_G / PCLAMP_G macro are as follows, where x can be
“1” or “2”, depending on the type of analog power & ground pair in use.
Step 1: Place PVDDxANA_V/H_G analog power and PVSSxANA_V/H_G analog ground cell of the
same type (i.e. either for core voltage or I/O voltage) together.
Step 2: Place PCLAMPC_V/H_G cell in between (the PVDD1ANA_V/H_G analog power &
PVSS1ANA_V/H_G analog ground pair) and internal core; or place PCLAMP_G cell in between (the
PVDD2ANA_V/H_G analog power & PVSS2ANA_V/H_G analog ground pair) and internal core
Step 3: Connect from AVDD pin of the PVDDxANA_V/H_G to VDDESD pin of the
PCLAMPC_V/H_G / PCLAMP_G macro.
Step 4: Connect from AVSS pin of PVSSxANA_V/H_G to VSSESD pin of the PCLAMPC_V/H_G /
PCLAMP_G macro.
Step 5: Connect from VDDESD and VSSESD rails of PCLAMPC_V/H_G / PCLAMP_G macro to
internal power rail and ground rail respectively, as illustrated in Figure 8.6.
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8.7
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Analog Macro
To internal core
power and ground
PCLAMPC_V/H_G/PCLAMP_G
Metal connection between
Analog P/G and the
PCLAMP macro
Std I/Os
Std I/Os
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Figure 8.6: Illustration of PCLAMPx Macro Implementation
8.8
The PCORNER_G Corner Cell
It is required to implement the bonded digital I/O ground (PVSS2DGZ_V/H_G, PVSS3DGZ_V/H_G)
right next to the PCORNER_G corner cell (on both sides) for ESD consideration. Please refer to
Section 6.2 for details.
8.9
The PRCUT_G Power-Cut Cell for Digital Domain
Separation
It is required to implement the PRCUT_V/H_G power-cut cell between TWO digital I/O domains
using the same I/O library. Please refer to Section 6.3 for details. It is also required to implement the
bonded digital ground (PVSS1DGZ_V/H_G, PVSS3DGZ_V/H_G) beside the PRCUT_V/H_G.
8.10 The PENDCAP_G Guard-Band Closure Cell
The PENDCAP_G guard-band-closure cell is to insert the guard ring on the domain edge. Different
from the PRCUT_G power-cut cell that can close the guard bands on both sides of power-cut cell,
PENDCAP_G can close the guard band on one side. Please refer to Section 6.4 for details.
8.11 How to Integrate TSMC I/O with Other IP
VSS is the global ESD bus for TSMC I/O. To integrate TSMC I/O with other IP, it is required to
comply with the following rules to avoid the detrimental application issue resulting from
inappropriate integration.
Note
1. TSMC cannot guarantee the ESD & latch-up if the TSMC I/O is mixed with other IP in a
common domain.
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PVDDxANA_V/H_G
+
PVSSxANA_V/H_G
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2. It is required to implement the PENDCAP_G guard-band closure cell between the
digital I/O domain and other IP. Furthermore, it is required to comply with the
application requirements stated in Section 6.4.
3. As to the power/ground metal connection at the domain interface, it is necessary to avoid
the 90-degree metal bus connection as illustrated in Figure 8.7. For ESD robustness, please
adopt the 135-degree metal connection as illustrated in Figure 8.8.
4. It is required to connect the global ESD bus of other IP to the VSS bus of TSMC I/O (e.g.
through mesh, or direct metal connection). The VSS connection must comply with the
"Maximum ESD Current Density for Via, and Metal" table in DRM.
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5. Other IP design & implementation must comply with TSMC ESD rules/guidelines.
Figure 8.7: Illustration of the 90-degree Metal Connection
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Figure 8.8: Illustration of the 135-degree Metal Connection
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Chapter 9
The N28 Analog I/O
The analog I/O cells are available from the N28 hybrid I/O library, featuring a single library that
contains both analog I/O and the corresponding digital I/O cells. For the application requirements on
digital I/O, please refer to Section 1.5 for read guide.
This chapter covers the following topics:

The PDB3A_V/H_G, PDB3AC_V/H_G analog I/O signal cell

The PVDD3A_V/H_G, PVDD3AC_V/H_G analog power cell

The PVSS3A_V/H_G, PVSS3AC_V/H_G analog ground cell

The PVDD1A_V/H_G, PVDD1AC_V/H_G analog power cell

The PVSS1A_V/H_G, PVSS1AC_V/H_G analog ground cell

The PVSS2A_V/H_G, PVSS2AC_V/H_G global ESD ground bus (VSS) supply

The PFILLERxA_G, PCORNERA_G, PRCUTA_G, PENDCAPA_G accessory cell
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Analog I/O Power / Ground Rail
e\
9.1
This section provides information on the analog I/O power/ground rail configuration. Please make
sure that the power & ground rail(s) of each analog I/O cell are well connected through cell abutment.

TAVDD/TACVDD Power Bus: As indicated in Figure 9.2, the analog I/O is powered by the
TAVDD/TACVDD power rail, where TAVDD is for analog domain supplied by the I/O
voltage, whereas TACVDD is for analog domain supplied by the core voltage.

VSS Global ESD Bus: VSS of the analog I/O is used as the global ESD ground bus.

TAVSS/TACVSS Ground Bus: As indicated in Figure 9.2, the TAVSS/ TACVSS bus is only
implemented within the staggered analog I/O, where TAVSS is for analog domain supplied by
the I/O voltage, whereas TACVSS is for analog domain supplied by the core voltage.
9.2
PDB3A_V/H_G, PDB3AC_V/H_G Analog Signal Cell
Figure 9.1 illustrates the general structure of (PDB3A_V/H_G, PDB3AC_V/H_G) analog signal cell
with the ESD clamping device to power/ground bus.
Power
ESD device
To PAD side
To analog
macro
Signal Input Output
ESD device
Ground
Figure 9.1: The PDB3A/AC_V/H_G General Structure
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The Analog I/O Power/Ground Rail
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
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Table 9.1: Analog Signal Cell Category
Domain Type
For the domain
supplied by core
voltage
In-Pairs
PDB3AC_V/H_G
Pair up with PVDD3AC_V/H_G, PVSS3AC_V/H_G,
PVSS2AC_V/H_G, PCLAMPC_V/H_G in the corevoltage analog domain separated by PRCUTA_G
power-cut cell or PENDCAPA_G guard-ring closure
cell.
PDB3A_V/H_G
M
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Pair up with PVDD3A_V/H_G, PVSS3A_V/H_G,
PVSS2A_V/H_G, PCLAMP_G in the I/O-voltage
analog domain separated by PRCUTA_G power-cut
cell or PENDCAPA_G guard-ring closure cell.
The Figure 9.2 below depicts the ESD scheme of PDB3A_V/H_G / PDB3AC_V/H_G with staggered
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AIO (to Analog Macro)
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AIO (to Analog Macro)
VSS (Global ESD Bus)
VSS (Global ESD Bus)
e\
ESD Device
ESD Device
TAVDD (Power Bus)
TACVDD (Power Bus)
ESD Device
ESD Device
ESD Device
ESD Device
TACVSS (ESD Ground Bus)
TAVSS (ESD Ground Bus)
To PAD
PDB3A_V/H_G
To PAD
PDB3AC_G
(for Analog Domain supplied by I/O Voltage)
aspect ratio.
(for Analog Domain supplied by Core Voltage)
Figure 9.2: The ESD Scheme of Analog I/O Signal Cell
Note
1. Due to the poly orientation restriction in the N28 design rule, the cells containing “_V” are
for vertical usage, while the ones containing “_H” are for horizontal usage.
2. The equivalent capacitance of the I/O cell can be obtained from the library datasheet or
Synopsys timing power design kit. It is necessary to verify by simulation if the
PDB3A/AC_V/H_G is suitable for your application.
3. For signal integrity, the signal swing cannot exceed the power rail voltage (Core or I/O) by
0.3V, nor go under the ground rail voltage by 0.3V.
4. If PDB3A/AC_V/H_G is connected to the internal gate, it is required to insert the
secondary ESD protection devices as illustrated in Figure 9.3 to ensure optimal ESD
protection.
5. If PDB3A/AC_V/H_G is connected to the internal drain, it is required to either insert the
secondary ESD protection devices as illustrated in Figure 9.5, or follow the ESD guideline
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For the domain
supplied by I/O
voltage
Cell Name
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specified in TSMC Design Rule Manual.
6. The PDB3AC_V/H_G can only be connected to internal core device; whereas the
PDB3A_V/H_G can only be connected to internal I/O device.
The following are the conditions where the PDB3A_V/H_G / PDB3AC_V/H_G is connected to
internal analog macro.

Condition 1: Connect the PDB3A_V/H_G / PDB3AC_V/H_G to the internal gate
AIO
ESD
NMOS
e\
Signal Input Output
PDB3A/AC_V/H_G
Figure 9.3: The Secondary ESD Protection Device to Internal Gate
Passive load or active load
(note: for active load, the
“stacked” devices is needed
Analog Signal Out to
internal circuitry
Analog Signal In from
PDB3A/AC
Analog Signal Out to
internal circuitry
Analog Signal In from
PDB3A/AC
Analog Signal Out to
internal circuitry
Analog Signal In from
PDB3A/AC
The Allowed Analog Victim Type
The Prohibited Analog Victim Type
Figure 9.4: The Allowed Analog Victim Type

Condition 2: Connect the PDB3A_V/H_G / PDB3AC_V/H_G to the drain side of internal
device
It is required to implement your own secondary ESD protection device (with proper dimensions) as
specified in the ESD guideline of TSMC Design Rule Manual, as illustrated in Figure 9.5.
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AIO
Added secondary
ESD devices
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Figure 9.3 illustrates that it is required to implement your own secondary ESD protection device (with
proper dimensions) as specified in the ESD guideline of TSMC Design Rule Manual. Note that
PDB3A_V/H_G must get connected to internal I/O device, and PDB3AC_V/H_G must get connected
to internal core device. Figure 9.4 denotes the allowed analog victim type that needs your attention.
Security C - TSMC Secret
Added secondary
ESD devices
AIO
AIO
ESD
Signal Input Output
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Figure 9.5: The Secondary ESD Protection Device to Internal Drain
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However, if the secondary ESD protection device cannot be implemented in your application, it is a
must to ensure that the internal P & N transistors (as indicated in yellow) with drain side connected to
the analog signal pin closely follow the ESD guidelines of TSMC Design Rule Manual.
9.3
PVDD3A_V/H_G / PVDD3AC_V/H_G Analog Power Cell
The PVDD3A_V/H_G / PVDD3AC_V/H_G is the analog power supply to both analog macro and I/O
power rail, where the PVDD3AC_V/H_G is to supply both analog macro and TACVDD I/O power
rail with core voltage, while PVDD3A_V/H_G is to supply both analog macro and TAVDD I/O
power rail with I/O voltage.
The Figure 9.6 depicts the ESD scheme of PVDD3A_V/H_G and PVDD3AC_V/H_G cell.
AVDD (to Analog Macro)
AVDD (to Analog Macro)
Dummy resistor
Dummy resistor
VSS (Global ESD Bus)
ESD Device
VSS (Global ESD Bus)
ESD Device
TAVDD (Power Bus)
ESD Device
TACVDD (Power Bus)
ESD Device
TACVSS (ESD Ground Bus)
TAVSS (ESD Ground Bus)
PVDD3A_V/H_G
PVDD3AC_V/H_G
(for Analog Domain supplied by I/O Voltage)
(for Analog Domain supplied by Core Voltage)
Figure 9.6: The ESD Scheme for Analog Power Cell
Note:
1. It is prohibited to mix PVDD3A_V/H_G and PVDD3AC_V/H_G in a common domain.
2. For the powers supplied by the power cells or connected to power clamp macro cells from the
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TSMC I/O libraries, the ramp-up must be longer than 10us.
Table 9.2: Analog Power Cell Category
Cell Name
Port to core
Port to PAD
Power &
Ground Bus
Core Voltage
PVDD3AC_V/H_G
AVDD
TACVDD
TACVDD,
VSS, TACVSS
I/O Voltage
PVDD3A_V/H_G
AVDD
TAVDD
TAVDD,
VSS, TAVSS
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9.4
PVSS3A_V/H_G, PVSS3AC_V/H_G Analog Ground Cell
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Figure 9.7 presents the PVSS3A_V/H_G, PVSS3AC_V/H_G ESD scheme. The PVSS3AC_V/H_G
is to supply both analog macro and TACVSS I/O ground rail and needs to be implemented in the
core-voltage analog domain, while the PVSS3A_V/H_G is to supply both analog macro and TAVSS
I/O ground rail and needs to be implemented in the I/O-voltage analog domain.
AVSS (to Analog Macro)
AVSS (to Analog Macro)
e\
Dummy resistor
Dummy resistor
VSS (Global ESD Bus)
VSS (Global ESD Bus)
ESD Device
ESD Device
TAVDD (Power Bus)
TACVDD (Power Bus)
ESD Device
ESD Device
TACVSS (ESD Ground Bus)
TAVSS (ESD Ground Bus)
PVSS3A_V/H_G
PVSS3AC_V/H_G
(for Analog Domain supplied by I/O Voltage)
(for Analog Domain supplied by Core Voltage)
Figure 9.7: The ESD Scheme for Analog Ground Cell
Note: PVSS3A_V/H_G needs to be used with PVDD3A_V/H_G, while PVSS3AC_V/H_G needs
to be used with PVDD3AC_V/H_G.
Table 9.3: Analog Ground Cell Category
Analog Domain
Cell Name
Port to core
Port to PAD
Power &
Ground Bus
Core Voltage
PVSS3AC_V/H_G
AVSS
TACVSS
TACVDD,
VSS, TACVSS
I/O Voltage
PVSS3A_V/H_G
AVSS
TAVSS
TAVDD,
VSS, TAVSS
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9.5
PVDD1A_V/H_G / PVDD1AC_V/H_G Analog Power Cell
The PVDD1A_V/H_G / PVDD1AC_V/H_G is the analog power supply to the analog macro, where
the PVDD1AC_V/H_G is to supply the analog macro with core voltage, while the PVDD1A_V/H_G
is to supply the analog macro with I/O voltage.
Figure 9.8 depicts the ESD scheme of PVDD1A_V/H_G and PVDD1AC_V/H_G cell.
AVDD (to Analog Macro)
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AVDD (to Analog Macro)
VSS (Global ESD Bus)
VSS (Global ESD Bus)
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ESD Device
ESD Device
ESD Device
ESD Device
TAVDD (Power Bus)
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TACVDD (Power Bus)
TACVSS (ESD Ground Bus)
TAVSS (ESD Ground Bus)
PVDD1A_V/H_G
(for Analog Macro supplied by I/O Voltage)
PVDD1AC_V/H_G
(for Analog Macro supplied by Core Voltage)
Figure 9.8: The ESD Scheme for PVDD1A_V/H_G / PVDD1AC_V/H_G
Note that there is no connection between the ‘AVDD’ of the PVDD1A_V/H_G / PVDD1AC_V/H_G
and the TAVDD / TACVDD power rail. As such, PVDD1A_V/H_G and PVDD1AC_V/H_G can be
used in the same power domain. That is, PVDD1A_V/H_G can be directly placed in an analog power
domain supplied with core voltage. Similarly, PVDD1AC_V/H_G can be used in an analog power
domain supplied with I/O voltage, for example 1.8V.
Note:
1. PVDD1AC_V/H_G is to supply a core analog macro made of core devices, while
PVDD1A_V/H_G is to supply a core analog macro made of I/O devices.
2. For the powers supplied by the power cells or connected to power clamp macro cells from the
TSMC I/O libraries, the ramp-up must be longer than 10us.
9.6
PVSS1A_V/H_G, PVSS1AC_V/H_G Analog Ground Cell
Figure 9.9 presents the PVSS1A_V/H_G, PVSS1AC_V/H_G ESD scheme. The PVSS1A_V/H_G /
PVSS1AC_V/H_G is the analog ground supply to the analog macro. The PVSS1AC_V/H_G needs to
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PVDD1A_V/H_G / PVDD1AC_V/H_G is to supply the analog macro with dedicated power, and
cannot be used for Tx/Rx power and ground. For this case, it is necessary to use the
PVDD3A_V/H_G / PVDD3AC_V/H_G.
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be used with the PVDD1AC_V/H_G. The PVSS1A_V/H_G needs to be used with the
PVDD1A_V/H_G.
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AVSS (to Analog Macro)
AVSS (to Analog Macro)
VSS (Global ESD Bus)
ESD Device
VSS (Global ESD Bus)
ESD Device
TAVDD (Power Bus)
ESD Device
ESD Device
ESD Device
TACVSS (ESD Ground Bus)
PVSS1A_V/H_G
PVSS1AC_V/H_G
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TAVSS (ESD Ground Bus)
(for Analog Macro supplied by I/O Voltage)
(for Analog Macro supplied by Core Voltage)
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Figure 9.9: The ESD Scheme for PVSS1A_V/H_G / PVSS1AC_V/H_G
PVSS2A_V/H_G, PVSS2AC_V/H_G Global ESD Ground
Bus VSS Supply
The PVSS2A_V/H_G, PVSS2AC_V/H_G cell is to supply the VSS global ESD bus in analog I/O
domain. Figure 9.10 presents the (PVSS2A_V/H_G, PVSS2AC_V/H_G) ESD scheme. Note that
PVSS2A_V/H_G and PVSS2AC_V/H_G have pin out to core, and can be used to supply the common
ground to the core region, as well as to supply the global ESD ground bus, VSS, in the analog domain.
It is required to implement the “bonded” PVSS2A_V/H_G in the I/O-voltage analog domain, and the
“bonded” PVSS2AC_V/H_G in the core-voltage analog domain. Please refer to Chapter 10 for details.
VSS (Global ESD Bus)
VSS (Global ESD Bus)
TAVDD (Power Bus)
TACVDD (Power Bus)
ESD Device
ESD Device
ESD Device
ESD Device
TACVSS (ESD Ground Bus)
TAVSS (ESD Ground Bus)
PVSS2A_V/H_G
PVSS2AC_V/H_G
(for Analog Domain supplied by I/O Voltage)
(for Analog Domain supplied by Core Voltage)
Figure 9.10: The ESD Scheme for the VSS ESD Ground Bus Supply
Note: It is prohibited to mix PVSS2A_V/H_G with PVSS2AC_V/H_G in a common domain.
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ESD Device
TACVDD (Power Bus)
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Table 9.4: The VSS ESD Bus Supply Cell Category
Analog Domain
Cell Name
Port to core
Port to PAD
Power &
Ground Bus
Core Voltage
PVSS2AC_V/H_G
VSS
VSS
TACVDD, VSS,
TACVSS
I/O Voltage
PVSS2A_V/H_G
VSS
VSS
TAVDD, VSS,
TAVSS
9.8.1
The PFILLERxA_G Filler Cell
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PFILLERxA_G, PCORNERA_G, PRCUTA_G,
PENDCAPA_G Accessory Cell
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The filler cell for analog domain is named PFILLERxA_G, where x is related to the pr-boundary
width. For example the PFILLER1A_G is 1 μm wide; PFILLER05A_G is 0.5 μm wide.
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It is required to insert the wide fillers first and then the narrow fillers afterwards. To avoid the metalslot-rule violation, do not only use narrow filler cells to fill the large I/O space.
For example, to fill 30μm space between two analog I/O cells, use one 20μm pitch filler cell
(PFILLER20A_G) and one 10μm pitch filler cell (PFILLER10A_G) instead of using 6 “5μm pitch”
filler cells (PFILLER5A_G).
PADxxNAU
PADxxGAU
PFILLERxA_G
Figure 9.11: The Filler-Cell Implementation
For ESD robustness, if the empty space is longer than one analog I/O cell width, we strongly
recommend to implement the dummy analog power cell (PVDD3A_V/H_G, PVDD3AC_V/H_G)
together with the PFILLERxA_G filler cells to fill the gap, where dummy means “not-bonded”, but
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used as filler cell. Figure 9.12 is an example. However, doing so would increase the stand-by leakage
current that results from the analog power cells. Please justify it based on your leakage spec.
Filler
cell
I/O
I/O
I/O
I/O
Figure 9.12: The Dummy Analog Power Cell Implementation
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The PCORNERA_G Corner Cell
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9.8.2
The N28 corner cell for analog domain is named PCORNERA_G. It is required to implement the
PCORNERA_G corner cell available from the I/O library in the analog I/O domain that spans two
sides of the chip. Furthermore, it is required to implement the bonded analog ground
(PVSS3A_V/H_G, PVSS3AC_V/H_G) right next to each side of the PCORNERA_G corner cell for
ESD robustness.
9.8.3
The PRCUTA_G Power-Cut Cell for Analog-Digital I/O Domain
Separation or Analog-Analog I/O Domain Separation
For domain separation, it is required to implement PRCUTA_G power-cut cell between two analog
I/O domains, or, between analog I/O domain and the corresponding digital I/O domain.
Similar to PRCUT_G, the PRCUTA_G power-cut cell contains no device, where all the metal bus is
cut, except that the VSS bus (the global ESD bus) stays connected through the PRCUTA_G cell.
Please refer to Figure 9.13 for illustration.
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Dummy
power
cell
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VSS
TAVDD or TACVDD
TAVDD or TACVDD
TAVSS or TACVSS
TAVSS or TACVSS
PRCUTA_G
PRCUTA_G
Analog Domain II
Figure 9.13: The PRCUTA_G Scheme & Layout
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Guard band closure
on both sides
1. For the robust cross-domain ESD & latch-up protection, it is required to implement the
analog power (PVDD3A_V/H_G, PVDD3AC_V/H_G) or analog ground
(PVSS3A_V/H_G, PVSS3AC_V/H_G) right next to the PRCUTA_G power-cut cell.
Doing so can shorten the ESD discharge path across different domains.
2. There is no limitation on the number of I/O domains separated by the PRCUTA_G or
PRCUT_G power-cut cell, as long as domains on both sides of PRCUTA_G or PRCUT_G
are implemented with I/O cells. If either side of the power-cut cell is implemented with the
3rd party IP, TSMC cannot guarantee the cross-domain ESD/latch-up performance.
9.8.4
The PENDCAPA_G Guard-Band Closure Cell
When analog I/O cells are not implemented in a ring (e.g. L shape), it is required to implement the
PENDCAPA_G guard-band-closure cell on the analog domain edge for latch-up protection. Different
from the PRCUTA_G that can close the guard bands on both sides of power-cut cell, the
PENDCAPA_G can close the guard band on one side.
In other words, it is required to mirror PENDCAPA_G horizontally to close the guard band on the
other side of the domain edge. Please refer to Figure 9.14 for illustration.
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Analog Domain I
Note
VSS
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The mirrored
PENDCAPA_G
N28 analog I/Os
PENDCAPA_G
Note
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Figure 9.14: The PENDCAPA_G Cell Implementation
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1. When using PENDCAPA_G cell, please fulfill the rules described in a separate file named
“ApplicationGuide_N28_AAIO” , which is available on tsmc online.
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2. Please make sure that the N-Well /P-Sub of the circuit layout around the PENDCAPA_G
cell is connected to power/ground solidly. It is recommended to have the connection
resistance within 1 ohm.
3. The I/O library design uses VSS as global ESD bus. Therefore, VSS bus of all the I/O
cells must be connected together for ESD robustness even if PENDCAPA_G is in use. It is
required to have VSS connection complied with the "Maximum ESD Current Density for
Via, and Metal" table in DRM.
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It is required to implement either
analog Power or analog Ground cell
right beside the PENDCAPA_G cell
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Chapter 10 The ESD & Latch-Up Considerations
for N28 Analog I/O
This chapter provides information about the following topics:

Analog I/O Placement

The Dummy Analog Power/Ground Cell Insertion

The Power/Ground Metal Bus Resistance Requirement

The 20pF Requirement

The Required Analog Power/Ground Cell Number

The ESD Clamp Macro for Analog Power-Ground Pair

The Power-Cut Cell and Guard-Band Closure Cell

How to Integrate TSMC analog I/O with the 3rd Party IP
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10.1 The ESD Network
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or
ESD Clamp
ESD Clamp
ESD Clamp
ESD clamp
ESD clamp
ESD clamp
TACVDD
LC
ESD Clamp
nf
ESD Clamp
ESD Clamp
ESD Clamp
\L
VDDPST
ESD Clamp
lI
ESD Clamp
or
ESD Clamp
VSS
ct
ESD Clamp
AVSS
AVDD
du
ESD Clamp
PCLAMPC_V/H_G
AVSS
19
ESD Clamp
20
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VSS
To Analog Macro
46
AVDD
AVSS
VDD
en
AIO
77
PCLAMP_G
/2
AVSS
on
03
PCLAMPC_V/H_G
AVDD
To Analog Macro
ic
To Analog Macro
97
m
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TSMC analog I/O, power, ground cells contain the ESD clamp circuitry to construct the ESD
protection network as illustrated in Figure 10.1 (where the I/O rail is supplied with core voltage) and
in Figure 10.2 (where the I/O rail is supplied with I/O voltage).
ESD Clamp
ESD Clamp
VSSPST
TACVSS
domain + internal analog
ground for
internal analog
analog macro
macro
VSS rail
macro
PVSS1A_V/H_G
PRCUTA_G
Core level voltage for internal
PVSS1AC_V/H_G
I/O level voltage for
PVDD1AC_V/H_G
PVSS2AC_V-H_G
Analog
PVDD1A_V/H_G
PDB3AC_V/H_G
PVSS3AC_V/H_G
Analog I/O
PVDD3AC_V/H_G
PRCUTA_G
Digital Domain
Other Analog Domain
Or Digital Domain
Core level voltage for analog
It is required to implement the secondary ESD protection device together with PDB3AC_V/H_G analog signal cell
Figure 10.1: ESD Network for Analog I/O, with analog I/O ring supplied with core voltage
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The ESD Network
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To Analog Macro
To Analog Macro
PCLAMP_G
PCLAMP_G
AVDD
To Analog Macro
AVSS
AVDD
VSS
AIO
PCLAMPC_V/H_G
AVSS
AVDD
AVSS
VDD
VSS
VSS
ESD Clamp
ESD Clamp
ESD Clamp
ESD Clamp
ESD Clamp
ESD Clamp
ESD Clamp
VDDPST
TAVDD
ESD Clamp
VSSPST
TAVSS
PVSS1AC_V/H_G
PVDD1AC_V/H_G
PVSS1A_V/H_G
PRCUTA_G
Other Analog Domain
Or Digital Domain
Analog
I/O level voltage for
Core level voltage for internal
ground for
internal analog
analog macro
Analog I/O
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ESD Clamp
ESD Clamp
PVDD1A_V/H_G
domain + internal analog
ESD clamp
ESD clamp
ESD Clamp
PVSS2A_V-H_G
I/O level voltage for analog
ESD Clamp
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PVSS3A_V/H_G
PVDD3A_V/H_G
PRCUTA_G
Digital Domain
ESD Clamp
ESD Clamp
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ESD Clamp
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ESD Clamp
VSS rail
macro
It is required to implement the secondary ESD protection device together with PDB3AC_V/H_G analog signal cell
Figure 10.2: ESD Network for Analog I/O, with analog I/O ring supplied with I/O voltage
10.2 The Global ESD Bus
TSMC I/O design is using VSS as global ESD bus.
VSS global
ESD bus
Core
I/O ring
Die edge
Figure 10.3: Global ESD Bus – VSS

To achieve robust ESD protection, it is required to have VSS pin of PVSS2A_G/PVSS2AC_G
(in analog domain) connected to VSS core ground mesh to make the VSS as chip-level
global.
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L-Shape I/O Placement
U-Shape I/O Placement
Core P/G Mesh
Core P/G Mesh
When the I/O cell placement does not form a ring (e.g. L shape), it is required to have VSS
connection from the I/O domain to the 3rd party IP nearby.

All the connections mentioned above must comply with "Maximum ESD Current Density for
Via, and Metal" table in DRM.
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
10.3 The Dummy Analog Power/Ground Cell Insertion
To achieve short ESD discharge path, it is strongly suggested to replace some of the filler cells with
the dummy analog power or ground cells if space is allowed, where dummy means “not bonded”,
simply used as the filler cells. Please refer to Figure 10.3 for illustration.
Note that the analog power/ground cells contain ESD clamp circuitry; whereas the filler cells do not.
At the package phase, dummy analog power/ground is not bonded, so that the total pin count would
not get impacted. However, the only trade-off is an increase in the stand-by leakage current of the
I/O
Filler
cell
I/O
I/O
I/O
Dummy
power
cell
dummy analog power/ground cell. Please judge it based on the total stand-by leakage spec.
Figure 10.3: Replace Filler Cells with Dummy Analog Power Cells
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Figure 10.4: I/O Implementation in L Shape / U Shape
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10.4 The ESD Analog Power / Ground Metal Bus Resistance
Requirement
Similar to the resistance calculation for digital I/Os explained in section 8.4, the ESD power/ground
metal bus resistance “R” from cell A to cell B can be calculated as illustrated in Figure 10.4.
R = Rsheet x L/W, where Rsheet is available from the spice model card.
Core
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Bus
Line
L
Cell A
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“Bonded” pad
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Figure 10.4: Illustration of Bus Resistance Calculation
Within the same analog domain, it is required to ensure that the metal bus resistance CANNOT be
greater than the value listed in the Table 10.1.
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PVDD3A/AC_V/H_G
PVSS3A/AC_V/H_G
PVSS2A/AC_V/H_G
PVSS1DGZ_V/H_G
PVDD1A/AC_V/H_G
PVSS1A/AC_V/H_G
1
3
1
1
1
3
1
1
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1
1
PVSS3A/AC_V/H_G
1
1
PVSS2A/AC_V/H_G
PVSS1DGZ_V/H_G
3
3
3
1
1
1
3
1
1
1
3
Analog I/O
PVDD3A/AC_V/H_G
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3
1
1
3
3
1
1
Note that the bus resistance between analog I/O, PVDD1A/AC_V/H_G, PVSS1A/AC_V/H_G listed
in the table above is for the case where the circuit is placed between these I/Os. There is no max. bus
resistance if there is no circuit placed between them. The measurement method shown in Figure 10.5
is required when PVSS2A_V/H_G / PVSS2AC_V/H_G / PVSS1DGZ_V/H_G is not implemented in
the same I/O domain.
Core
W
Cell B
VSS Bus Line
Line
L
“Bonded” pad
Cell A
“Bonded” pad
Figure 10.5 Measure the VSS Bus Resistance from any Analog Signal Cell to the Closest Bonded
Digital Pre-Driver Ground Supply in the Adjacent Digital I/O Domain
10.5 The 20pF Requirement
The minimal capacitive load between the “AVDD” pin on the core side of (PVDD3A_V/H_G,
PVDD3AC_V/H_G, PVDD1A_V/H_G, PVDD1AC_V/H_G) and the “AVSS” pin on the core side of
(PVSS3A_V/H_G, PVSS3AC_V/H_G, PVSS1A_V/H_G, PVSS1AC_V/H_G) is 20pF.
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Analog I/O
Table 10.1: The max resistance between different I/O types
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AVDD
AVSS
AVDD
>20pF
AVSS
AVDD
>20pF
AIO
AVSS
>20pF
VDD
VSS
VSS
ESD Clamp
ESD Clamp
ESD Clamp
ESD Clamp
ESD Clamp
ESD Clamp
ESD Clamp
VDDPST
TACVDD
ESD Clamp
ESD Clamp
ESD Clamp
TACVSS
PVSS2AC_V-H_G
PVSS1AC_V/H_G
PVDD1AC_V/H_G
PVSS1A_V/H_G
PVDD1A_V/H_G
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PVSS3AC_V/H_G
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PRCUTA_G
PRCUTA_G
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ESD clamp
ESD clamp
ESD Clamp
VSSPST
ESD Clamp
ESD Clamp
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If insufficient, it is required to insert the decoupling capacitor. Please refer to Figure 10.6 for
illustration.
Figure 10.6: The 20pF Requirement
10.6 The Required Analog Power / Ground Cell Number
To achieve robust ESD/latch-up protection, it is required to implement:
For I/O-voltage analog domain:

PVDD3A_V/H_G analog power cell with I/O voltage: “at least” 2 bonded analog power to
supply TAVDD analog power bus. The total number of the bonded PVDD3A_V/H_G must
also meet the TAVDD bus resistance requirement.

PVDD1A_V/H_G dedicated analog power cell with I/O voltage: If in use, “at least” 2
bonded PVDD1A_V/H_G dedicated analog power cells connected to the same package pin.

PVSS3A_V/H_G analog ground cell: “at least” 1 bonded analog ground cell to supply
TAVSS analog ground bus. The total number of the bonded PVSS3A_V/H_G must also meet
the TAVSS bus resistance requirement.

PVSS2A_V/H_G global ESD ground bus supply: this cell is needed in case the VSS bus
resistance requirement cannot be fulfilled by the digital PVSS1DGZ_V/H_G. The
PVSS2A_V/H_G / PVSS1DGZ_V/H_G must meet the VSS bus resistance requirement.
For core-voltage analog domain:

PVDD3AC_V/H_G analog power cell with core voltage: “at least” 3 bonded analog power
to supply TACVDD analog power bus. The total number of the bonded PVDD3AC_V/H_G
must meet the TACVDD bus resistance requirement.

PVDD1AC_V/H_G dedicated analog power cell with core voltage: If in use, “at least” 3
bonded PVDD1AC_V/H_G dedicated analog power cells connected to the same package pin.

PVSS3AC_V/H_G analog ground cell: “at least” 1 bonded analog ground cell to supply
TACVSS analog ground bus. The total number of the bonded PVSS3AC_V/H_G must meet
the TACVSS bus resistance requirement.
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
PVSS2AC_V/H_G global ESD ground bus supply: this I/O is needed in case thethe VSS
bus resistance requirement cannot be fullfilled by the digital PVSS1DGZ_V/H_G. The
PVSS2AC_V/H_G / PVSS1DGZ_V/H_G must meet the VSS bus resistance requirement.
10.7 The ESD Clamp Macro
10.7.1 PCLAMPC_V/H_G ESD Core-Clamp Macro

10.7.2 PCLAMP_G ESD I/O-Clamp Macro

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When to use it: While using PVDD3A_V/H_G (I/O-voltage analog power) and
PVSS3A_V/H_G (the corresponding analog ground cell), or when using PVDD1A_V/H_G
(dedicated I/O-voltage analog power) and PVSS1A_V/H_G (the corresponding dedicated
analog ground cell), it is required to use at least one PCLAMP_G ESD clamp macro along
with the I/O voltage analog power-ground pair.
10.7.3 Implement PCLAMPC_V/H_G, PCLAMP_G ESD Clamp Macro
on the Core Side
The implementation is identical to the implementation with digital PVDD1ANA_V/H_G /
PVSS1ANA_V/H_G for PCLAMPC_V/H_G; identical to PVDD2ANA_V/H_G /
PVSS2ANA_V/H_G for PCLAMP. Please refer to section 8.7 for details.
10.8 The PRCUTA_G Power-Cut Cell for Analog-Analog or
Analog-Digital Domain Separation
It is required to implement the PRCUTA_G power-cut cell between two analog I/O domains, or
between the analog I/O domain and the corresponding digital I/O domain. Please refer to Section
9.8.2 for details.
10.9 The PCORNERA_G Corner Cell
It is required to implement the bonded ground cell (PVSS3A_V/H_G / PVSS3AC_V/H_G) right next
to each side of the PCORNERA_G corner cell for ESD robustness. Please refer to Section 9.8.3 for
details.
10.10 The PENDCAPA_G Guard-Band Closure Cell
The PENDCAPA_G guard-band-closure cell implementation is to close the guard band on the domain
edge. Different from the PRCUTA_G power-cut cell that can close the guard bands on both sides of
the power-cut cell, the PENDCAPA_G can close the guard band on one side. Please refer to Section
9.8.4 for details.
10.11 How to Integrate TSMC I/O with Other IP
VSS is the global ESD bus for TSMC I/O. To integrate TSMC I/O with other IP, it is required to
comply with the following rules.
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When to use it: While using PVDD3AC_V/H_G (core-voltage analog power) and
PVSS3AC_V/H_G (the corresponding analog ground cell), or when using PVDD1AC_V/H_G
(dedicated core-voltage analog power) and PVSS1AC_V/H_G (the corresponding dedicated
analog ground cell), it is required to use at least one PCLAMPC_V/H_G ESD core-clamp
macro along with the core voltage analog power-ground pair.
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Note
1. TSMC cannot guarantee the ESD & latch-up if the TSMC I/O is mixed with other IP in a
common domain.
2. It is required to implement the PENDCAPA_G guard-band closure cell between the
analog I/O domain edge and other IP. Furthermore, it is required to comply with the
application requirements stated in Section 9.8.4 for PENDCAPA_G placement.
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4. It is required to connect the global ESD bus of other IP to the VSS bus of TSMC I/O (e.g.
through mesh, or direct metal connection). The VSS connection must comply with the
"Maximum ESD Current Density for Via, and Metal" table in DRM.
5. Other IP design & implementation must comply with TSMC ESD rules/guidelines.
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Figure 10.7: Illustration of the 135-degree Metal Connection
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3. As to the power/ground metal connection at the domain interface, it is necessary to avoid
the 90-degree metal bus connection. For ESD robustness, please adopt the 135-degree
metal connection as illustrated in Figure 10.7.
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Chapter 11 The Bond Pad for N28 I/O
The bond pads compatible with N28 I/O cells are available from the tpbn28v library.
This chapter covers the following topics:
The Bond Pad Library

The Naming Convention for the CUP Bond Pad and Flip Chip Bumps

The Library Hierarchy

The Bond Pad Type
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11.1 The Bond Pad Library
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The I/O cell is designed to support either CUP wire bond or RDL flip chip in consideration of area
saving, where the CUP bond pads for I/O and the flip chip bumps are available from the bond pad
library.
The TSMC N28 bond pad library naming follows the conventions below:
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[Category] –[geometry] – [layout style]
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Category: TPB - bond pad library provides wire-bond pads and flip chip bumps.
Geometry: N28 - TSMC N28 process.
Layout style: V - combo layout style.
As an example, TPBN28V can be decomposed as TPB-N28-V, which indicates TSMC bond pad
library, in 28nm process with combo layout style.
11.2 The Naming Convention for the Bond Pad
The naming convention for bond pad:
PAD-[Pitch] - [Category]
PAD: indicates bond pad or flip chip bump
Pitch: x μm pitch for bond pad or x μm UBM width for bump
Category:

GU: staggered outer CUP wire-bond pads for digital I/O (Note that “outer” vs. “inner” is with
respect to core.)

NU: staggered inner CUP wire-bond pads for digital I/O

APB: flip chip bump for AP RDL

MTB: flip chip bump for RDL with top metal
For examples,

The PAD60GU is the staggered outer CUP pad (with 60um staggered pitch) for the I/O.

The PAD60NU is the staggered inner CUP pad (with 60um staggered pitch) for the I/O.

The PAD80APB is the bump cell with 80um x 80um UBM dimension for the AP RDL
application.
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
The PAD80MTB is the bump cell with 80um x 80um UBM dimension for the MT RDL
application.
11.3 The Library Hierarchy
The N28 bond pad library design kits have two directories, namely “cup” for CUP wire bond, “fc” for
flip-chip bump.
fc directory
MTRDL/Metal Scheme/
PADxAPB
PADxMTB
Figure 11.1 The Back-End Hierarchy of the Bond Pad Library
11.4 CUP Bond Pad Type
It is required to insert the appropriate number of filler cell if the target pad pitch is bigger than the I/O
pitch. It should also be noted that, depending on the pitch, the CUP bonding pad could extend over the
I/O edge (towards chip edge) as well as the core region, therefore blocking some metal layers for
place and route, it is necessary to first place the CUP bonding pads prior to P&R. Please refer to the
I/O library release note for information.
11.4.1 The Staggered CUP Pads for I/O
The I/O library name contains “GV” characters (e.g. tphn28hpmgv18), and the corresponding
staggered CUP pads are PADxNU and PADxGU, where PADxNU is the staggered inner pad, and
PADxGU is the staggered outer pad. The “inner” and “outer” are with respect to core as illustrated in
Figure 11.2
To connect the CUP pad to I/O cell, it is required to instance the I/O and the corresponding bond pad
at the same coordinates.
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APRDL
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(Library Name: tpbn28v
PADxNU
PADxGU
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The Bond Pad
Library
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cup directory
Metal Scheme
e.g. 9m/9M_6X2Z
…
…
…
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PAD60NU
Figure 11.2 The PADxGU and PADxNU Staggered CUP Pads
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1. For CUP wire-bond, after the CUP pad is implemented on top of the I/O cell, the CUP pad
would extend toward CORE and die edge, respectively.
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PAD60GU
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Chapter 12 Applications
This chapter covers the following topics:
The Back-End Kit Directory

CUP Wire Bond

RDL Flip Chip

Double I/O Rings

AAIO (Area Array I/O) Application
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12.1 The Back-End Kit Directory
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The I/O library design kit has “.tar.gz” file name extension (e.g. tphn28hpgv18_100a_gdsu6lm.tar.gz).
After un-zip followed by un-tar, the following back-end directory would be generated:
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/TSMCHOME/digital/Back_End/ design-kit type (e.g. gds) /libraryname_designkit version (e.g.
tphn28hpgv18_100a) /mt_2 /metal layer number (e.g. 9lm) / design kit (the target file)
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Where mt_2 indicates that this particular design kit contains metals up to two metal layers below the
target top metal. For instance, the gds under /mt_2/9lm/ directory contains metal layers up to metal 7,
which is 2 metal layers below the target 9 metal layer tape-out.
Table 12.1 lists the name of the back-end directory, where you can find the back-end design kit for
CUP wire bond or RDL flip-chip application.
Table 12.1: The Back-End Kit Directory
Application
CUP Wire Bond
RDL Flip Chip
I/O Back-End Kit
mt_2
mt_2
Bond Pad Back-End Kit
Cup
Fc
Note:
Please do not use Apollo frame view (apf design kit) to stream out the gds.
12.2 CUP (Circuit under Pad) Wire Bond
CUP stands for Circuit under Pad, which means, the bond pad is placed on top of the I/O cell,
commonly known as the CUP wire-bond application.
The CUP pad pin of the staggered I/O is located close to the center of the I/O cell. To connect the
CUP pad to the I/O cell, it is required to instance the I/O and the corresponding bond pad at the same
coordinates.
Note
1. It is necessary to place the CUP bonding pads on top of the I/O prior to running P&R.
2. To achieve the desired metal scheme, it is required to correctly select the design kit from
the applicable back-end directory, by referring to the back-end-directory table in the bond
pad library release note for various metal scheme options.
For Example: To tape out 1P6M (6 metal layers) with 4X1Z metal scheme, it is necessary to read the
bond pad library release note, where there is table that shows how to realize 6M_4X1Z metal scheme
by adopting the design kit from the applicable back-end directory. Please refer to
Figure 12.1 for example.
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In this example, 1P6M with 4X1Z metal scheme can be achieved as follows:
I/O: Adopt gds under “mt_2/6lm” directory.

CUP pad: Adopt gds under “cup/6m/6M_4X1Z” directory.
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
Metal 4
VIA 3
Metal 3
VIA 2
Metal 2
VIA 1
Metal 1
Metals from I/O body
Metal 6
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VIA 5
Metal 6
64
VIA 5
Metal 5
4VIA 4
Metal 5
4VIA 4
Metal 4
VIA 3
Metal 3
VIA 2
Metal 2
VIA 1
Metal 1
Metals
from
CUP
bonding
pad
Combination of metals
from I/O body and
CUP bonding pad
Figure 12.2: Illustration for I/O & CUP Pad Combination
12.3 RDL (Re-Distribution Layer) Flip Chip
Flip Chip, the direct electrical connection of face-down (hence "flipped") electronic components onto
the substrate, features the following benefits:

Reduce the required board area.

Reduce the inductance and capacitance of inter-connections, improving the accuracy of
impedance control.

Provide effective heat dissipation using bumps.
N28 I/O can support APRDL / MTRDL. Please refer to the bond pad library release note for details.
For Example: To tape out 1P6M (6 metal layers) with 4X1Z metal scheme using MTRDL, it is
necessary to read the bond pad library release note, where there is table that shows how to realize
6M_4X1Z metal scheme by adopting the design kit from the applicable back-end directory:
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Figure 12.1: The Back-End Directory Combination for Various Metal Schemes (snapshot from
tpbn28v release note)
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As indicated in
Figure 12.1, 1P6M with 4X1Z metal scheme can be realized as follows:

I/O: Adopt gds under “mt_2/6lm” directory, where gds contains metals up to metal 4.

APRDL Flip-Chip Bump: Adopt gds under “fc/MTRDL/6m/6M_Z” directory.
Note
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2. It is required to implement the ESD clamp macro (PCLAMP_G, PCLAMPC_V/H_G)
between the power and ground mesh.
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12.3.1 PCLAMP_G/PCLAMPC_V/H_G usage as ESD clamp cell for RDL
flip chip
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RDL flip chip relies on power/ground mesh to supply the core and the I/O ring. In this case, the ESD
clamp protections embedded in the PVDD1DGZ_V/H_G and PVDD2DGZ_V/H_G are far from the
bump, which results in degrading the ESD protection on the core region because of the mesh metal
resistance. Therefore, it is mandatory to implement PCLAMP_G and PCLAMPC_V/H_G ESD
clamp macro by following the below requirements to ensure effective ESD protection:

It is required to implement at least 2 ESD clamp macro (PCLAMPC_V/H_G for core power;
PCLAMP_G for I/O power) within a single power domain between power and ground mesh.

The max resistance from core power bump (VDD) or I/O power bump (VDDPST) to a clamp
cell (PCLAMPC_V/H_G or PCLAMP_G, respectively) is 0.1 Ohm, and the max resistance
from core ground bump (VSS) or I/O ground bump (VSSPST) to a clamp cell is also 0.1 Ohm,
as illustrated in Figure 12.3.

The metal rails connecting from VDD and VSS bumps to the (PCLAMPC_V/H_G or
PCLAMP_G) must satisfy the design rule for the total width of metal lines connected from the
bond pad / bump to ESD device (PCLAMPC_V/H_G or PCLAMP_G).
< 0.1 Ohm
< 0.1 Ohm
Figure 12.3: Illustration of PCLAMPx implementation for RDL flip chip
12.4 Double I/O Rings
The double I/O ring can be used for the high-pin-count application. It is a must to comply with the
following requirements for implementation.
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1. It is required to read the bond pad library release note for information on the required tapeout layer, the special usage note, which directory to access for various metal scheme
options, etc.
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CORE
I/O
Inner I/O Ring
Corner
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Figure 12.4: Illustration for the Double I/O Rings
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Note
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1. In consideration of signal integrity, the following steps can be helpful to the place & route.
a. Route the I/O signal first.
b. Insert the routing blockage layer in the top two metals. (By default, routing is not
blocked in the top two metals.)
c. Finally, route the internal signal afterwards.
2. For the double I/O rings with RDL, at least one layer should be reserved for routing from
the outer I/O ring to core. Please refer to Figure 12.5 for illustration.
3. For latch-up prevention, please treat the inner ring as AAIO placement and follow the rules
described in a separate file named “ApplicationGuide_N28_AAIO” which is available on
TSMC online.
4. Do not flip the I/O cells in the inner ring. That is, the core side of the I/O cells in the outer
ring should face the pad side of the I/O cells in the inner ring (i.e. the head-to-tail style). In
this case, the corner cell at the outer corner should have the same orientation as the one at
the inner corner.
5. A power domain is the region where there are the dedicated power & ground supply. Since
the I/O domain in the inner ring is considered a different power domain from that in the
outer ring, it is required to implement the correct power/ground cells in each inner I/O
domain. Furthermore, in case a domain is on both outer and inner rings, it is required to
connect from the power/ground cells of the inner I/O ring to those of the outer, and each
connection must comply with the “Maximum ESD Current Density for Via, and Metal"
table in DRM. Please refer to Figure 12.6 for illustration.
6. It is required to implement “one and only one” PVDD2POC_V/H_G / PVDD2POC in each
digital I/O domain of the inner and the outer ring. Though the power/ground cells of inner
and outer I/O rings are connected as instructed in Note 5, the POC rail remains
disconnected.
7. It is required to implement the power-cut cell (PRCUT_G, PRCUTA_G) between different
power domains. On the other hand, if I/O domains cannot form a ring, it is required to
implement the (PENDCAP_G / PENDCAPA_G) cell at each domain edge to close up the
guard ring. Also, it is mandatory to follow the associated requirements stated in Sections
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Outer I/O Ring
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6.4 and 8.10. Please refer to Figure 12.6 and Figure 12.7 for illustration.
Core
Inner I/O
Figure 12.5: Illustration of RDL to Core with Double I/O Rings
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CORE
Inner I/O Ring
Outer I/O Ring
Power/Ground Cell
Corner
I/O Cell
Power-Cut Cell
Figure 12.6: Illustration of the Power/Ground Cell Connection between the Inner and the Outer
I/O Ring
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Outer I/O
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Note: Since the inner domain A
and B are disconnected in the
inner I/O region, it is required to
ensure that the VSS bus of these
2 domains is connected and the
connection must comply with the
“Maximum ESD Current Density
for Via, and Metal" table in DRM.
CORE
A
B
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Outer I/O Ring
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Power/Ground Cell
I/O Cell
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Figure 12.7: Illustration of the PENDCAP Cell Implementation
12.5 AAIO (Area Array I/O) Application
Our N28 I/O libraries are designed for peripheral I/O placement which means that all I/O cells are
placed on the chip edge and no other circuit layout outside the I/O ring. In case customers need AAIO
placement, which means that there is other circuit layout surrounding the I/O cells, e.g. Figure 12.8,
please fulfill all the rules described in a separate document named “ApplicationGuide_N28_AAIO”,
which is available on TSMC online, for details.
Chip edge
peripheral I/O
placement
AAIO
placement
PENDCAP*
Other circuit layout
Figure 12.8: Illustration of AAIO Placement
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Chapter 13 Electromigration (EM) Consideration
This chapter provides information on the following topics:

EM Capacity of the Power/Ground Cell

EM Capacity of the Bond Pad

EM Capacity Enhancement
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TSMC N28 I/O library contains several sets of power/ground cells to supply current to the core and
the I/O.
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13.1.1 Determine the Maximum Allowable Current
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To determine the maximum allowable current that each power/ground cell can supply, it is required to
refer to the layout as well as to the maximum DC current density (Jmax) and temperature derating
factor tables of the TSMC design rule manual. Then, multiply the most critical metal width by Jmax
and the temperature rating factor to come up with the maximum EM value. Please refer to the I/O
library release note for the calculated EM values.
Note that the EM bottleneck might lie in the metal routing between TSMC power/ground cell and the
internal macro (e.g. narrow metal width, insufficient via number, etc.) Please pay attention to the
inter-connection between the power/ground cell and the internal core.
13.1.2 Determine the Required Number of Power/ Ground Cells
The EM table that lists the maximum allowable current for each power/ground cell can be found in
the library release note, which can be used for calculating the required number of power/ground cell
to supply sufficient current based on the estimated power consumption. Specifically to determine the
required number of digital I/O power/ground cells, it is required to consider the Simultaneously
Switching Outputs (SSO) effect. Please refer to the Chapter 7 for details.
13.1.3 Locate the EM Critical Point
EM is a reliability factor in chip manufacturing. EM may not cause chip failure immediately upon
power up, but could degrade the performance over time. To locate a possible EM weak point, the
EDA tool analysis of the current distribution and EM criterion is strongly recommended. Nevertheless,
performing a layout review focused on the connecting ports to power/ground cells is needed,
particularly for via number and metal width. Adding via arrays or stacked metal can help to increase
the maximum allowable current.
13.1.4 EM vs. Temperature
The magnitude of EM capacity would vary with temperature. For example, EM at 110°C is greater
than that at 125°C. Attention to the temperature associated with your EM criteria is needed. To
convert EM from one temperature to another, it is required to multiply it by the DC rating factor
available from the Design Rule Manual.
13.2 EM Capacity of the Bond Pad
As long as TSMC I/O is connected to the corresponding TSMC bond pad, the EM bottleneck would
lie in the I/O rather than the bond pad. Therefore, the bond pad EM capacity is not given in the bond
pad library release note.
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13.1 EM Capacity of the Power/Ground Cell
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13.3 EM Capacity Enhancement
13.3.1 Double/Triple Bonds
When the package pin count is limited, double or triple bonds to the same package power or ground
pin is recommended for EM enhancement.
Figure 13.1 shows an example of double bonds with the core power & ground supply. With this
method, the EM capacity can be significantly increased. The ESD performance can also benefit from
the reduced bond wire inductance resulting from the double/triple bonds.
Single bond on core power/ground cells
Double bonds on core power/ground cells
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Die Edge
VDD
VSS
Package
Pins
VDD
VSS
Figure 13.1: Double Bonds with the Core Power & Ground Supply
13.3.2 Connect Top Two Metal Lines from the CUP Pad to Core
TSMC N28 General I/O Library Application Note
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Option 1: Simply connect top two metal lines from the core CUP pad (PADxNU_SL) as illustrated in
Direct connection with the power/gnd mesh
To core region
VIA array between
CUP pad and the
power mesh.
e\
To core region
Direct connection with the power/gnd mesh
VIA array between
CUP pad and the
power mesh.
Figure 13.2: EM Enhancement by Top Two Metal Connections (Option 1)
Option 2: To connect the top 2 metal lines from the staggered outer CUP pad to core, it would be
needed to insert filler cells to enlarge the space in between. Please refer to Figure 13.3 for illustration.
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Figure 13.2. It is also possible to make a direct connection between the CUP bonding pad extending
over the core region and the power/gnd mesh
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Insert filler cells on both sides of
the power/ground cell & connect
the top 2 metal lines from the
CUP outer pad to core for EM
enhancement
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Option 3: To connect the top 2 metal lines from the staggered outer CUP pad to core, instead of
inserting filler cells as mentioned in Option 2, simply implement another identical Power or Ground
cell beside to enlarge the space in between.
e\
Then, modify the CUP pad pin of two identical Power or Ground cells, to which you can implement
the CUP pad in the middle of two cells.
Finally, connect the top two metal lines from the CUP pad to core for EM enhancement. Please refer
Place two identical Power or
Ground cells together, modify
the CUP pad pin to which CUP
pad can be connected in the
middle; connect the top 2 metal
lines from the CUP pad to core
for EM enhancement
to
Figure 13.4 for illustration.
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Figure 13.3: EM Enhancement by Top Two Metal Connections (Option 2)
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Place two identical Power or
Ground cells together, modify
the CUP pad pin to which CUP
pad can be connected in the
middle; connect the top 2 metal
lines from the CUP pad to core
for EM enhancement
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Compared with Option 2, Option 3 is preferable in terms of ESD robustness, since the ESD clamp
circuitry is embedded within the power/ground cell. As a result, placing two identical power or
ground cells together is more robust than the filler-cell insertion.
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Figure 13.4: EM Enhancement by Top Two Metal Connections (Option 3)
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Chapter 14 Library Integration Notes
To correctly tape out TSMC I/O cells, it is required to closely follow the TSMC masking layers and
bias documents described in the “tape-out layer information” of the library release note; and refer to
this chapter for general tape-out information.
14.1 GDSII Number Mapping
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Warning: The mixed or incorrect mapping of GDSII layers would result in serious mask issue
and silicon failure.
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14.2 ESD Mask
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The ESD implant layer is required for N28 I/O library. Please make sure all the ESD-related GDSII
layers are taped out correctly according to the “Masking Layers & Bias” table as well as to the library
release note for the required tape-out layers together with special note on the ESD mask generation, if
any.
14.3 GDSII Change to Mask Revision
A minor change in the GDSII layer might lead to a significant change in mask set. For example,
modification of the OD2 GDSII layer not only changes the OD2 mask but also other masks, such as
PW1V, PW2V, NW1V, NW2V, PO, N2V, and so forth. It is required to review the “Masking Layers
& Bias” document beforehand.
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For libraries from different vendors, the GDSII numbers defined for each process node and dummy
layers might be different. Therefore, it is required to comply with the definition in the technologydependent “GDS Layer Usage Description File” that can be downloaded from TSMC Online.
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Chapter 15 Simulation Notes
15.1 LPE Netlist
As both parasitic interconnect resistance and capacitance have an impact on electrical performance,
the N28 I/O library layout is extracted with both R and C. Moreover, three lpe netlists are provided
within the lpe kit.
Table 15.1: LPE netlist name and RC command file
RC command file
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{library name}_{version number}_lpe.spi
Typical
{library name}_{version number}_lpe_best.spi
Cbest
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{library name}_{version number}_lpe_worst.spi
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15.2 Characterization Conditions
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The characterization conditions of TSMC N28 I/O libraries in different PVT (Process Voltage
Temperature) combinations are listed below. The condition coverage would vary.
Table 15.2: Corner definition and PVT conditions
Description
Low Temp
Best Case
Typical Case
Worst Case
Worst Case Low Temp.
Worst Case Zero Degree
Maximum Leakage
Global Maximum Leakage
LPE Netlist
Core
Voltage
I/O
Voltage
Temp
Process
_lpe_best.spi
1.1*Vdd
1.1*Vddpst
-40
FF
_lpe_best.spi
1.1*Vdd
1.1*Vddpst
0
FF
_lpe.spi
1.0*Vdd
1.0*Vddpst
25
TT
_lpe_worst.spi
0.9*Vdd
0.9*Vddpst
125
SS
_lpe_worst.spi
0.9*Vdd
0.9*Vddpst
-40
SS
_lpe_worst.spi
0.9*Vdd
0.9*Vddpst
0
SS
_lpe_best.spi
1.1*Vdd
1.1*Vddpst
125
FF
_lpe_best.spi
1.1*Vdd
1.1*Vddpst
125
FFG
The characterization corner is named according to the following naming convention:
[Process corner][core voltage]v[I/O voltage]v[Temperature]c
Where:
Process corner: defines which spice corner is used for characterization
Core voltage: defines the Vdd core voltage
I/O voltage: defines the Vddpst I/O voltage
Temperature: Defines the temperature
For examples:
tt0p81v1p8v25c corresponds to characterization with TT process, 0.81 V Vdd voltage, 1.8 V Vddpst
voltage, and 25 °C.
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LPE netlist name
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ff1v1p98vm40c corresponds to characterization with FF process, 1 V Vdd voltage, 1.98 V Vddpst
voltage, and -40 °C.
Note
1. PVT (Process Voltage Temperature) characterization corners are available in the library
release note. Note that TSMC in-house N28 I/O library is designed to operate within the
offered PVT conditions. If your design is beyond the given PVT conditions, it is required
to contact TSMC.
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15.3 Power / Ground Pin Information
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In both digital and analog I/Os, power, ground and POC pin appear at the subcircuit definition,
allowing user to use the I/Os in voltage islands. They follow certain naming conventions.
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Here is the list of power/ground/POC pins that appear in the digital I/O subcircuit definition:
VDD: core voltage (supplied by PVDD1DGZ_V/H_G)

VDDPST: I/O voltage (supplied by PVDD2DGZ_V/H_G)

VSSPST: post driver ground voltage (supplied by PVSS2DGZ_V/H_G)

VSS: pre-driver and core region voltage (supplied by either PVSS1DGZ_V/H_G or
PVSS3DGZ_V/H_G)

POC: POC signal (supplied by PVDD2POC_V/H_G)
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
Resulting in a subcircuit definition as follows (example):
.SUBCKT PRDW04DGZ_H_G C PAD I OEN REN VDD VDDPST VSS VSSPST POC
For analog I/Os, the convention differs, depending on whether the analog I/O is to be placed in a core
voltage domain or an I/O voltage domain.
For the analog I/Os that will be placed in a core voltage domain, the convention is:

TACVDD: analog core voltage (supplied by PVDD3AC_V/H_G)

TACVSS: analog core ground (supplied by PVSS3AC_V/H_G)

VSS: digital core ground (supplied by either: PVSS2AC_V/H_G or PVSS1DGZ_V/H_G or
PVSS3DGZ_V/H_G)
Resulting in a subcircuit definition as follows (example):
.SUBCKT PDB3AC_H_G AIO TACVDD TACVSS VSS
For the analog I/Os that will be placed in an I/O voltage domain, the convention is:

TAVDD: analog core voltage (supplied by PVDD3A_V/H_G)

TAVSS: analog core ground (supplied by PVSS3A_V/H_G)

VSS: digital core ground (supplied by either: PVSS2A_V/H_G or PVSS1DGZ_V/H_G or
PVSS3DGZ_V/H_G)
Resulting in a subcircuit definition as follows (example):
.SUBCKT PDB3A_V_G AIO TAVDD TAVSS VSS
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2. For re-characterization or customization request that requires modification on off-the-shelf
I/O, unless specifically requested in Statement of Work (SOW) form, it would still be
based on the characterization conditions of the original library.
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Note that for simplification, this document always uses the above conventions. For example,
VDDPST is the digital I/O voltage.
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Chapter 16 Layout Considerations
TSMC N28 design rule manual defines a unique vertical poly orientation. As TSMC I/Os can be
placed in a ring, it is necessary to provide two sets of cells: one that can be placed vertically, that is at
the bottom and top of the I/O ring, and another one that can be placed horizontally, at the left and
right sides. For this, each function I/O cell comes with two different layout styles:
{cell_name}_V_G: the I/O is to be used as-is in vertical direction, at the bottom and top sides
of the chip

{cell_name}_H_G: the I/O needs to be rotated and placed horizontally at the left and right
sides of the chip.
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Since only the core oxide needs to follow this poly orientation, some cells are not offered with _V_G
or _H_G extension. This is the case for example for the I/O voltage ESD clamp (PCLAMP_G). Also,
cells that do not contain any device come with one type only, for example filler and corner cells. User
needs to refer to the library release note for more information.
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Both sets of cells (_V_G and _H_G) are fully modeled in terms of design kits. Behavioral models are
identical, while minor difference in terms of timing/power can be expected. User can refer to the nldm
design kit.
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It should be noted that the library contains all cells placed vertically. In this case when running a DRC
at cell level the _H_V cells would return the poly orientation violation. However when correctly
placed in a ring the violation would not be reported. On the other hand rotating a _V_G cell and
placing it at the left and right sides of a chip would be caught when running DRC.
Core transistors
in the correct
orientation
Core
transistors
rotated
Thick
transistors
Thick
transistors
Digital I/O with vertical
layout style
Digital I/O with horizontal
layout style
Figure 16.1: Layout snapshot of the I/O predriver for the same I/O. The I/O with horizontal
layout style requires rotation so that all core devices follow single poly orientation
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
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Chapter 17 The Absolute Maximum Rating
Note: Long-term exposure to absolute maximum ratings may affect device reliability, and
permanent damage may occur if the operation exceeds the maximum ratings listed in Table 17.1:.
The I/O should be operated under the recommended operating conditions specified in the library
databook.
Table 17.1: Absolute Maximum Ratings
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Parameter
Value
Power Supply Voltage
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Input Voltage, VI
Please check TSMC Online
Please check TSMC Online
Please check TSMC Online
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Output Voltage, VO
-40C ~ +125C
Operation Temperature, TOPT
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The maximum voltage levels in the table below should be determined by using the e-Reliability
Model System > Overall Reliability Assessment from TSMC-Online by entering the required input
and product lifetime conditions.
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Chapter 18 N28 I/O Usage Checklist
To ensure the I/O usage correctness, it is necessary to go through the checklist below based on your
chip implementation.
18.1 Review Checklist
Remark
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2. For legibility, the cell names do not come with the _V/H_G extension. For example, PVDD2POC
refers to PVDD2POC_V/H_G.
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3. Terms:
3.1. bonded: connected to bond pad/package
3.2. bumped: connected to flip-chip bump/package
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4. For the item with serial number that contains “y” letter (e.g. 15y.1), it is categorized as the subitem that needs to be checked if the mother question is applicable to your application (e.g. 15).
For example, if you answer a “yes” for item 15, you also need to answer the sub-questions (15y.1,
15y.2) related to the question 15.
Official Check Items
Serial
No.
check item
General Check
criteria/spec or
check method
1
All of the above libraries used in the chip are the most updated version?
(Note: To determine whether the library version is the most up-to-date,
please log onto TSMC Online Design Portal 2.0, or check with TSMC
Field Application Engineer for information.)
yes
2
Is customer's target process node the same as what these libraries are
designed for (e.g. not porting N28HP tphn28hpgv18 I/O to N28HPL
process node)?
yes
3
Have you read the N28 I/O General Application Note to understand the
general usage requirement?
yes
4
Have you read the associated I/O & bond pad library release note(s) to
understand the specific library usage requirement?
yes
5
Do the required tape out layers listed in library release note exist in the
tape-out GDS?
yes
6
Do the required tape out layers listed in library release note will be / have
been specified in tape-out MT form?
yes
Digital Domain Usage Requirement (If digital cells are implemented)
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1. Please ensure that you have read N28 I/O General Application Note as well as the associated
library release note(s), understanding the usage constraints prior to filling out this checklist.
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yes
8
Are there at least three PVDD1DGZ cells connected to package in each
digital I/O domain?
yes
9
Are there at least two PVDD2DGZ cells connected to package in each
digital I/O domain? (one of them can be PVDD2POC)
yes
10
Is there at least one PVSS1DGZ or PVSS3DGZ cell connected to package
in each digital I/O domain?
yes
11
Is there at least one PVSS2DGZ or PVSS3DGZ cell connected to package
in each digital I/O domain?
yes
12
Is the PVDD1DGZ used as a "core-voltage" power supply?
yes
13
From the metal bus resistance point of view, does the cell placement follow
the Table 8.1 of the TSMC N28 I/O General Application Note?
14
Is the bonded ground cell PVSS2DGZ (or PVSS3DGZ) implemented next
to "both side" of the PCORNER corner cell?
15
Is this chip flip-chip application?
yes or NA
15y.1
Is the metal bus resistance from the power / ground bump to the
PCLAMPC ESD clamp macro cell less than 0.1 ohm?
yes
15y.2
Is the metal bus resistance from the power / ground bump to the PCLAMP
ESD clamp macro cell less than 0.1 ohm?
yes
16
Is any PVDD1ANA implemented?
yes or NA
16y.1
Is the PVDD1ANA used as the core-voltage analog power supply?
yes
16y.2
Are there at least three PVDD1ANA cells connected to the same package
pin?
yes
16y.3
Is PCLAMPC implemented with PVDD1ANA?
yes
16y.4
Is the capacitive load between the AVDD pin (on the core side of
PVDD1ANA) and ground pin greater than or equal to 20pF?
yes
17
Is any PVDD2ANA implemented as a power supply cell?
yes or NA
17y.1
Is the PVDD2ANA connected to IO transistor, not core transistor?
yes
17y.2
Is PCLAMP implemented with PVDD2ANA?
yes
17y.3
Is PVDD2ANA powered up after the digital PVDD2DGZ power cell is on?
yes
17y.4
Is the capacitive load between the AVDD pin (on the core side of
PVDD2ANA) and ground pin greater than or equal to 20pF?
yes
18
Is any PVDD2ANA implemented as an analog signal?
yes or NA
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Is there “one and only one” PVDD2POC cell in each digital I/O domain?
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yes
yes
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yes
18y.2
Is the connection between PVDD2ANA and internal analog macro
adequately made based on the N28 I/O application note (e.g. implement the
secondary ESD protection device, etc.)?
yes
18y.3
Is the maximum signal swing of PVDD2ANA cell lower than or equal to
the nominal VDDPST + 0.3V?
yes
18y.4
Is the minimum signal swing of PVDD2ANA cell higher than or equal to 0.3V?
yes
19
By taking the worst SSO scenario into account [i.e. use the SSO DF
(Driving Factor) given in the library databook & assume every bidirectional I/O to be used as output drivers], is the number of
“bonded/bumped” PVDD2DGZ enough to avoid the SSO noise effect?
yes
20
By taking the worst SSO scenario into account [i.e. use the SSO DF
(Driving Factor) given in the library databook & assume every bidirectional I/O to be used as output drivers], is the number of
“bonded/bumped” PVSS2DGZ or PVSS3DGZ enough to avoid the SSO
noise effect?
yes
21
Is the ramp-up time for digital power up of
PVDD1ANA/PVDD1DGZPVDD2DGZ, respectively, longer than 10us?
yes
22
If the empty gap space between two digital cells is larger than one cell
width, is dummy digital power cell implemented prior to filler cells?
(where “dummy” means “not-bonded”)
yes
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Is the PVDD2ANA connected to IO transistor, not core transistor?
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18y.1
Analog Domain Usage Requirement (If analog cells are implemented)
23
Is PDB3AC implemented?
yes or NA
23y.1
Is PDB3AC connected to core transistor, not IO transistor?
yes
23y.2
Is PDB3AC analog signal cell implemented with PVDD3AC analog power
and PVSS3AC analog ground in the core-voltage analog domain?
yes
23y.3
Is the VSS metal bus resistance from any of PDB3AC analog signal cells to
the nearest bonded / bumped VSS ground supply (either by PVSS2AC in
the same domain or by PVSS1DGZ cell in the adjacent digital domain) less
than 1 Ohm?
yes
23y.4
Is the maximum signal swing of PDB3AC cell lower than or equal to the
nominal TACVDD + 0.3V?
yes
23y.5
Is the minimum signal swing of PDB3AC cell higher than or equal to 0.3V?
yes
23y.6
Is the connection between PDB3AC and internal analog macro adequately
made based on the N28 I/O application note (e.g. implement the secondary
ESD protection device, etc.)?
yes
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yes or NA
24y.1
Is PDB3A connected to IO transistor?
yes
24y.2
Is PDB3A analog signal cell implemented with PVDD3A analog power
and PVSS3A analog ground in the IO-voltage analog domain?
yes
24y.3
Is the VSS metal bus resistance from any of PDB3A analog signal cells to
the nearest bonded / bumped VSS ground supply (either by PVSS2A in the
same domain or by PVSS1DGZ cell in the adjacent digital domain) less
than 1 Ohm?
yes
24y.4
Is the maximum signal swing of PDB3A cell lower than or equal to the
nominal TAVDD + 0.3V?
yes
24y.5
Is the minimum signal swing of PDB3A cell higher than or equal to -0.3V?
yes
24y.6
Is the connection between PDB3A and internal analog macro adequately
made based on the N28 I/O application note (e.g. implement the secondary
ESD protection device, etc.)?
yes
25
Is PVDD3AC implemented?
yes or NA
25y.1
Are there at least three PVDD3AC cells connected to package in each corevoltage analog domain?
yes
25y.2
Is there at least one PVSS3AC connected to package in each core-voltage
analog domain?
yes
25y.3
Is the PVDD3AC connected to a core-voltage power supply, not an IOvoltage power supply?
yes
25y.4
Is PCLAMPC implemented with PVDD3AC in each core-voltage analog
domain?
yes
26
Is PVDD3A implemented?
yes or NA
26y.1
Are there at least two PVDD3A cells connected to package in each IOvoltage analog domain?
yes
26y.2
Is there at least one PVSS3A connected to package in the IO-voltage
analog domain?
yes
26y.3
Is the PVDD3A connected to a IO-voltage power supply, not a corevoltage power supply?
yes
26y.4
Is PCLAMP implemented with PVDD3A in each IO-voltage analog
domain?
yes
27
Is PVDD1AC implemented?
yes or NA
27y.1
Are there at least three PVDD1AC cells connected to the same package
pin?
yes
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Is PDB3A implemented?
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yes
27y.3
Is PCLAMPC implemented with PVDD1AC?
yes
27y.4
Are there at least three PVDD3AC cells connected to package in each corevoltage analog domain?
yes
27y.5
Is there at least one PVSS3AC connected to package in each core-voltage
analog domain?
yes
28
Is PVDD1A implemented?
yes or NA
28y.1
Are there at least two PVDD1A cells connected to the same package pin?
28y.2
Is the PVDD1A connected to an IO-voltage power supply, not a corevoltage power supply?
28y.3
Is PCLAMP implemented with PVDD1A in each IO-voltage analog
domain?
28y.4
Are there at least two PVDD3A cells connected to package in each IOvoltage analog domain?
yes
28y.5
Is there at least one PVSS3A connected to package in the IO-voltage
analog domain?
yes
29
Is the ramp-up time for analog power up of
PVDD3AC/PVDD3A/PVDD1AC/PVDD1A, respectively, longer than
10us?
yes
30
From metal bus resistance point of view, does the cell placement follow the
Table 10.1 of the TSMC N28 I/O General Application Note?
yes
31
Is this chip flip-chip application?
yes or NA
31y.1
Is the metal bus resistance from the power / ground bump to the
PCLAMPC ESD clamp macro cell less than 0.1 ohm?
yes
31y.2
Is the metal bus resistance from the power / ground bump to the PCLAMP
ESD clamp macro cell less than 0.1 ohm?
yes
32
Is the capacitive load between the “AVDD” pin (on the core side of
PVDD3A / PVDD3AC / PVDD1A / PVDD1AC) and ground pin greater
than or equal to 20pF, respectively?
yes
yes
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Is the PVDD1AC connected to a core-voltage power supply, not an IOvoltage power supply?
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27y.2
yes
yes
Digital Domain Interface Check
TSMC N28 General I/O Library Application Note
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If the I/O cells
aren't placed
as an entire
ring, the
answer must
be "yes".
For other
cases, the
answer could
be "NA".
34
Is PRCUT implemented?
yes or NA
34y.1
Is the PRCUT power-cut cell implemented between two digital I/O
domains, not analog-to-digital domains?
yes
34y.2
Is digital ground PVSS1DGZ or PVSS3DGZ placed right next to both
sides of the PRCUT power-cut cell? (Within 2 cell width from the PRCUT
on each side is acceptable.)
35
Is PENDCAP implemented?
35y.1
It is prohibited to implement any memory IP beside the digital I/O domain
enclosed by the PENDCAP. Do you follow this application rule?
yes
35y.2
Is the distance between the edge of PENDCAP cell and other non-memory
IP at least 20um apart?
yes
35y.3
Is the N-Well / P-Sub of the non-memory IP adjacent to the digital domain
enclosed by PENDCAP connected to power / ground supply within 1 ohm?
yes
35y.4
For the power / ground bus connection from the nearby non-memory IP to
the digital domain, is the total power/ground bus width of the same metal
layer connected from this IP greater than or equal to the total power /
ground bus width of the same metal layer in digital I/O cell?
yes
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yes
yes or NA
Analog Domain Interface Check
36
Is PRCUTA or PENDCAPA cell implemented for analog domain
separation/closure as instructed in the application note?
If the I/O cells
aren't placed
as an entire
ring, the
answer must
be "yes".
For other
cases, the
answer could
be "NA".
37
Is PENDCAPA implemented?
yes or NA
37y.1
It is prohibited to implement any memory IP beside the analog domain
enclosed by the PENDCAPA. Do you follow this application rule?
yes
TSMC N28 General I/O Library Application Note
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Is PRCUT or PENDCAP cell implemented for digital domain
separation/closure as instructed in the application note?
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Is the distance between the edge of PENDCAPA cell and other nonmemory IP at least 20um apart?
yes
37y.3
Is the N-Well / P-Sub of the non-memory IP adjacent to the analog domain
enclosed by PENDCAPA connected to power / ground supply within 1
ohm?
yes
37y.4
For the power / ground bus connection from the nearby non-memory IP to
the analog domain, is the total power/ground bus width of the same metal
layer connected from this IP greater than or equal to the total power /
ground bus width of the same metal layer in analog I/O cell?
yes
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Bond Pad Check
yes or NA
38y.1
Does prBoundary of bonding pads and I/Os originate at (0,0) coordinate?
38y.2
Have the bond pad cell name with "A" been implemented with analog cells, yes
and the bond pad cell name without "A" been implemented with digital
cells?
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Do you use TSMC in-house wire bond pad?
yes
Double I/O Ring Check
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37y.2
39
Are the I/O cells implemented in both the inner and the outer domains
(where inner and outer are with respect to core)?
yes or NA
39y.1
Is the inner ring treated as AAIO placement and follow the rules described
in a separate file named “ApplicationGuide_N28_AAIO” which is
available on TSMC online?
yes
39y.2
Does the core side of the I/O cells in the outer ring face the pad side of the
I/O cells in the inner ring (i.e. the head-to-tail style)?
yes
39y.3
Are the global VSS buses of inner and outer rings connected together with
solid connection? (comply with the "Maximum ESD Current Density for
Via, and Metal" table in DRM)
yes
TSMC N28 General I/O Library Application Note
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Chapter 19 Contact Us
TSMC N28 I/O libraries are released under the supervision of TSMC standard quality assurance (QA)
procedure. For any found issue, please refer to the library release note and designkit.info (packed as
part of the deliverable kits) for guidance on how to tackle the known issues. For any technical
questions, please contact TSMC regional application engineer or your library distributor for assistance.
TSMC Confidential Information 977746 Muse\ Semiconductor\ LLC 03/28/2019
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Chapter 20 TSMC9000 Overview
TSMC9000, overall IP acceptance requirements and review procedure

Memory9000, for SRAMs, register files, ROMs and CAMs

IP9000, for a wide diversity of IP, including eDRAM/1TRAM, electrical-fuse, specialty I/O,
mixed-signal/analog IP, non-volatile memory IP and high-speed PHY IP

Soft-IP9000, for synthesizable IP based on an RTL implementation
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

Library9000, for standard cells, standard I/O and ESD IP
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TSMC works on Library/Memory/IP quality assessment with IP ecosystem partners according to the
TSMC9000 requirements. There are seven assessments defined for hard IP, three of them for physical
review, DFM compliance, and pre-silicon assessment of the design and are performed before test chip
tape-outs. The pre-silicon assessment includes design kits and design margin reviews that are specific
to a certain IP: two of them are typical and split lot silicon assessments which are related to test chip
reports, and the others are IP Validation Center and volume production record. The IP Validation
Center audits IP testing results by the TSMC test laboratory and all IP are monitored in volume
production for issues.
Soft-IP9000, for synthesizable IP based on an RTL implementation, was created to extend
TSMC9000 to cover Soft-IP. Based on the Soft-IP9000 requirements, two soft-IP quality assessments
are done which include RTL code and physical implementation, and soft IP are monitored in volume
production as well.
TSMC9000 Levels of Acceptance
TSMC N28 General I/O Library Application Note
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TSMC9000, TSMC library and IP quality management program, aims to provide customer with
consistent, simple way to review set of minimum quality requirements for libraries and IP designed
for TSMC process technologies. The reviews can be viewed via TSMC-Online using your login info.
TSMC9000 team monitors ongoing IP quality and its requirements are documented and constantly
revised to keep IP quality requirements up-to-date. TSMC IP Alliance members submit required
TSMC9000 data and silicon reports to TSMC for assessments. TSMC9000 assessment results are
posted to TSMC-Online after review. Customers can see the assessment results and scores on TSMCOnline and understand the IP confidence level and/or risk level of using the IP for reference and
judgment. Having these assessment results readily available can significantly shorten design Lead
Time (L/T), which also lowers Total Cost of Ownership (TCO) of the entire SoC design process.
Certification by TSMC9000 is one of the key requirements for acceptance to TSMC IP Alliance
Program. The TSMC9000 requirements are described in the following documents: