Prof. Upendra D Patil
Department of Electronics and Telecommunication Engineering,
PHCET, Rasayani
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Dynamic Read-Write Memory (DRAM) Circuits
• All of the static RAM cells examined in the previous section consist of a twoinverter latch circuit, which is accessed for "read" and "write" operations via
two pass transistors.
• Consequently, the SRAM cells require four to six transistors per bit, and four
to five lines connecting to each cell, including the power and ground
connections.
• To satisfy these requirements, a substantial silicon area must be reserved for
each memory cell.
• In addition, most SRAM cells have non-negligible standby (static) power
dissipation, with the exception of the full CMOS SRAM cell.
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• As the trend for high-density RAM arrays forces the memory cell size to
shrink, alternative data storage concepts must be considered to accommodate
these demands.
• In a dynamic RAM cell, binary data is stored simply as charge in a capacitor,
where the presence or absence of stored charge determines the value of the
stored bit.
• Note that the data stored as charge in a capacitor cannot be retained
indefinitely, because the leakage currents eventually remove or modify the
stored charge.
• Thus, all dynamic memory cells require a periodic refreshing of the stored
data, so that unwanted modifications due to leakage are prevented before they
occur.
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• The use of a capacitor as the primary storage device generally enables the
DRAM cell to be realized on a much smaller silicon area compared to the
typical SRAM cell.
• Notice that even as the binary data is stored as charge in a capacitor, the
DRAM cell must have access devices, or switches, which can be activated
externally for "read" and "write“ operations.
• But this requirement does not significantly affect the area advantage over the
SRAM cell, since the cell access circuitry is usually very simple.
• Also, no static power is dissipated for storing charge on the capacitance
• Consequently, dynamic RAM arrays can achieve higher integration densities
than SRAM arrays.
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• Note that a DRAM array also requires additional peripheral circuitry for
scheduling and performing the periodic data refresh operations.
• The hardware overhead of the refresh circuitry, however, does not overshadow
the area advantages gained by the small cell size.
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• Figures below shows some of the steps in the historical evolution of the
DRAM cell.
• The four-transistor cell shown in Fig. (a) is the simplest and one of the earliest
dynamic memory cells.
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• This cell is derived from the six-transistor static RAM cell by removing the
load devices.
• The cell has in fact two storage nodes, i.e., the parasitic oxide and diffusion
capacitances of the nodes indicated in the circuit diagram.
• Since no current path is provided to the storage nodes for restoring the charge
being lost to leakage, the cell must be refreshed periodically.
• It is obvious that the four-transistor dynamic RAM cell can have only a
marginal area advantage over the six-transistor SRAM cell.
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• The three-transistor DRAM cell shown in Fig. (b) was the first widely used
dynamic memory cell.
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• It utilizes a single transistor as the storage device (where the transistor is
turned on or off depending on the charge stored on its gate capacitance), and
one transistor each for the "read" and "write" access switches.
• The cell has two control and two I/O lines.
• Its separate read and write select lines make it relatively fast, but the four lines
with their additional contacts tend to increase the cell area.
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• The one-transistor DRAM cell shown in Fig. (c) has become the industry
standard dynamic RAM cell in high-density DRAM arrays.
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• With only one transistor and one capacitor, it has the lowest component count
and, hence, the smallest silicon area of all the dynamic memory cells.
• The cell has one read-write control line (word line) and one I/O line (bit line).
• Unlike in the other dynamic memory cells, the storage capacitance of the onetransistor (1T) DRAM cell is explicit.
• This means that a separate capacitor must be manufactured for each storage
cell, instead of relying on the parasitic oxide and diffusion capacitances of the
transistors for data storage.
• The word line of the one-transistor DRAM cell is controlled by the row
address decoder.
• Once the selected transistor is turned on, the charge stored in the capacitor can
be detected and/or modified through the bit line.
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Three-Transistor DRAM Cell
• The circuit diagram of a typical threetransistor dynamic RAM cell is shown in
Fig. as well as the column pull-up
(precharge) transistors and the column
read/write circuitry.
• Here, the binary information is stored in
the form of charge in the parasitic node
capacitance Cl.
• The storage transistor M2 is turned on or
off depending on the charge stored in C1,
and the pass transistors Ml and M3 act as
access switches for data read and write
operations.
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Three-transistor DRAM cell with the pull-up and
read/write circuitry.
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• The cell has two separate bit lines for "data read" and "data write," and two
separate word lines to control the access transistors.
• The operation of the three-transistor DRAM cell and its peripheral circuitry is
based on a two-phase non-overlapping clock scheme.
• The precharge events are driven by ϕ1, whereas the "read" and "write" events
are driven by ϕ2.
• Every "data read" and "data write“ operation is preceded by a precharge cycle,
which is initiated with the precharge signal PC going high.
• During the precharge cycle, the column pull-up transistors are activated, and
the corresponding column capacitances C2 and C3 are charged up to logichigh level.
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• With typical enhancement type nMOS pull-up transistors (VTO≈ 1.0 V) and a
power supply voltage of 5 V, the voltage level of both columns after the
precharge is approximately equal to 3.5 V.
• All "data read" and "data write" operations are performed during the active ϕ2
phase, i.e., when PC is low.
• Figure below depicts the typical voltage waveforms associated with the 3T
DRAM cell during a sequence of four consecutive operations: write " 1," read
"1,“ write "0," and read "0.“
• The four precharge cycles shown in this Fig. are numbered 1, 3, 5, and 7,
respectively.
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Typical voltage waveforms associated with the 3-T DRAM cell during four consecutive operations: write "1," read "1,"
write "0," and read "O.
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One-Transistor DRAM Cell
• The circuit diagram of the one-transistor (1-T) DRAM cell consisting of one
explicit storage capacitor and one access transistor is shown in Fig.
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• Here, Cl represents the storage capacitor which typically has a value of 30 to
100 fF.
• Similar to the 3-T DRAM cell, binary data are stored as the presence or
absence of charge in the storage capacitor.
• Capacitor C2 represents the much larger parasitic column capacitance
associated with the word line.
• Charge sharing between this large capacitance and the very small storage
capacitance plays a very important role in the operation of the -T DRAM cell.
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• The "data write" operation on the 1-T cell is quite straightforward.
• For the write "1“ operation, the bit line (D) is raised to logic " 1 " by the write
circuitry, while the selected word line is pulled high by the row address
decoder.
• The access transistor Ml turns on, allowing the storage capacitor C1 to charge
up to a logic-high level.
• For the write “0“ operation, the bit line (D) is pulled to logic “0" and the word
line is pulled high by the row address decoder.
• In this case, the storage capacitor C1 discharges through the access transistor,
resulting in a stored “0" bit.
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• In order to read stored data out of a 1-T DRAM cell, on the other hand, we have to
build a fairly elaborate read-refresh circuit.
• The reason for this is the fact that the "data read" operation on the one-transistor
DRAM cell is by necessity a "destructive readout."
• This means that the stored data must be destroyed or lost during the read operation.
• Typically, the read operation starts with precharging the column capacitance C2
• Then, the word line is pulled high in order to activate the access transistor Ml.
• Charge sharing between C1 and C2 occurs and, depending on the amount of stored
charge on C1, the column voltage either increases or decreases slightly.
• Note that charge sharing inevitably destroys the stored charge on C1.
• Hence, we also have to refresh data every time we perform a "data read" operation.
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Floating Gate Memory
• A MOSFET made with
two layers of poly is seen
in Fig. (along with its
schematic symbol and a
typical layout).
• As seen in the figure, the
polyl is floating, that is,
not electrically
connected to anything.
• A dielectric surrounds
this floating island of
polyl.
A floating gate MOSFET, its symbol and layout
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• With the gate oxide on the bottom, a thin oxide insulates the MOSFET from
the poly2 (word/row line) above.
• Poly2 is the controlling gate of the transistor (the terminal we drive to turn the
MOSFET on).
• We are going to make a memory element out of this cell by changing, adding
or removing, the charge stored on the floating gate.
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• Figure shows the difference between the erased state and the programmed
state in a floating gate memory.
• The erased state, the state of the memory when it is fabricated (that is, before
we force charge onto the floating gate), shows normal MOSFET behavior.
Programmed and erased states of a floating gate memory.
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• Above the threshold voltage, the device turns on and conducts a current.
• When the cell is programmed, we force a negative charge (electrons) onto the
floating gate (how we force this charge will be discussed shortly).
• This negative charge attracts a positive charge beneath the gate oxide.
• The result is that a larger controlling gate voltage must be applied to turn the
device on (the threshold voltage increases).
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Trapped negative charge on the floating gate.
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Erasable Programmable Read-Only Memory (EPROM)
• Erasable programmable ROM (EPROM) was the first floating gate memory
that could be programmed electrically.
• To erase (return the cell to its fabricated state, that is, leave no trapped charge
on the floating gate), the cell is exposed to ultra-violet light through a quartz
window in the top of the chip's package.
• The ultra-violet light increases the conductivity of the silicon-dioxide
surrounding the floating gate and allows the trapped charge to leak off.
• The inability to erase the EPROM electrically has resulted in its being replaced
by Flash memory (discussed later).
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• Programming the
EPROM relies on
channel hot-electron
(CHE) injection
• CHE is accomplished by
driving the gate and the
drain of the MOSFET to
high voltages (say a
pumped voltage of 25
V), Fig.
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• The high voltage on the drain of the device causes hot electrons (those with
significant kinetic energy) to flow in the channel.
• A large positive potential applied to the gate attracts some of these electrons to
the floating gate.
• The electrons can penetrate the potential barrier between the floating gate and
channel because of their large energies.
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Important Notes
• When we are programming the floating gate device, the accumulation of electrons
on the floating gate causes an increase in the device's threshold voltage.
• The more electrons that are trapped the higher the threshold voltage.
• This increase in threshold voltage causes the drain current to decrease.
• The decrease in drain current then reduces the rate at which the electrons are trapped
on the floating gate oxide.
• If we apply the programming voltages for a long period of time, the drain current
drops to zero (or practically a small value).
• Because of this feedback mechanism, the programming is said to be self-limiting
• We simply apply the high voltages for a long enough time to ensure that the selected
devices are programmed.
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• Next examine Row of floating gate devices.
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• When we are programming a row of cells, we drive the word line to a high
voltage.
• If the cell is to remain erased, we simply leave the corresponding bit line at
ground.
• If the cell is to be programmed, we drive the bit line to the high voltage.
• For CHE, both the drain and gate terminals of the floating device must be at a
high voltage.
• This is important because it removes the need for a select transistor
(something we'll have to use in other programming methods to keep from
programming an unselected cell).
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Flash Memory
• By reducing the thickness of the oxide from, say, 300 A (a typical value used
in an EPROM) to 100 Ä, Fowler-Nordheim tunneling (FNT) [2] can be used
to program or erase the memory cell.
• Floating gate memory that can be both electrically erased and programmed is
called electrically erasable programmable ROM (EEPROM).
• Note that this name is an oxymoron. If we can electrically write to the
memory, then it isn’t a read-only memory.
• For this reason, and because the rows of memory are generally erased in a
flash (that is, large amounts of memory, say a memory array, are erased
simultaneously and, when compared to the EPROM method of removing the
chips from the system and exposing to ultra-violet light to erase, very quickly),
we call floating gate memory that can be electrically programmed and erased
Flash memory.
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• While CHE and FNT can be used together (CHE for the programming and
FNT for erasing) to implement a memory technology, we assume FNT is used
for both programming and erasing in the remaining discussion.
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• Figure shows the basic idea of using FNT to program a device (recall that this
means to trap electrons on the floating gate so that the devices threshold
voltage increases).
FNT of electrons from the p-well to a floating gate to increase threshold voltage (showing programming).
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• The control gate (poly2) is driven to a large positive voltage.
• For a 100 gate oxide this voltage is somewhere between 15 and 20 V.
• Note that we are assuming that our NMOS devices are sitting in a p-well that
is sitting in an n-well (so we can adjust the p-well [body of the NMOS]
potential).
• The electrons tunnel through the thin oxide via FNT and accumulate on the
floating gate.
• Like programming in an EPROM device, this mechanism is self-limiting.
• As electrons accumulate on the floating gate, the amount of tunneling current
falls.
• Note that if we didn't want to program the device when poly2 is at 20 V we
could hold the drain at a higher voltage (not ground) to reduce the potential
across the thin gate oxide (aka tunnel oxide).
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• To erase the device using FNT, examine Fig. Both the p-well and the n-well
are driven to 20 V while the control gate (poly2) is grounded.
FNT of electrons from the floating gate to p-well to decrease threshold voltage (showing erasing).
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• Electrons tunnel via FNT off of the floating gate (polyl) to the p-well.
• The source and drain contacts to the device are floating (to accomplish this we
will float the bit line and the source n+ outside of the array).
• Again, the movement of charge is self-limiting (however, there are device
issues that can result in over erasing).
• The tunnel current drops as positive charge accumulates on the floating gate.
• If the erasing time is long, a significant amount of positive charge can
accumulate on the floating gate.
• This will decrease the threshold voltage of the MOSFET.
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• Figure shows the programmed and erase states for a Flash memory where a
positive threshold voltage indicates that the device is programmed and a
negative threshold voltage indicates that the device is erased (we show ± 3 V
as typical values).
Programmed and erased states of a flash memory.
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• The schematic
and layout of a 4bit NAND Flash
memory cell is
seen in Fig.
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• The select transistors are made using single poly (normal) MOSFETs.
• When the cell (all four bits) is erased, the p-well and the n-well are driven to
20 V external to the memory array via the p+ implant.
• The bit lines and the n+ source connection at the bottom of the layout are
floated.
• The four control gates and the two select MOSFET gates are pulled to ground
(so all six poly gates, aka, word lines, are at ground for an erase).
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• To illustrate
programming
the floating
gate MOSFET
connected to
RAO (row
address 0),
examine the
connections to
the NAND cell
seen in Fig.
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The bit line is driven to ground.
A voltage, say 20 V, is applied to the gate of the top select gate.
The gates of the floating gate MOSFETs connected to RA1-RA3 are driven to 5V.
This 5 V signal turns on these devices but isn't so big that FNT will occur in them.
The bottom select MOSFET remains off so that there is no DC path from the bit line
to ground.
• The p-well (which is common to all of the cells in the memory array, that is, not just
the four in the memory cell) is pulled to ground external to the memory array via the
p+ implant.
• Because the gate, RAO, is pulled to 20 V and the drain implant is pulled to ground
through the bit line, the device will be programmed (electrons will tunnel through
the oxide and accumulate on the floating gate).
•
•
•
•
•
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• The next thing we need to look at before talking about reading the cell is how
we keep from programming the adjacent floating gate devices, those also
connected to RAO, if they are to remain erased.
• What we need to do is ensure that no FNT occurs in these unselected devices.
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• Figure shows how we keep
from programming a
device.
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• The bit line of the cell that is to remain erased is driven to a voltage that is
large enough to keep FNT from occurring.
• The bottom select MOSFET is off, so there won't be a DC path from the bit
line to ground (this is important because all other MOSFETs in the memory
cell will be on).
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• To understand reading a NAND Flash cell, consider the Fig.
Expanded view showing erased and programmed IV curves
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• If both select transistors are turned on (say 5 V on their gates), the unselected
row lines are driven high (say, again, to 5 V), and the selected row line is held
at zero volts, then the current difference between Ierased and Iprog can be used to
determine if the (selected) floating gate MOSFET is erased or programmed.
• If an average current, that is, (Ierased + Iprog)/2 is driven into the bit line, an
erased cell will keep the bitline at a low voltage.
• The selected (erased) MOSFET will want to sink a current of Ierased when its
gate is zero volts.
• A programmed cell won't be able to sink this current (it will want to sink a
current of Iprog) and so the bit line will go high.
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• Table
shows a
summary of
erasing,
programmi
ng, and
reading a
NAND
Flash
memory
cell.
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NPTEL / Swayam Course:
1. https://nptel.ac.in/courses/117/101/117101058/
2. https://nptel.ac.in/courses/108/107/108107129/
VLABs
1. https://vlsi-iitg.vlabs.ac.in/
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References
• [1] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital
Integrated Circuits: A Design Perspective”, Pearson Education, 2nd Edition.
• [2] Lenzlinger, M., and E. H. Snow. "Fowler‐Nordheim tunneling into
thermally grown SiO2." Journal of Applied physics 40.1 (1969): 278-283.
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