FP
Floorplan styles:
There are two styles in which macros can be placed which gives us two floorplan
types namely: abutted floorplan and channelled floorplan.

Abutted Floorplan:
In this floorplan style, macros are placed adjoining to each other without leaving any
space in between. Generally this style is not recommended because channel is
required in between macros to serve purpose for routing, buffering of macro pins and
to meet implant layer spacing rules.

Channelled Floorplan:
Channelled floorplan is one in which appropriate spacing is provided between
macros. Minimum spacing between macros can be computed using below formula:
For example if there are 100 pins in a macro on layer M3 whose pitch is 0.5 microns.
In total we have 8 metal layers available for routing out of which 4 are vertical layers
and 4 are horizontal. According to above formula, minimum vertical spacing =
(100*0.5)/(4) = 12.5 microns.
Floorplan Stages:
Broadly speaking floorplanning comprises of 3 major stages.

Create die and core

Port placement

Create voltage area

Macro placement

Physical cells

Power planning
Inputs for Floorplanning :
Various input files required to kick start floorplanning are:
 Synthesized netlist (.v)

.tf

.lib & .lef

Design constraints (SDC)

.upf

.tlu+
# Creating core and die area
initialize_floorplan -core_offset 5 -core_utilization 0.75 -side_ratio {} -site_def
unit -flip_first_row true -use_site_row
# Port Placement
# side 1, pin_spacing 5 , layer M5 , corner_keepout 100u .
remove_block_pin_constraints -self
remove_individual_pin_constraints
set_block_pin_constraints -allowed_layers M5 -corner_keepout_distance 100 pin_spacing 5 -sides 1 -self
place_pins -ports [remove_from_collection [all_inputs ] [get_ports *clk*]]
check_pin_placement -ports [all_inputs ] -wire_track true -corner_keep_out
true
# Place output ports
# side 3, pin_spacing 5 , layer M5 , corner_keepout 100u .
remove_block_pin_constraints -self
set_block_pin_constraints -allowed_layers M5 -corner_keepout_distance 100 pin_spacing 5 -sides 3 -self
place_pins -ports [all_outputs]
check_pin_placement -ports [all_outputs ] -wire_track true -corner_keep_out
true
# Clock ports
# side 2 , pin_spacing 5, layer M6 , corner_keepout 100u
remove_block_pin_constraints -self
set_block_pin_constraints -allowed_layers M6 -corner_keepout_distance 100 pin_spacing 5 -sides 2 -self
place_pins -ports [get_ports *clk*]
check_pin_placement [get_port *clk*] -wire_track true -corner_keep_out true
#Load upf
load_upf ./inputs/ORCA_TOP.upf
connect_pg_net
check_mv_design
# Create voltage area and guardband
create_voltage_area -power_domains PD_RISC_CORE -region $va_bbox guard_band {{ }}
#Macro placement
# Apply keepout margin around macro
create_keepout_margin -outer { } [get_flat_cells -filter "is_hard_macro"] -type
hard
# Check PG drc
check_pg_drc
# check pg connectivity
check_pg_connectivity -check_std_cell_pins none
# Fix macros
set_attribute [get_flat_cells -filter "is_hard_macro"] physical_status -value
fixed
# Endcap-cells
remove_cell [get_flat_cells *boundarycell* -all ]
set_boundary_cell_rules -left_boundary_cell
saed32_hvt|saed32_hvt_std/DCAP_HVT -right_boundary_cell
saed32_hvt|saed32_hvt_std/DCAP_HVT -at_va_boundary
compile_boundary_cells
check_boundary_cells
# Tap Cells
remove_cells [get_flat_cells *tapfiller* -all ]
create_tap_cells -lib_cell saed32_hvt|saed32_hvt_std/DCAP_HVT -distance 30
-pattern stagger -skip_fixed_cells
check_legality
# Power Planning
Output files after performing floorplanning are:

Floorplan DEF(.def)

Floorplan netlist (.v)

Initial utilization report