1. Different type of physical cells (special cell)
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ANS:
ENDCAP Cell (Boundary Cell)
TAP Cell
DECAP Cell
SPARE Cell
TIE Cell
Filler Cell
1) ENDCAP Cell (Boundary Cell):
There are high chances to get damaged the gate of standard cells placed
at the boundary during the manufacturing of chip.
To prevent such damages at the boundary we have a special kind of cell
in the standard cell library is called end cap cell or boundary cell.
Why need to place End Cap / Boundary Cell?
To protect the gate of a standard cell placed near the boundary from
damage during manufacturing.
To make the proper alignment with the other block.
Some standard cell library has end cap cell which serve as decap cell
also.
Where to place End Cap / Boundary Cells
The end cap cell or boundary cell is placed at both the ends of each
placement row to terminate the row.
It has also been placed at the top and bottom row at the block level to
make integration with other blocks.
Some standard cell library has also corner end cap cells to place the
corner of the block.
Boundary cells have fixed attribute, therefore these cells can not be
moved during the optimization.
2) TAP Cell or well tap Cell:
Ans:
Well tap cells (or Tap cells) are used to prevent the latch-up issue in the
CMOS design.
Well tap cells connect the nwell to VDD and p-substrate to VSS in order
to prevent the latch-up issue.
There is no logical function in well tap cell rather than proving a taping
to nwell and p-substrate therefore well tap cell is called a physical-only
cell.
Well tap cells having no logical functions, it has only two connections.
nwell to the power supply (VDD)
p-substrate to the ground (VSS)
Well tap cell has no input and output pins, therefore it is called a
physical-only cell.
3) DECAP Cell
Decap cells are basically a charge storing device made of the capacitors
and used to support the instant current requirement in the power
delivery network.
Power droop or ground bounce may occur. These power droop or
ground bounce will affect the constant power supply and ultimately the
delay of standard cells may get affected.
To support the power delivery network from such sudden power
requirements, decap cells are inserted throughout the design.
Decap capacitor schematic using a pMOS and an nMOS transistor.
From this schematic, we can say that the capacitance due to nMOS and
pMOS will be in parallel and get added to form a big capacitor.
4) SPARE Cell
ANS:
Once a chip is fabricated and if any functionality issue is found in the
chip or some functionality enhancement is required in the next
fabrication.
This might be a very challenging task without spare cells. But with the
help of pre-placed spare cells, these changes can be done very easily.
Spare cells generally consist of a group of standard cells mainly
inverter, buffer, nand, nor, and, or, exor, mux, flip flops and maybe
some specially designed configurable spare cells.
The inputs of spare cells are tied either VDD or VSS through the tie
cell and the output is left floating.
Spare cells enable us to modify/improve the functionality of a chip
with minimal changes in the mask.
We can use already placed spare cells from the nearby location and
just need to modify the metal interconnect.
5) TIE Cell
Ans:
The tie cell is a standard cell, designed specially to provide the high or
low signal to the input (gate terminal) of any logic gate.
The high/low signal can not be applied directly to the gate of any
transistors because of some limitations of transistors, especially in the
lower node.
A tie cell is used to connect the input of any logic to
the VDD or VSS.
Schematic of tie cells:
There are two types of tie cells.
Tie-high cell
Tie- low cell
The tie cell has no input pin and only one output pin. The output of the
tie-high cell is always high and the output of the tie-low cell is always
low and it is the glitch-free output that connects to the input of any logic
gates.
In the tie-high cell, the drain and gate of nMOS are shorted together and
connected to the gate of pMOS, and output is taken from the drain of
pMOS. Whereas in the tie-low cell the drain and gate of pMOS are
shorted together and connected to the gate of nMOS and output is taken
from the drain of nMOS.
6) Filler Cell
Ans:
Filler cells are inserting for density rules, to meet core utilization targets
and to avoid sagging of layer.
Filler cells are inserting at the last stage of placement and routing.
2) What are metal layers ?
Ans:
To route any PG/Clock/Signal we need metal layers.
There can be number of metal layers which has been used to complete the routing.
The number of metal layers to be used depend upon the foundry and technology
node.
The metal layers are drawn in such a way that from M0-M14 we will have
Horizontal and vertical metal layers. That means M0 is horizontal, M1 is vertical,
M2 is horizontal and so on.
To connect with these metal layers, we need VIAs which connects two metal
layers.
Resistance value is decreases if we go further to higher metal layers. Normally
M1 has 1.5 times higher resistance than M2.
3) What is VIA ?
Ans:
Via is an electrical connection that establishes the connectivity between two
layers.
Vias are established at points where a net changes layer. But if the number of vias
is more, then it not only reduces the reliability of the product but also causes delay
and affects the circuit performance.
There three types of VIA:
1.Single Via
2.Array Via
3.Stacked Via
Via & Metal connection view:
1. Single Via & Array Via
2. Stacked Via