2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004 An Improved ZVS PWM Full-bridge Converter with Clamping Diodes Xinbo Ruan, Senior Member, IEEE, and Fuxin Liu Aero-Power Sci-tech Center College of Automation Engineering Nanjing University of Aeronautics and Astronautics Nanjing, 210016, Jiangsu Province, P.R.China Phone: 0086-25-84892053, Fax: 0086-25-84893500 E-mail: ruanxb@nuaa.edu.cn Abstract － Phase-shifted ZVS PWM full-bridge converter realizes ZVS and eliminates the voltage oscillation caused by the reverse recovery of the rectifier diodes by introducing a resonant inductance and two clamping diodes. This paper improves the converter just by exchanging the position of the resonant inductance and the transformer such that the transformer is connected with the lagging leg. The improved converter has several advantages over the original counterpart, e.g., the clamping diodes conduct only once in a switching cycle, and the resonant inductance current is smaller in zero state, leading to a higher efficiency and reduced duty cycle loss. A blocking capacitor is usually introduced to the primary side to prevent the transformer from saturating, this paper analyzes the effects of the blocking capacitor in different positions, and a best scheme is determined. A 2850W prototype converter is built to verify the effectiveness of the improved converter and the best scheme for the blocking capacitor. I. INTRODUCTION Phase-shifted full-bridge converters have been widely used in medium-to-high power applications because they achieve zero-voltage-switching (ZVS) with the use of the leakage inductance of the high-frequency transformer and the intrinsic capacitors of the switches without no additional active switch or passive element, and phase-shifted control is a pulse-width modulation [1-3]. The leading leg is easy to achieve ZVS using the energy stored in both the output filter inductance and the leakage inductance. The lagging leg realizes ZVS using the energy stored in the leakage inductance, it will lose ZVS at light load because the leakage inductance is quite small. A saturable inductance is introduced instead of the leakage inductance to achieve ZVS for the lagging leg in a wide load range and reduce the duty cycle loss [4]. However the saturable inductance brings large loss and limits the switching frequency. In order to achieve soft-switching for the lagging leg in a wide load range, [5-8] proposed several topologies to achieve zerocurrent-switching (ZCS) for the lagging leg. All the converters mentioned above achieve softswitching for the power switches, however the reverse recovery of the rectifier diodes still results in voltage oscillation and voltage spike. Richard Redl, et al, introduced a resonant inductance Lr (instead of the leakage inductance) and two clamping diodes, D5 and D6, into the primary side as shown in Fig.1(a), which clamps the output rectified voltage at the reflected input voltage, thus the voltage oscillation is eliminated, and the diodes with lower voltage rating can be 0-7803-8399-0/04/$20.00 ©2004 IEEE. adopted [9, 10]. The transformer is connected with the leading leg and the resonant inductance is connected with the lagging leg as well. As shown in Fig.1(b), the converter has the following demerits: 1) the clamping diodes conduct twice in a switching cycle, one of which is useless for the voltage-clamping; 2) in zero state (vAB=0), the resonant inductance current is freewheeling, resulting in relatively high conduction loss; and 3) when a blocking capacitor is inserted in series with the transformer or the resonant inductance to prevent the transformer from saturating, the dc component of vAB applied on the blocking capacitor will result in asymmetry in both directions of the current of the transformer or the resonant inductance. This paper improves the converter in Fig.1(a) by simply exchanging the position of the transformer and the resonant inductance such that the transformer is connected with the lagging leg. This improvement not only keeps the advantage that the voltage oscillation is eliminated, but also the clamping diodes only conduct once, and the resonant inductance current in zero state is reduced, leading to reduced conduction loss in the primary side, and as a result, the efficiency is expected to be increased. In this paper, Section II analyzes the operation principle of the improved converter. Section III compares the improved converter and the original one. Section IV analyzes the effect of the blocking capacitor in different positions, and a best scheme is determined. Section V presents the experimental results to verify the advantages of the improved converter and the best scheme for the blocking capacitor. II. OPERATION PRINCIPLE Fig.2 shows the main circuit and key waveforms of the improved converter. We define the converter in Fig.1(a) as Tr-lead type because the transformer is connected with the leading leg, and the improved converter in Fig.2(a) as Tr-lag type because the transformer is connected with the lagging leg. The Tr-lead type converter is analyzed in details in [9] and [10]. Here we analyze the operation principle of the Tr-lag type converter. In a switching cycle, the improved converter has 16 switching modes. Fig.3 gives the equivalent circuits of the switching modes in a half cycle. Before the analysis, some assumptions are made: 1) all the switches and diodes are ideal, except for the rectifier diode, which is equivalent to an ideal diode and a capacitor to simulate the reverse recovery; 1476 2004 35th Annual IEEE Power Electronics Specialists Conference D1 Q1 D5 * C Tr Q3 D3 C3 C2 *D R1 B iLr Q4 D6 D4 D1 Lf Tr Q2 Lr ip A Vin D2 C1 * + _ vrect Aachen, Germany, 2004 RLd Cf + Vo _ Q1 DR2 Q4 (a) Main circuit Q1 Q3 Q4 Q1 Q2 vAB Q4 I5 Vin 0 Q1 t vrect Cf + Vo _ C4 Q4 t Q1 Q2 I1 iLr ip I2 Q4 t I3 vAB Vin t t 0 t Vin iD5 -I4 iD5 t iD6 t t iD6 t vrect Vin /K t 0 t0 t1 t2 t3 t4 t5 t6 t7 D4 _ RLd DR2 Q3 Vin vrect * + (a) Main circuit I1 iLr ip *D R1 Tr D6 Lf Tr B C C3 D3 C2 Q2 ip * iLr Q3 C4 D5 Lr A Vin D2 C1 t 0 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t0 t1 t2 t3 t4 t5 t6 t7 (b) Key waveforms Fig.1 ZVS PWM full-bridge converter proposed by Redl, et al. t8 t9 t10t11 t12t13t14 t15 t16 t17 t18 (b) Key waveforms Fig.2 Improved ZVS PWM full-bridge converter. 2) all the capacitors and inductance are ideal; 3) C1=C3=Clead, C2=C4=Clag; 4) Lf>>Lr/K2, where K is the primary to secondary windings ratio; and 5) the leakage inductance of the transformer is very small to be ignored. 1) Mode 1 [t0, t1] [Fig.3(a)]: Prior to t0, Q1, Q4 and DR1 conduct. At t0, Q1 is turned off, the resonant inductance current iLr charges C1 and discharges C3, the potential voltage of point A decays. Q1 is zero-voltage turn-off thanks to C1 and C3. As the potential voltage of point C is greater than zero, D6 is reverse biased. Will D5 conduct? If D5 conduct, the primary voltage of the transformer is clamped at Vin, and the secondary voltage keeps unchanged accordingly, so ip will keep unchanged. A negative voltage is applied on Lr, forcing iLr to decay, so ip is greater than iLr. The difference current of ip and iLr will flow through D6, which is conflicted with the conduction of D5. Therefore D5 does not conduct. This mode can be further simplified as Fig.4(a), where C D′ is the reflected CDR2 to the primary side, and I1 is the reflected filter inductance current at t0. C'D I 1 sin ω1 (t − t 0 ) v C1 (t ) = 2C lead (2C lead + C ' D )ω1 (1) 1 + I 1 (t − t 0 ) 2C lead + C ' D v C 3 (t ) = Vin − v C1 (t ) Vin /K (2) i p (t ) = i Lr (t ) = C' D I 1 cos ω1 (t − t 0 ) 2C lead + C ' D 2C lead I1 + 2C lead + C ' D v C 'D (t ) = 1 ( I 2 − I 1 ) sin ω 2 (t − t1 ) C ' D ⋅ω 2 (3) (4) + Vin cos ω 2 (t − t1 ) 2C lead + C ' D . 2C lead ⋅ C ' D ⋅Lr At t1, the voltage of C3 decays to zero, and D3 conducts. 2) Mode 2 [t1, t2] [Fig.3(b)]: After D3 conducts, Q3 can be zero-voltage turned on. CDR2 continues being discharged, and iLr and ip continue decaying. The equivalent circuit is further simplified as Fig.4(b). i p (t ) = i Lr (t ) = ( I 2 − I 1 ) cos ω 2 (t − t1 ) where ω1 = − v C ' D (t ) = VC ' D (t1 ) Lr ω 2 sin ω 2 (t − t1 ) + I 1 1 ( I 2 − I 1 ) sin ω 2 (t − t1 ) C ' D ⋅ω 2 + VC ' D (t1 ) cos ω 2 (t − t1 ) where ω 2 = 1 1477 Lr ⋅ C ' D , I2 is the primary current at t1. (5) (6) 2004 35th Annual IEEE Power Electronics Specialists Conference D1 Q1 Vin D2 C1 D5 Lr A iLr Q3 D3 * C C3 ip CDR1 C2 Tr B * Tr Q4 D6 D4 C4 D1 Lf *D R1 Q2 Aachen, Germany, 2004 RLd Cf + Vo _ Q1 Vin DR2 D5 Lr A Q3 CDR2 vCDR2+ _ D2 C1 iLr D3 * C C3 Q1 Vin D2 C1 D5 Lr A iLr Q3 D3 * ip * Tr Q4 D6 D4 D1 Lf *D R1 B C C3 Tr Q2 RLd Q1 Vin D2 C1 Cf + Vo _ Q1 Vin DR2 C4 D5 Lr A iLr Q3 D3 * C C3 ip iLr D3 B * Q4 D6 D4 D1 Lf *D R1 Tr * C C3 Q1 Vin D2 C1 D5 RLd + Vo _ Cf Q1 Vin DR2 C4 Lr A iLr Q3 D3 * ip iLr C3 * Tr Q4 D6 D4 Vin Lr C RLd Cf + Vo _ C4 * DR2 CDR1 Tr Q4 Lf *D R1 Q2 * D4 C4 RLd Cf + Vo _ DR2 CDR2 ip C2 Tr *D R1 Q2 B * Tr Q4 v _ CDR1 + CDR1 Lf D4 RLd Cf + Vo _ DR2 C4 CDR2 I1 C D5 iLr D3 * C C3 ip C2 CDR1 Tr *D R1 Q2 B * Tr D6 Q4 D4 C4 C'D I1 At t2, CDR2 is fully discharged, and DR2 conducts, the potential voltage of point C decays to zero. 3) Mode 3 [t2, t3] [Fig.3(c)]: DR1 and DR2 conduct simultaneously, clamping the secondary voltage at zero. The potential voltages of point A, B and C are zero. iLr is equal to ip, and they are freewheeling. 4) Mode 4 [t3, t4] [Fig.3(d)]: At t3, turn off Q4, ip charges C4 and discharges C2. Q4 is zero-voltage turn-off thanks to C2 and C4. As both the rectifier diodes are conducting, both the primary and secondary voltages of the transformer are zero, vAB is fully applied on Lr. During this interval, Lr resonates with C2 and C4. i L r (t ) = i p (t ) = I 3 cos ω 3 (t − t 2 ) (7) (8) Lf RLd Cf + Vo _ DR2 CDR2 (h) [t8, t9] where Z r1 = Lr 2C lag , ω 3 = 1 (a) Mode 1 (b) Mode 2 Fig.4 Further simplified equivalent circuits of mode 1 and mode 2 vC 4 (t ) = Z r1 I 3 sin ω 3 (t − t 2 ) D2 C1 vC 2 (t ) = Vin − Z r1 I 3 sin ω 3 (t − t 2 ) Lr ip=iLr C'D C2 B D6 Fig.3 Equivalent circuits of the switching modes A C3 + Vo _ CDR2 vCDR2+ _ Tr C Lr A Q3 CDR2 A ip=iLr Q1 Vin DR2 (g) [t7, t8] C1 ip D5 C3 D3 D1 Lf *D R1 B C C4 Cf (f) [t6, t7] Tr Q2 D4 D2 C1 Lr A Q3 CDR2 CDR1 C2 Q4 D6 (e) [t4, t6] D1 * RLd (d) [t3, t4] Tr Q2 B Tr D5 Lr A Q3 CDR2 CDR1 C2 *D R1 D2 C1 (c) [t2, t3] D1 ip Lf (b) [t1, t2] CDR1 C2 Tr Q2 D6 (a) [t0, t1] D1 CDR1 C2 (9) 2 Lr C lag , I3 is the primary current at t2. At t4, the voltage of C4 rises to Vin, and the voltage of C2 decays to zero, D2 conducts. 5) Mode 5 [t4, t6] [Fig.3(e)]: Q2 can be zero-voltage turned on with D2 conducting. During this mode, ip is not enough to provide the load current, both the rectifier diodes continue conducting. Vin is fully applied on Lr, iLr and ip decay linearly. Before t5, ip flows though D2 and D3. After t5, iLr and ip across zero and continue increasing in the negative direction and flow through Q2 and Q3. At t6, ip reaches the reflected filter inductance current, DR1 turns off, and DR2 carries all the load current. 6) Mode 6 [t6, t7] [Fig.3(f)]: At t6, Lr resonates with CDR1, CDR1 is charged, ip and iLr continue increasing. I Lf (t 6 ) Vin i p (t ) = i Lr (t ) = + sin ω 4 (t − t 6 ) (10) K Z r2 v CDR 1 ( t ) = 2V in [1 − cos ω 4 ( t − t 6 )] K where Z r 2 = Lr C D′ , ω 4 = 1 1478 Lr C D′ . (11) 2004 35th Annual IEEE Power Electronics Specialists Conference At t7, the voltage of CDR1 rises to 2Vin /K, and the primary voltage of the transformer, vBC, is Vin, the potential voltage of point C reduces to zero. So D6 conducts, clamping vBC at Vin, and the voltage of CDR1 is clamped at 2Vin /K accordingly. I Lf (t 6 ) Vin + I Lr (t 7 ) = I p (t 7 ) = − ≡ −I 4 . Zr2 K 7) Mode 7 [t7, t8] [Fig.3(g)]: When D6 conducts, ip decays downwards to the reflected filter inductance current, and increases in the negative direction. iLr keeps unchanged. The difference of iLr and ip flows through D6. At t8, ip equals to iLr, and D6 is turned off. V − KVo ⋅ (t − t 7 ) i p (t ) = − I 4 + in 2 (12) K Lf 8) Mode 8 [t8, t9] [Fig.3(h)]: During this mode, the primary side powers the load, ip is equal to iLr, as expressed in (12). Aachen, Germany, 2004 C. Conduction Loss in Zero State In zero state, the resonant inductance current is smaller in Tr-lag type converter than Tr-lead type converter, so the conduction loss of the resonant inductance and the primary side is reduced, leading to a higher efficiency. D. Duty Cycle Loss The duty cycle loss is proportional to the time for the resonant inductance current to transit from the positive (or negative) value to the negative (or positive) reflected output filter inductance current. As the initial transition current of resonant inductance is smaller in Tr-lag type converter than the Tr-lead type converter, the duty cycle loss is reduced, so the primary to secondary windings ratio of the transformer can be increased, thus the time of the zero state will be shortened and the primary current is reduced, as a result, the conduction loss in zero state will be further reduced, a higher efficiency can be expected, especially for a wide line range. IV. THE EFFECT OF THE BLOCKING CAPACITOR III. COMPARISON OF TR-LAG TYPE AND TR-LEAD TYPE CONVERTERS According to the above analysis, we can know that Tr-lag type converter can eliminate the voltage oscillation resulted by the reverse recovery of the rectifier diodes, the same as Tr-lead type converter. The difference between the two converters is the turn-off of the leading switches. For the Tr-lead type converter, when the leading switch is turned off, the clamping diode conducts, and the resonant inductance is shorted, its current keeps at I1 until the turn-off of the lagging switch [9, 10]. For the Tr-lag type converter, when the leading switch is turned off, the clamping diode does not conduct, the resonant inductance current equals to the primary current, and they are decaying. A. Achievement of ZVS In Tr-lead type converter, in order to achieve ZVS for the leading switches, it needs enough energy to charge/discharge of the output capacitors of the leading switches and to discharge the junction capacitor of one rectifier diode, and the energy is provided only by the filter inductance. In Tr-lag type converter, in order to achieve ZVS for the leading switches, it needs enough energy to charge/discharge of the output capacitors of the leading switches and discharge part of the junction capacitor of one rectifier diode, and the energy is provided by the filter inductance and the resonant inductance. So it is slightly easier to achieve ZVS for the Tr-lag type converter than the Tr-leading type converter. The resonant inductance provides energy to achieve ZVS for the lagging switches in both converters. When the lagging switch turns off, the resonant inductance current is smaller in the Tr-lag type converter than in the Tr-lead type converter, so the lagging switches are slightly difficult to achieve ZVS in Tr-lag type converter than in the Tr-lead type converter. B. Current of the Clamping Diodes The clamping diodes only conduct once in a switching cycle in Tr-lag type converter, so the current rating of the clamping diodes can be reduced. In practical circuit, the switches in the same leg and their drive circuits can not be well matched, so their conduction time and conduction voltage drop will not be identical, resulting in a dc component in vAB, which probably makes the transformer saturated if the dc component does not effectively blocked. A simply way to prevent the transformer from saturating is to insert a blocking capacitor to the primary side in series with the transformer or the resonant inductance. Introducing the blocking capacitor Cb to the Tr-lead type and the Tr-lag type converters, four converters are obtained, as shown in Fig.5. In Tr-lead type converter, the clamping diodes conduct twice in a switching cycle. One occurs in zero state, both the transformer and the resonant inductance are shorted. The other occurs after the output rectified voltage is clamped, the resonant inductance is shorted. If Cb is in series with the resonant inductance, the dc component across it will result in asymmetry of the resonant inductance current in positive and negative direction when the resonant inductance (including Cb) is shorted (see Fig.6(a)); If Cb is in series with the transformer, the dc component across it will result in asymmetry of the primary current in positive and negative direction when the transformer is shorted (including Cb) (see Fig.6(b)). The asymmetry of ip or iLr will result in asymmetry between the currents of two clamping diodes. In Tr-lag type converter, the clamping diodes only conduct after the output rectified voltage is clamped. At that time, only the resonant inductance is shorted. If Cb is in series with the resonant inductance, the dc component across it will result in asymmetry of the resonant inductance current when the resonant inductance (including Cb) is shorted; If Cb is in series with the transformer, the dc component across it will not result in asymmetry of the primary current because the transformer is not shorted by the clamping diodes. So the best scheme of the four converters is to insert the blocking capacitor into the Tr-lag type converter and it is in series with the transformer, as shown in Fig.5(d). 1479 2004 35th Annual IEEE Power Electronics Specialists Conference D1 D2 C1 D5 Q1 Vin A Lr C * Q3 D3 C3 Q4 D6 CDR1 Tr Lf *D R1 Q2 Cb Tr C2 B D4 * RLd Cf Aachen, Germany, 2004 ip: [10A/div] + Vo _ iLr: [10A/div] DR2 iD5: [10A/div] C4 CDR2 iD6: [10A/div] (a) Tr-lead type (Cb series with Lr) D1 D2 C1 D5 Q1 Vin A * D3 C3 CDR1 *D R1 B Q4 D6 D4 * C4 vAB: [500V/div] Lf Tr Q2 Cb Tr Q3 Lr C C2 RLd Cf + Vo _ vrect: [50V/div] Time: [2us/div] DR2 (a) Tr-lead type (Cb series with Lr) CDR2 ip: [10A/div] (b) Tr-lead type (Cb series with Tr) D1 D2 C1 D5 Q1 Vin Q3 Lr D3 Cb C3 CDR1 *D R1 B * * Tr Q4 D6 Lf Tr Q2 C A C2 D4 C4 RLd Cf iLr: [10A/div] + Vo _ iD5: [10A/div] DR2 iD6: [10A/div] vAB: [500V/div] CDR2 (c) Tr-lag type (Cb series with Lr) D1 C1 Q1 Vin D5 Lr D3 C3 C2 * Tr Cb Q4 D6 vrect: [50V/div] CDR1 Lf Tr *D R1 Q2 C A Q3 D2 B D4 * C4 RLd Cf Time: [2us/div] + Vo _ (b) Tr-lead type (Cb series with Tr) ip: [10A/div] DR2 CDR2 iLr: [10A/div] (d) Tr-lag type (Cb series with Tr) Fig.5 Four converters with the blocking capacitor Lr Cb Cb iD5: [10A/div] iD6: [10A/div] Tr vAB: [500V/div] (a) Cb series with Lr (b) Cb series with Tr Fig.6 Equivalent circuit when the clamping diodes conduct vrect: [50V/div] V. EXPERIMENTAL RESULTS AND DISCUSSION Time: [2us/div] In order to verify the operation principle of the Tr-lag type converter and the effect of the blocking capacitor, a prototype with 28.5V/100A output is built in our lab with the following parameters: − Input voltage: Vin=270V±10%; − Output voltage: Vo=28.5V; − Output current: Io=100A; − Q1(D1&C1) ~ Q4(D4&C4)：APT4012BVR (37A/400V); − Rectifier diodes DR1 and DR2: DSEI2x121-02A; − Clamping diodes D5 and D6: DSEI12-06A; − Resonant inductance: Lr=4uH; − Blocking capacitor: Cb=5uF; − The primary to secondary windings ratio: K=6.5; − Output filter inductance: Lf=3uH; − Output filter capacitor: Cf=2200uF×6; − Switching frequency: fs=100kHz. 1480 (c) Tr-lag type (Cb series with Lr) ip: [10A/div] iLr: [10A/div] iD5: [10A/div] iD6: [10A/div] vAB: [500V/div] vrect: [50V/div] Time: [2us/div] (d) Tr-lag type (Cb series with Tr) Fig.7 Experimental waveforms of ZVS PWM full-bridge 2004 35th Annual IEEE Power Electronics Specialists Conference Tr lag increased because the conduction loss is reduced due to the reduced resonant inductance current. If the line range is wider, the benefits of the reduced duty cycle loss will be presented, and the efficiency will be expected to be further higher in the improved converter. Tr lead Efficiency（%） 94.5 93.5 VI. CONCLUSIONS 92.5 The ZVS PWM full-bridge converter with clamping diodes is improved just by exchanging the position of the transformer and the resonant inductance such that the transformer is connected with the lagging leg. The improved converter keep the advantage of eliminating the voltage oscillation resulted by the reverse recovery of the rectifier diodes, furthermore, it brings the following advantages over the original one: The clamping diodes conduct only once, which reduces their current stress; The resonant inductance current is reduced in zero state, so the conduction loss in zero state is reduced, and as a result, the efficiency is increased. The duty cycle loss is reduced by the reduced resonant inductance current, which is potentially benefit for the efficiency increase. The blocking capacitor can be inserted in series with transformer to prevent the transformer from saturating, without the risk of asymmetry of the primary current or resonant inductance current. The operation principle and the advantages of the improved converter are analyzed in details, and verified by a prototype converter. 91.5 90.5 0 50 100 Output Current（A） (a) At different output current under nominal input voltage Tr lag Tr lead 94.0 Efficiency（%） Aachen, Germany, 2004 93.7 93.4 93.1 92.8 92.5 240 260 280 300 Input Voltage（V） REFERENCES (b) Under different input voltage at full load Fig.8 Measured overall conversion efficiency of ZVS PWM full-bridge converters [1] Fig.7 shows the experimental waveforms of ip, iLr, iD5, iD6, vAB and vrect (from the top to the bottom) of the four converters (in Fig.5) at full load under the nominal input voltage, which illustrates that no voltage oscillation occurs in vrect thanks to the two clamping diodes. The clamping diodes conduct twice in Tr-lead type converter and only once in Tr-lag type converter. iLr in zero state is smaller in Tr-lag type converter than Tr-lead type converter. As shown in Fig.7(a) and (c), when the blocking capacitor is in series with the resonant inductance, the dc component across it results in asymmetry of the resonant inductance current, and as a result, the currents of the two clamping diodes are asymmetrical. Fig.7(b) illustrates that when the blocking capacitor is in series with the transformer in Tr-lead type converter, the primary current is asymmetry, and the currents of the two clamping diodes are asymmetrical accordingly. Fig.7(d) indicates that when the blocking capacitor is in series with the transformer in Tr-lag type converter, the transformer current is symmetrical, and the currents of the two clamping diodes are symmetrical accordingly. So Fig.7 clearly illustrated that the converter in Fig.5(d) is the best scheme. Fig.8 shows that the Tr-lag type converter has a higher efficiency than the Tr-lead type converter. The efficiency is D. M. Sable, and F. C. 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