Semiconductor Engineering
MOS Field-Effect Transistor
Velocity Saturation
Prof. Si-Hyun Park, Dept. of Electronic Eng., Yeungnam Uni.
Semiconductor Engineering
Velocity Saturation
6
8.0x10
𝜇𝑛𝑠 Esat
For silicon
6
𝑣 (cm/s)
6.0x10
𝑣=
6
4.0x10
=
6
2.0x10
𝑣sat
E
1+ sat
E
𝜇𝑛𝑠 E
1+E
E
=
𝑣sat
E
E
Esat
Esat
=
sat
+1
𝜇𝑛𝑠 E,
𝜇𝑛𝑠 Esat ,
𝑣
𝜇𝑛𝑠 ≡ Esat
sat
for E ≪ Esat
for Esat ≪ E
0.0
0
4
1x10
4
2x10
4
4
3x10
4x10
E (V/cm)
In ideal 𝐼𝐷 -𝑉𝐷 model, assume 𝜇 =
𝑣
E
= constant, through channel at least in linear region
𝐼𝑦 = 𝑊𝑄𝑛′ 𝑣𝑛𝑦 = −𝑊𝑄𝑛′ 𝜇𝑛𝑠 E𝑦 = −𝑊𝑄𝑛′ 𝜇𝑛𝑠
𝑉𝐷𝑆
𝐿
= 𝐼𝐷𝑆
𝐼𝐷𝑆 ∝ 𝑉𝐷S in linear region 𝑉𝐷𝑆 ≤ 𝑉𝐺𝑆 − 𝑉𝑇 ,
In real case, for E > Esat even in linear region , 𝜇 =
ex) 𝐿 = 1 μm, 𝑉𝐷S = 1 V
𝐿 < 1 μm, 𝑉𝐷S = 1 V
then E𝑦 =
𝑉𝐷S
𝐿
𝑣
E
→ 0, 𝑣 → 𝑣sat , 𝐼 = 𝑊𝑄𝑛′ 𝑣𝑛𝑦 → 𝐼sat
= 104 V/cm ≅ Esat,n
then E𝑦 > Esat,n ,
𝐼𝐷𝑆 = 𝐼sat even in linear region 𝑉𝐷𝑆 (= 1 V) ≤ 𝑉𝐺𝑆 − 𝑉𝑇 ,
Esat,n ≅ 104 V/cm
Assume piece-wise model for 𝑣,
Semiconductor Engineering
6
For E ≤ Esat
8.0x10
for E ≤ Esat
for Esat ≤ E
6.0x10
′
𝐼𝑦 = −𝑊𝐶𝑜𝑥
𝑉𝐺𝑆 − 𝑉𝑐 − 𝑉𝑇 𝜇𝑛𝑠
6
4.0x10
𝜇𝑛𝑠 E𝑦
𝑣𝑛𝑦 = −
6
2.0x10
In inversion mode (𝑉𝑇 < 𝑉𝐺𝑆 ),
E𝑐 = E𝑦 𝑦 : channel electric field
𝐼𝐷𝑆 = 𝐼𝑦 (𝑦): drain current through channel
𝑉𝑐 = 𝑉𝑦 𝑦 : channel potential to source
𝑑𝑉𝑦 𝑦
𝐼𝑦 = 𝑊𝑄𝑛′ 𝑣𝑛𝑦 →
6
v (cm/s)
𝜇𝑛𝑠 E
,
E
1+
Esat
𝑣=
1
𝑣sat = 𝜇𝑛𝑠 Esat ,
2
0.0
0
4
1x10
4
2x10
E (V/cm)
4
3x10
4
4x10
𝐼𝐷𝑆 1 −
1+
E𝑦.sat
𝑑𝑉𝑐 (𝑦)
𝑑𝑦
𝐼𝐷𝑆 𝐿 + 𝐼𝐷𝑆
−
𝑑𝑉𝑐
E𝑦.sat
E𝑦.sat
′ 𝑊
𝜇𝑛𝑠 𝐶𝑜𝑥
1
1+E
′
𝑄𝑛′ = −𝐶𝑜𝑥
𝑉𝐺𝑆 − 𝑉𝑐 − 𝑉𝑇
𝑉𝐷𝑆
2
𝑑𝑉𝑐 (𝑦)
𝑑𝑦
′
= −𝜇𝑛𝑠 𝑊𝐶𝑜𝑥
𝑉𝐺𝑆 − 𝑉𝑐 − 𝑉𝑇 𝑑𝑉𝑐
′
= 𝜇𝑛𝑠 𝑊𝑧 𝐶𝑜𝑥
𝑦.sat 𝐿
𝐼𝐷𝑆 𝑉𝐷𝑆
𝑑𝑦
𝑉𝑐 𝐿 =0
𝑑𝑉𝑐
𝐼
𝐷𝑆
𝑉𝑐 0 =𝑉𝐷𝑆
E𝑦.sat
𝑉𝐷𝑆
𝐼𝐷𝑆 𝑉𝐷𝑆 =
𝑑𝑉𝑦 (𝑦)
′
= −𝑊𝐶𝑜𝑥
𝑉𝐺𝑆 − 𝑉𝑐 − 𝑉𝑇 𝜇𝑛𝑠
E𝑦.sat
𝐼𝐷𝑆 𝑑𝑦 −𝐼𝐷𝑆
𝑦=𝐿
𝐼 𝑑𝑦
𝑦=0 𝐷𝑆
E𝑦 = −
E𝑦
𝑑𝑦
𝑑𝑉𝑦 𝑦
𝑑𝑦
1−
E𝑦.sat
𝐿
=−
𝑉𝑐 𝐿 =0
𝜇 𝑊 𝐶′
𝑉𝑐 0 =𝑉𝐷𝑆 𝑛 𝑧 𝑜𝑥
𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆 −
𝑉𝐺𝑆 − 𝑉𝑐 − 𝑉𝑇 𝑑𝑉𝑐
2
𝑉𝐷𝑆
2
2
2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆 − 𝑉𝐷𝑆
′
𝜇𝑛𝑠 𝐶𝑜𝑥
𝑊
2
=𝜶
2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆 − 𝑉𝐷𝑆
2
𝐿
𝜶 𝑉𝐷𝑆 ≡
1
𝑉
1+E 𝐷𝑆 𝐿
𝑦.sat
Effect of velocity saturation : reduce 𝐼𝐷 by a factor of
E𝑦.ave ≡
1+
When a large 𝐿 or small 𝑉𝐷𝑆 E𝑦.ave → 0 , it is negligible.
𝑉𝐷𝑆
E𝑦.ave
E𝑦.sat
𝐿
Semiconductor Engineering
𝐼𝐷𝑆 𝑉𝐷𝑆 =
′ 𝑊
𝜇𝑛𝑠 𝐶𝑜𝑥
1
1+E
𝑉𝐷𝑆
2
𝑦.sat 𝐿
ideal case
with velocity saturation
-3
=0
-3
1.2x10
𝑉𝐷𝑆 =𝑉𝐷𝑆.𝑠𝑎𝑡
2
𝑉 −𝑉
1+ 1+2 𝐺𝑆 𝑇
𝑉𝐺𝑆 − 𝑉𝑇
-3
𝐼𝐷S (𝐴)
𝑉𝐷𝑆.𝑠𝑎𝑡 =
2
2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆 − 𝑉𝐷𝑆
1.4x10
𝑑𝐼𝐷 𝑉𝐷𝑆
𝑑𝑉𝐷𝑆
𝐿
E𝑦.sat 𝐿
𝐼𝐷𝑆.𝑠𝑎𝑡 = 𝐼𝐷𝑆 𝑉𝐷𝑆.𝑠𝑎𝑡 =
′ 𝑊
𝜇𝑛𝑠 𝐶𝑜𝑥
2
2
𝐿
𝑉 −𝑉
1+ 1+2 𝐺𝑆 𝑇
𝑉𝐺𝑆 − 𝑉𝑇
2
1.0x10
-4
8.0x10
𝑉𝐺𝑆 = 4.0 V
-4
6.0x10
E𝑦.sat 𝐿
-4
4.0x10
𝑉𝐷𝑆.𝑠𝑎𝑡 = 𝜷 𝑉𝐺𝑆 − 𝑉𝑇
𝐼𝐷𝑆.𝑠𝑎𝑡 =
′ 𝑊
𝜇𝑛𝑠 𝐶𝑜𝑥
2
𝐿
𝑉𝐺𝑆 = 3.0 V
-4
2.0x10
2
𝜷 𝑉𝐺𝑆 − 𝑉𝑇
𝜷(𝑉𝐺𝑆 ) ≡
2
0.0
0
𝑉 −𝑉
1+ 1+2 𝐺𝑆 𝑇
1
2
E𝑦.sat 𝐿
𝜶 𝑉𝐷𝑆 ≡
1.0
𝛽
0.8
3
𝑉𝐷𝑆 (𝑉)
𝜇𝑛𝑠 = 680 cm2 /V−s
′ = 6.9 × 10−8 F ∙ cm−2
𝐶𝑜𝑥
Esat = 104 V/cm
1
𝑉
1+E 𝐷𝑆 𝐿
𝑦.sat
4
𝑉𝐺𝑆 = 2.5 V
5
6
(𝑉𝑇 = 1.5 V)
𝑊 = 15 𝜇m
𝐿 = 2 𝜇m
0.6
𝛼
0.4
𝐼𝐷S 𝑉𝐷𝑆 =
0.2
0.0
0
1
2
3
4
𝑉𝐷𝑆 , 𝑉𝐺𝑆 −𝑉𝑇
5
6
′ 𝑊
𝜇𝑛𝑠 𝐶𝑜𝑥
2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆
2
𝐿
′ 𝑊
2
𝜇𝑛𝑠 𝐶𝑜𝑥
𝜷 𝑉𝐺𝑆 − 𝑉𝑇 ,
2
𝐿
𝜶
2
− 𝑉𝐷𝑆
, 𝑉𝐷𝑆 ≤ 𝜷 𝑉𝐺𝑆 − 𝑉𝑇 , linear
𝜷 𝑉𝐺𝑆 − 𝑉𝑇 ≤ 𝑉𝐷𝑆 , saturation
Assume piece-wise model for 𝑣,
Semiconductor Engineering
6
8.0x10
For E ≥ Esat
for E ≤ Esat
6
6.0x10
for Esat ≤ E
v (cm/s)
𝜇𝑛𝑠 E
,
E
1+
Esat
𝑣=
1
𝑣sat = 𝜇𝑛𝑠 Esat ,
2
′
𝑉𝐺𝑆 − 𝑉𝐷𝑆.sat − 𝑉𝑇
𝐼𝑦 = 𝑊𝑄𝑛′ 𝑣𝑛𝑦 → 𝐼𝑦 (𝑦 = 0) = 𝑊𝐶𝑜𝑥
𝜇 E
2 𝑛𝑠 y.sat
6
4.0x10
1
′
𝑄𝑛′ (𝑦 = 0) = −𝐶𝑜𝑥
𝑉𝐺𝑆 − 𝑉𝐷𝑆.sat − 𝑉𝑇
𝑣𝑛𝑦 = 𝑣𝑛𝑦.sat = − 𝜇𝑛𝑠 Ey.sat
6
2.0x10
In inversion mode (𝑉𝑇 < 𝑉𝐺𝑆 ),
E𝑐 = E𝑦 𝑦 : channel electric field
𝐼𝐷𝑆 = 𝐼𝑦 (𝑦): drain current through channel
𝑉𝑐 = 𝑉𝑦 𝑦 : channel potential to source
1
2
0.0
0
4
1x10
4
2x10
4
3x10
𝐼𝐷𝑆.sat =
4
4x10
′
𝜇𝑛𝑠 𝐶𝑜𝑥
2
E (V/cm)
𝑊 𝑉𝐺𝑆 − 𝑉𝐷𝑆.sat − 𝑉𝑇 Ey.sat
E = Esat
𝐼𝐷𝑆 𝑉𝐷𝑆.sat =
𝐼𝐷𝑆.sat =
1
𝑉
1+ E𝐷𝑆.sat
𝑦.sat 𝐿
1
𝑉
1+ E𝐷𝑆.sat
𝑦.sat 𝐿
′
𝜇𝑛𝑠 𝐶𝑜𝑥
2
′ 𝑊
𝜇𝑛𝑠 𝐶𝑜𝑥
2
𝐿
2
2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆.sat − 𝑉𝐷𝑆.sat
𝑊 𝑉𝐺𝑆 − 𝑉𝐷𝑆.sat − 𝑉𝑇 Ey.sat
2
2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆.sat − 𝑉𝐷𝑆.sat
= 𝑉𝐺𝑆 − 𝑉𝐷𝑆.sat − 𝑉𝑇 Ey.sat 𝐿
2
2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆.sat − 𝑉𝐷𝑆.sat
= 𝑉𝐺𝑆 − 𝑉𝐷𝑆.sat − 𝑉𝑇 E𝑦.sat 𝐿 + 𝑉𝐷𝑆.sat
𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆.sat = 𝑉𝐺𝑆 − 𝑉𝐷𝑆.sat − 𝑉𝑇 E𝑦.sat 𝐿
𝑉𝐺𝑆 − 𝑉𝑇 + E𝑦.sat 𝐿 𝑉𝐷𝑆.sat = 𝑉𝐺𝑆 − 𝑉𝑇 E𝑦.sat 𝐿
1
𝑉𝐷𝑆.sat
1
𝑉𝐷𝑆.sat
=
1
𝑉𝐺𝑆 −𝑉𝑇
+
=
𝑉𝐺𝑆 −𝑉𝑇 +E𝑦.sat 𝐿
𝑉𝐺𝑆 −𝑉𝑇 E𝑦.sat 𝐿
1
E𝑦.sat 𝐿
Semiconductor
Engineering
1
1
1
𝑉𝐷𝑆.sat
=𝑉
𝐺𝑆 −𝑉𝑇
+E
𝐼𝐷𝑆 𝑉𝐷𝑆.sat =
𝑦.sat 𝐿
′ 𝑊
𝜇𝑛𝑠 𝐶𝑜𝑥
1
𝑉
1+ E𝐷𝑆.sat
𝐿
2
𝐿
2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆.sat −
2
𝑉𝐷𝑆.sat
𝐼𝐷𝑆.sat =
Short channel device
E𝑦.sat 𝐿 ≫ 𝑉𝐺𝑆 − 𝑉𝑇
E𝑦.sat 𝐿 ≪ 𝑉𝐺𝑆 − 𝑉𝑇
→ 𝑉𝐷𝑆.sat ≅ 𝑉𝐺𝑆 − 𝑉𝑇
′ 𝑊
𝜇𝑛𝑠 𝐶𝑜𝑥
1
𝑉
1+ E𝐷𝑆.sat
𝐿
2
𝐿
2
2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆.sat − 𝑉𝐷𝑆.sat
𝐼𝐷𝑆.sat =
′
𝜇𝑛𝑠 𝐶𝑜𝑥
𝑦.sat
≅
′
𝜇𝑛𝑠 𝐶𝑜𝑥
𝑊
2
𝐿
𝑉𝐺𝑆 − 𝑉𝑇
𝐼𝐷𝑆.sat ∝ 𝑉𝐺𝑆 − 𝑉𝑇
2
𝑊 𝑉𝐺𝑆 − 𝑉𝐷𝑆.sat − 𝑉𝑇 Ey.sat
𝑦.sat
Long channel device
𝐼𝐷𝑆 𝑉𝐷𝑆.sat =
′
𝜇𝑛𝑠 𝐶𝑜𝑥
≅
2
≅
ideal model like
2
𝑊 𝑉𝐺𝑆 − 𝑉𝐷𝑆.sat − 𝑉𝑇 Ey.sat
′
𝜇𝑛𝑠 𝐶𝑜𝑥
2
′
𝐶𝑜𝑥
𝑊
𝑊 𝑉𝐺𝑆 − E𝑦.sat 𝐿 − 𝑉𝑇 E𝑦.sat
𝑣sat 𝑉𝐺𝑆 − 𝑉𝑇
1
𝑣𝑦.sat = − 𝜇𝑛𝑠 Ey.sat
2
𝐼𝐷𝑆.sat ∝ 𝑉𝐺𝑆 − 𝑉𝑇
𝑉𝐺𝑆 (V)
-4
1.5x10
2
→ 𝑉𝐷𝑆.sat ≅ E𝑦.sat 𝐿
𝐿 = 20 𝜇m
𝑉𝐺𝑆 (V)
-3
2.0x10
4.5
𝐿 = 0.2 𝜇m
-3
4.5
-4
1.0x10
4.0
𝐼𝐷S (𝐴)
𝐼𝐷S (𝐴)
1.5x10
3.5
4.0
-3
1.0x10
3.5
-5
5.0x10
3.0
2.5
0.0
0
1
2
3
𝑉𝐷𝑆 (𝑉)
4
5
6
3.0
-4
5.0x10
2.5
𝜇𝑛𝑠 = 680 cm2 /V−s
′ = 6.9 × 10−8 F ∙ cm−2
𝐶𝑜𝑥
𝑊 = 15 𝜇m
0.0
0
1
2
3
𝑉𝐷𝑆 (𝑉)
4
5
6
Semiconductor Engineering
Pinch-off vs Velocity saturation
 Two mechanisms of 𝐼𝐷𝑆 saturation
- Pinch-off at drain-side for long-channel device
- Velocity saturation for short-channel device
 For short-channel device, velocity saturation occurs earlier than pinch-off
 low 𝑉𝐷𝑆.sat
1
𝑉𝐷𝑆.sat
=𝑉
1
𝐺𝑆 −𝑉𝑇
+E
1
𝑉𝐷𝑆.sat =
𝑦.sat 𝐿
𝑉𝐺𝑆 −𝑉𝑇 E𝑦.sat 𝐿
𝑉𝐺𝑆 −𝑉𝑇 +E𝑦.sat 𝐿
Gate
(Long Channel)
Source
𝑉𝐷𝑆.sat =
Gate
(Short Ch.)
Drain
𝑉𝐺𝑆 − 𝑉𝑇 E𝑦.sat 𝐿
→ 𝑉𝐺𝑆 − 𝑉𝑇
𝑉𝐺𝑆 − 𝑉𝑇 + E𝑦.sat 𝐿
Source
𝑉𝐷𝑆.sat =
Drain
𝑉𝐺𝑆 − 𝑉𝑇 E𝑦.sat 𝐿
→ E𝑦.sat 𝐿
𝑉𝐺𝑆 − 𝑉𝑇 + E𝑦.sat 𝐿