EEL 4783: HDL in Digital System Design
Lecture 3: Logic Design with Behavioral Models
Prof. Mingjie Lin
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HDL Levels
2
An AOI Circuit
3
Behavior Descriptions
4
Modified AOI
5
32-Bit Two-Channel MUX
6
32-Bit Two-Channel MUX
7
Propagation Delay
8
Continuous Assignments
9
Latches and Level-Sensitive Circuits
10
More Complex Latch
11
Cyclic Behavior of Flip-Flops
12
Even More Complex FFs
13
Latch vs.Flip-Flop
14
Final issues
• Please fill out the student info sheet before leaving
• Come by my office hours (right after class)
• Any questions or concerns?
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