Practices for J750 to J750EX
Conversion
Teradyne Internal Use Only
Because
Because technology
technology never
never stops
stops
Validate error
Validate error
– PPMU Issues.
– Patterns issue
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MBG 2
Validation error --- Due to PPMU
PPMU I-Range error after program validation.
> It is caused by difference of Irange between J750Ex and J750.
PPMU Measure
I Range and
Accuracy
50mA
+/- (400uA + 0.2%)
N/A
2mA
+/- (14uA + 0.1%)
2mA
200uA
+/- (1.4uA + 0.2%)
200uA +/- (2.1uA + 0.52%)
20uA
+/- (140nA + 0.2%)
20uA
+/- (160nA + 0.51%) (1ms Integ)
2uA
+/- (28nA + 0.2%)
(2 ms settle)
2uA
+/- (40nA + 1.0%) (10ms Integ)
N/A
200nA +/- (8nA + 1.4 %) (100ms Integ)
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+/- (16uA + 0.58%)
MBG 3
Validation error --- Correlative action
Validation error at PPMU IRange , change to corrective range.
The modification take about 5 minutes
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MBG 4
Validation Error-- The issue is relate to the use of LVM and subroutines
> This issue can be solved by recompiling the pattern file.
The modification take about 5 minutes
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MBG 5
Validate Error-- Due to Timeset not be used in patterns
Got most of timeset mapping errors
>This error caused from JTAG not be used in patterns but be
import to patterns.
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MBG 6
Validate Error ---Corrective action
>Remove Jtag timset from patterns import
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MBG 7
Validate Error ---Max timing cycle
Program Validate error
-
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MBG 8
Validate Error ---Max timing cycle
Program Validate error
According our spec.
Edge range max was 10uS
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MBG 9
Validate Error --- I source and I sink range
Change iSource and iSink value to J750Ex Spec.
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MBG 10
No Validation/Run Time Error But Fail Devices
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MBG 11
Fail device—PPMU range issue
Devices got intermittent failure on PPMU test items.
Test condition : using PPMU to force 0A and measure voltage value.
Changing the IRange from 2mA to 20uA can solve the issue.
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MBG 12
Fail Device Issues --- Frequency Counter issue
The Frequency counter on HSD200 requires a 0->X transition
to close the window, which was not required on HSD100
Totally, there are 3 patterns need to be modified:
idd_f_meas_10ms, idd_f_meas_50ms and fll_noPort.
Example:
clr_flag (cpuA) > FIX1US
> FIX1US
010XX;
010XX;
> FIX1US
> FIX1US
01000;
01000;
> FIX1US
> FIX1US
01000;
01000;
set_cpu(cpuA) > FIX1US
wait1:
010XX;
repeat 9997
010X0;
010XX;
> FIX1US
> FIX1US
01000;
01000;
> FIX1US
> FIX1US
01000;
01000;
set_cpu(cpuA) > FIX1US
wait1:
010XX;
> FIX1US
if (cpuA) jump wait1
010XX;
> FIX1US
> FIX1US
010XX;
010XX;
> FIX1US
010XX;
repeat 9997
> FIX1US
if (cpuA) jump wait1
010XX;
> FIX1US
> FIX1US
010XX;
010XX;
> FIX1US
010XX;
halt
ign
clr_flag (cpuA) > FIX1US
> FIX1US
halt
ign
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MBG 13
Match Loop Issues – Pipeline Length
>It is caused by precondition pattern--idd_allmodes_5xx_v5
>The pattern has a match loop which uses a fixed fail pipe
number for the repeats.
Compatibility
Issue
J750
J750Ex
Implication/Mitigation
FAIL and
COND Pipeline
Depths
34
42 <- this
should be
54
Patterns that hardcode FAIL or COND
pipe depth will require modification.
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Modify the pattern to use
pipe_minus opcode and recompile
the pattern for Digital Instrument
hsd100200.
MBG 14
Match Loop Issues — Corrective Action
// -----------------------------------------------------------------------subr wait_feedback_pulse:
repeat 30, ign > FIX10US
0 1 ---- H -- - ;
set_loopA 65000, ign
> FIX10US
0 1 ---- H -- - ;
ign
> FIX10US
0 1 ---- H -- - ;
m_loop:
ign
> FIX10US
0 1 ---- H -- - ;
ign
> FIX10US
0 1 ---- H -- - ;
ign
> FIX10US
0 1 ---- H -- - ;
if (pass) jump cont, ign
> FIX10US
0 1 ---- H -- - ;
if (fail) jump l1, ign, clr_fail, clr_cond
> FIX10US
l1:
end_loopA m_loop, ign
> FIX10US
timeout:
jump efb
> FIX10US
cont:
pop_loop
> FIX1US
efb:
return
> FIX1US
0 1 ---- H -- - ;
0 1 ---- H -- - ;
0 1 ---- H -- - ;
0 1 ---- X -- - ;
0 1 ---- X -- - ;
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// -----------------------------------------------------------------------subr wait_feedback_pulse:
repeat 50, ign > FIX10US
0 1 ---- H -- - ;
set_loopA 65000, ign
> FIX10US
0 1 ---- H -- - ;
ign
> FIX10US
0 1 ---- H -- - ;
m_loop:
ign
> FIX10US
0 1 ---- H -- - ;
ign
> FIX10US
0 1 ---- H -- - ;
ign
> FIX10US
0 1 ---- H -- - ;
if (pass) jump cont, ign
> FIX10US
0 1 ---- H -- - ;
if (fail) jump l1, ign, clr_fail, clr_cond
> FIX10US
l1:
end_loopA m_loop, ign
> FIX10US
timeout:
jump efb
> FIX10US
cont:
pop_loop
> FIX1US
efb:
return
> FIX1US
MBG 15
0 1 ---- H -- - ;
0 1 ---- H -- - ;
0 1 ---- H -- - ;
0 1 ---- X -- - ;
0 1 ---- X -- - ;
Devices fail on PPMU test item when running without datalog
window
– IG-XL bug cause devices fail
– Sbin245
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MBG 16
Devices fail when running without datalog window
Related test items : PR_pullupx_30_reg and PR_pulldownx_30_reg.
PR_pullupx_30_reg used PPMU to force 0V and measure current.
PR_pulldownx_30_reg used PPMU to force 3V and measure current.
It is a IG-XL bug that cause PR_pulldownx_30_reg still force 0V instead
of 3V when running without datalog window.
Action:
To create a workaround solution
To summit case
To push the bug be fix in P4.Plan to issue P4 in Feb.
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MBG 17
Workaround solution
Used a group pin named as PORT_PINS which include P1_PINS ~ PJ_PINS
Result :
We got all sites BIN1, if used a pin group instead of diffused digital PINS.
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MBG 18
Functional test group fail—Root cause
>It is caused by DC output & capacitance/inductance
different between HSD100 and HSD200
Compatibility Issue
J750
J750Ex
Implication
Device Loading
66 pF typical
60 pF typical
Isink change 0A
to -1mA or -5mA
165 nH typical
150 nH typical
35mA min
±55mA min, ±130mA
Total capacitance on the
path
Device Loading
Total inductance in series
with the path
VIH/VIL DC output Hi
Source/Low Sink
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MBG 19
Functional test group fail(1)—Corrective Action
For hardware spec difference
Modify 0A to -1mA
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MBG 20
VDD Leak End test group fail—Corrective Action
For Look Ahead
Add to Allpins
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MBG 21
VDD Leak End test group fail—Root cause
>The Pindata different test to test.
HSD100 has Look ahead functionality
Compatibility Issue
J750
J750Ex
Implication/
Mitigation
Look ahead functionality
yes
no
Init/Start State
HiZ add allpins
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MBG 22
Pins are not defined in pinmap
Debug to Bin 1
• In IccPreTestFunction, No “RESET_” in the pin map.
– Add Comment Block.
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MBG 23
Pins are not defined in pinmap
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MBG 24
Set Irange to better range
Change the IRange in the Instance.
Orig. setting 100mA
New setting 500uA
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MBG 25
MTO issue
• Highest bit of MTO capture memory is not work
• 32bit DG issue
• MTO capture memory issue
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MBG 26
Highest bit of MTO capture memory is not work
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MBG 27
To modify array depth from 15 to 16
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MBG 28
After modification MTO capture memory work normally
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MBG 29
No more sbin172(AD2) fail
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MBG 30
32 bit DG issue
• Program running error
Fixed :
Create new MTO template
Re-compoled Pattern for mto:dgen_32bit;
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MBG 31
Fail Device Issues --- MTO capture memory issue
Root cause : the usage of MTO is out of specification.
They ran it at 50MHz while it was set up to 25MHz.
Totally, there are 3 patterns need to be modified for AD2 group.
mrepeat 5
> FIX20NS
mrepeat 4
> FIX20NS
end_loopA ad2_conv1_sht0
> FIX20NS
1000X1
1001X1
1; //
1; //
1001X1
1; //
> FIX100NS
end_loopA ad2_conv1_sht0
> FIX100NS
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MBG 32
1000X1
1; //
1001X1
1; //