FQD1N50B / FQU1N50B
May 2000
QFET
TM
FQD1N50B / FQU1N50B
500V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply, power
factor correction, electronic lamp ballast based on half
bridge.
•
•
•
•
•
•
1.1A, 500V, RDS(on) = 9.0Ω @VGS = 10 V
Low gate charge ( typical 4.0 nC)
Low Crss ( typical 3.0 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
!
D
"
! "
"
"
G!
G
S
I-PAK
D-PAK
FQD Series
G D S
FQU Series
!
S
Absolute Maximum Ratings
Symbol
VDSS
ID
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
FQD1N50 / FQU1N50
500
Units
V
1.1
A
- Continuous (TC = 100°C)
IDM
Drain Current
- Pulsed
(Note 1)
0.7
A
4.4
A
VGSS
Gate-Source Voltage
± 30
V
EAS
Single Pulsed Avalanche Energy
(Note 2)
80
mJ
IAR
Avalanche Current
(Note 1)
1.1
A
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C) *
(Note 1)
2.5
4.5
2.5
mJ
V/ns
W
25
0.2
-55 to +150
W
W/°C
°C
300
°C
dv/dt
PD
(Note 3)
Power Dissipation (TC = 25°C)
TJ, TSTG
TL
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
--
Max
5.0
Units
°C/W
RθJA
RθJA
Thermal Resistance, Junction-to-Ambient *
--
50
°C/W
Thermal Resistance, Junction-to-Ambient
--
110
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Rev. A, May 2000
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
500
--
--
V
--
0.5
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
VDS = 500 V, VGS = 0 V
--
--
1
µA
VDS = 400 V, TC = 125°C
--
--
10
µA
Gate-Body Leakage Current, Forward
VGS = 30 V, VDS = 0 V
--
--
100
nA
Gate-Body Leakage Current, Reverse
VGS = -30 V, VDS = 0 V
--
--
-100
nA
VDS = VGS, ID = 250 µA
2.3
3.0
3.7
V
VDS = VGS, ID = 250 mA
3.6
4.3
5.0
V
--
6.8
9.0
Ω
--
0.98
--
S
--
115
150
pF
--
20
30
pF
--
3
4
pF
--
5
20
ns
--
25
60
ns
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 0.55 A
gFS
Forward Transconductance
VDS = 50 V, ID = 0.55 A
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 250 V, ID = 1.4 A,
RG = 25 Ω
(Note 4, 5)
VDS = 400 V, ID = 1.4 A,
VGS = 10 V
(Note 4, 5)
--
8
25
ns
--
20
50
ns
--
4.0
5.5
nC
--
1.1
--
nC
--
2.2
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
1.4
A
ISM
--
--
4.4
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 1.4 A
Drain-Source Diode Forward Voltage
--
--
1.4
V
trr
Reverse Recovery Time
--
170
--
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 1.4 A,
dIF / dt = 100 A/µs
--
0.4
--
µC
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 120mH, IAS = 1.1A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 1.4A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, May 2000
FQD1N50B / FQU1N50B
Electrical Characteristics
0
ID , Drain Current [A]
10
Bottom :
VGS
15 V
10 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
0
10
ID , Drain Current [A]
Top :
-1
10
150℃
-1
25℃
10
-55℃
※ Notes :
1. 250μs Pulse Test
2. TC = 25℃
※ Notes :
1. VDS = 50V
2. 250μs Pulse Test
-2
10
-2
-1
0
10
10
1
10
2
10
4
6
8
10
VGS , Gate-Source Voltage [V]
VDS , Drain-Source Voltage [V]
Figure 1. On-Region Characteristics.
Figure 2. Transfer Characteristics.
24
VGS = 10V
16
0
IDR , Reverse Drain Current [A]
RDS(on) , [ Ω ]
Drain-Source On-Resistance
20
VGS = 20V
12
8
4
※ Note : TJ = 25℃
0
0.0
10
-1
10
150℃
25℃
※ Notes :
1. VGS = 0V
2. 250μs Pulse Test
-2
0.5
1.0
1.5
2.0
2.5
3.0
10
0.2
0.4
0.6
0.8
1.0
1.2
ID , Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage.
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
12
200
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
Crss
VGS, Gate-Source Voltage [V]
Coss
100
50
VDS = 100V
10
VDS = 250V
Ciss
150
Capacitance [pF]
FQD1N50B / FQU1N50B
Typical Characteristics
VDS = 400V
8
6
4
2
※ Notes : ID = 1.4 A
0
-1
10
0
0
10
1
10
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics.
©2000 Fairchild Semiconductor International
0
1
2
3
4
5
QG, Total Gate Charge [nC]
Figure 6. Gate -Charge Characteristics.
Rev. A, May 2000
FQD1N50B / FQU1N50B
Typical Characteristics
(Continued)
3.0
1.2
RDS(ON) , (Normalized)
Drain-Source On-Resistance
BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 μA
0.9
0.8
-100
-50
0
50
100
150
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 0.7 A
0.5
0.0
-100
200
-50
o
0
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs Temperature.
Figure 8. On-Resistance Variation
vs Temperature.
1.2
Operation in This Area
is Limited by R DS(on)
1
10
0.9
ID, Drain Current [A]
ID, Drain Current [A]
100 µs
1 ms
0
10
10 ms
DC
-1
10
※ Notes :
0.6
0.3
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-2
10
0
1
10
2
10
0.0
25
3
10
10
50
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area.
100
125
150
Figure 10. Maximum Drain Current
vs Case Temperature.
D = 0 .5
10
※ N o te s :
1 . Z θ J C ( t ) = 5 . 0 ℃ /W M a x .
2 . D u ty F a c t o r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C( t )
0 .2
0
0 .1
0 .0 5
0 .0 2
10
PDM
0 .0 1
-1
t1
s in g le p u ls e
Z
θ JC
75
TC, Case Temperature [℃]
VDS, Drain-Source Voltage [V]
10
-5
10
-4
10
t2
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve.
©2000 Fairchild Semiconductor International
Rev. A, May 2000
FQD1N50B / FQU1N50B
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
VDS
90%
VDD
VGS
RG
VGS
DUT
10V
10%
td(on)
tr
td(off)
t on
tf
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
BVDSS
IAS
ID
RG
VDD
DUT
10V
tp
©2000 Fairchild Semiconductor International
ID (t)
VDS (t)
VDD
tp
Time
Rev. A, May 2000
FQD1N50B / FQU1N50B
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
I SD
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
©2000 Fairchild Semiconductor International
Rev. A, May 2000
DPAK
MIN0.55
0.91 ±0.10
9.50 ±0.30
0.50 ±0.10
0.76 ±0.10
0.50 ±0.10
1.02 ±0.20
2.30TYP
[2.30±0.20]
(1.00)
(3.05)
(2XR0.25)
(0.10)
2.70 ±0.20
6.10 ±0.20
9.50 ±0.30
6.60 ±0.20
(5.34)
(5.04)
(1.50)
(0.90)
2.30 ±0.20
(0.70)
2.30TYP
[2.30±0.20]
(0.50)
2.30 ±0.10
0.89 ±0.10
MAX0.96
(4.34)
2.70 ±0.20
0.60 ±0.20
(0.50)
6.10 ±0.20
5.34 ±0.30
0.70 ±0.20
6.60 ±0.20
0.80 ±0.20
FQD1N50B / FQU1N50B
Package Dimensions
0.76 ±0.10
©2000 Fairchild Semiconductor International
Rev. A, May 2000
(Continued)
IPAK
2.30 ±0.20
6.60 ±0.20
5.34 ±0.20
0.76 ±0.10
2.30TYP
[2.30±0.20]
©2000 Fairchild Semiconductor International
0.50 ±0.10
16.10 ±0.30
6.10 ±0.20
0.70 ±0.20
(0.50)
9.30 ±0.30
MAX0.96
(4.34)
1.80 ±0.20
0.80 ±0.10
0.60 ±0.20
(0.50)
2.30TYP
[2.30±0.20]
0.50 ±0.10
Rev. A, May 2000
FQD1N50B / FQU1N50B
Package Dimensions
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systems which, (a) are intended for surgical implant into
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support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. F1