PCE3601/201/0/2016 Tutorial Letter 201/0/2016 Power Electronics III (Theory) PCE3601 Year module Department Engineering of Electrical and Mining This tutorial letter contains important information about your module. BARCODE MEMO ASSIGNMENT 2 MEMO Question 1 A power control module of which the schematic is shown below in Figure 1 must be built. The only transformer available with a 10 VA rating steps 220 V down to 12 V at 50 Hz. The secondary of the transformer is represented by V1 in the circuit. D1 D2 12k R1 D3 1k R2 X1 R3 1K R4 48 R5 X2 10k R6 X3 10k C1 R7 V1 D4 C2 D5 150 R8 12k R9 50% 10k VR1 500m R11 Q2 Q1 1K R10 Figure 1 1.1 Identify and write down the labels of the components that form the synchronized ramp generator. (2) R2, R9, R3, C2, Q2, X1 1.2 Calculate the maximum voltage (VDD of OPAMPs) over capacitor C1 taking a diode volt drop to be 0.7 V. (2) VDD 2Vs 3VD 2(12) 3(0,7) 14,9 V 1.3 What is the practically measured amplitude of the zero-crossing-pulses if each of these pulses is 50 us wide? (1) Vz VDD 2 14,9 2 12,9 V 1.4 Calculate the pedestal voltage present at the non-inverting input of OPAMP X1. (2) V R9 12k VDD 14,9 13,75 V R9 R2 12k 1k 1.5 Determine the time that Q2 is OFF in each half cycle. tOFF (2) 1 1 tz 0,05 103 9,95 ms 2f 2 50 1.6 Suggest suitable values for R3 and C2. Show your reasoning and all design calculations to support the values you propose for these two components. (4) C2 must not be too big nor too small, thus select 100 nF. Q C2V I R3 tOFF where I R3 VDD V R3 100 109 13,75 14,9 13,75 9,95 103 R3 R3 8322 1.7 Sketch a functional block diagram of the power control module in Figure 1. 2 (6) PCE3601/201/0/2016 PSU From 12 V 50 Hz source Bridge rectifier Zero Crossing Detector SynchronisedR amp Generator PWM Power Stage [19] Question 2 Four topologies of DC to DC regulators are considered to regulate a load voltage. They are the BUCK, BOOST, BUCK-BOOST and Ҫuk regulators. 2.1 Sketch the basic topology of the BUCK regulator. (1) 2.2 Sketch the basic topology of the BOOST regulator. (1) 2.3 Sketch the basic topology of the BUCK-BOOST regulator. (1) 2.4 Sketch the basic topology of the ҪUK regulator. (1) 3 Figure 2 2.5 If the inductor current is as shown in Figure 2, determine the 2.5.1 average inductor current in a BUCK regulator, I ave Area period 2.5.2 I ave 1 4 40 106 40 106 1 160 106 20 106 180 106 2 4,5 A 40 106 40 106 40 106 average switch current in a BOOST regulator and (2) 1 4 20 106 20 106 1 Area 80 106 10 106 90 106 2 2, 25 A period 40 106 40 106 40 106 2.5.3 I ave (2) average diode current in a BUCK-BOOST regulator. Area period 2.5.4 (2) 1 4 20 106 20 106 1 80 106 10 106 90 106 2 2, 25 A 40 106 40 106 40 106 peak-to-peak current in inductor L1 of a ҪUK regulator. (2) Making the assumption that the ripple current is the most logical interpretation of the question I ripple I peak I min 5 4 1 A 2.6 Referring to Figure 2, determine the voltage over a 1,5 mH inductor between 0 us and 20 μs on the graph, if the circuit is a 2.6.1 BUCK regulator, vL 4 di 54 1,5 103 75 V dt 20 106 0 (2) PCE3601/201/0/2016 2.6.2 vL BUCK-BOOST regulator and (2) di 54 1,5 103 75 V dt 20 106 0 2.6.4 vL (2) di 54 1,5 103 75 V dt 20 106 0 2.6.3 vL BOOST regulator, ҪUK regulator. (2) di 54 1,5 103 75 V dt 20 106 0 2.7 Referring to Figure 2, calculate the voltage over the same inductor between 20 μs and 40 μs if the circuit is a 2.7.1 BUCK regulator, vL di 45 1,5 103 75 V 6 dt 40 10 20 106 2.7.2 vL (2) BUCK-BOOST regulator and (2) di 45 1,5 103 75 V 6 dt 40 10 20 106 2.7.4 vL BOOST regulator, di 45 1,5 103 75 V 6 dt 40 10 20 106 2.7.3 vL (2) ҪUK regulator. (2) di 45 1,5 103 75 V 6 dt 40 10 20 106 2.8 Use the information in the previous two questions to determine the load voltage if the circuit is a 2.8.1 BUCK regulator, Vo vswitchopen L 2.8.2 (2) di 45 1,5 103 75 75 V 6 dt 40 10 20 106 BOOST regulator, (4) Vo vswitchclosed vswitchopen 75 75 150 V 2.8.3 BUCK-BOOST regulator and Vo vswitchopen L 2.8.4 (4) di 45 1,5 103 75 V 6 dt 40 10 20 106 ҪUK regulator. (2) Assuming both inductors have the same current wave shape Vo vswitchopen L di 45 1,5 103 75 V dt 40 106 20 106 5 2.9 Calculate the frequency of operation of the circuits. f (2) 1 1 25 kHZ T 40 106 [42] Question 3 3.1 Explain why power electronic circuits are sources of RFI. (3) Power electronics makes use of static switches (no moving parts). This enables fast switching of the devices from conduction state to blocking state. Further, the devices are capable of conducting high currents and blocking high voltages. This causes rapid change in the current and or voltage levels over components in the circuit. These rapid changes are called transients. When ever a wave form does not conform to a pure sine or cosine wave it contains harmonics. Harmonics are multiples of the switching frequency in the case of power electronics. 3.2 Define EMC. (2) Electromagnetic compatibility (EMC) is defined as the ability of equipment or a system to function satisfactorily in its electromagnetic environment (EME) without introducing intolerable electromagnetic disturbance to any equipment in that environment (even itself). 3.3 How can EMC be achieved in power electronic circuits? (3) Electromagnetic compatibility can be achieved by the following actions: Reduce the level of EMI emissions from the source. Reduce the effectiveness of the path of the EMI. Reduce the susceptibility of the receptor. 3.4 Explain which precautions must be taken to limit RFI in power electronic circuits. Include basic circuits for RFI suppression. (6) Radio frequency interference must be prevented from entering into a circuit and must be eliminated if it enters the circuit. This is done by screening sensitive circuit sections and filtering of RFI frequencies. Harmonics between lines are removed by placing T-, - or L-type filters between the supply and the switching element. Further screening of the circuit and supplying a good earth to the screen prevents radiation of the RFI. L Switch N LOA D Scree n Earth Figure 5.2: Removing harmonics between the lines (symmetrical voltages) A symmetrical voltage (between a line and the earth), is attenuated by introducing a coupled inductor in series between the supply and the circuit. Screening will eliminate any radiation. 6 PCE3601/201/0/2016 Coupled inductor L LOA D 220 V 50 Hz Switch N Earth Figure 5.3: Removing harmonics between line and earth (asymmetrical) LOA D L 2 F Switch N 0,1 F 2 F Earth Figure 5.4: Minimal harmonic reduction scheme Limiting conductive interference is done by using filters and snubbers (transient suppression). Limiting radiative interference is done by using screening, earthing, correct printed circuit board (PCB) techniques and layout as well as other means of preventing the equipment becoming a transmitter of high-frequency emissions. 3.5 Up until 2008 the SABS was the guardian of EMC standards in the SADC region. Which entity is now the guardian according to a law passed in 2008? (1) ICASA [14] Question 4 Consider a DC load of 100 V. Ignore overlap and other losses. 4.1 Determine the harmonic content (up to 24th) of a single-phase bridge rectifier. (6) 4.2 Determine the harmonic content (up to 24th) of a three pulse zig-zag rectifier. (6) 4.3 Determine the harmonic content (up to 24th) of a three-phase bridge rectifier. (6) 4.4 Determine the harmonic content (up to 24th) of a twelve-pulse rectifier. (6) VDC 100 V ,thus 200 an 2 2 cos m m p 1 m 1, 2,3,... 7 [24] 8 PCE3601/201/0/2016 ASSIGNMENT 3 Question 1 1.1 Sketch a diagram to illustrate the concept of dynamic braking of a DC motor. (2) 1.2 Explain the use of dynamic braking of a DC motor. (4) To apply dynamic braking, the armature circuit is isolated from the supply and then a resistor of suitable rating is connected to the armature. The motor now acts as a generator and the kinetic energy of the motor is now dissipated in the resistor. The work done by the motor slows it down rapidly. As the motor speed drops, the braking power also drops. Dynamic braking is also called resistive braking. When the motor stops all the energy has been dissipated and the motor will not reverse. 1.3 Sketch a diagram to illustrate the concept of plugging to rapidly slow down a DC motor. (2) 1.4 Explain the application of plugging on a DC motor. (4) The supply terminals of the motor are swopped while the motor is still running. This causes the back-emf and the supply voltage to add, resulting in a high current and thus high counter torque which slows down the motor rapidly. If this process is not controlled by means of a PWM control scheme, serious damage can be caused to the motor and/or the load. A speed sensor must be used to sense zero speed to prevent reversal of the motor direction. 1.5 Sketch a diagram to illustrate the concept of regenerative braking of a DC motor. (2) 9 1.6 Explain the application of regenerative braking of a DC motor. (4) Regenerative braking implies that the motor is acting as a generator and its kinetic energy is not wasted in a resistor as in dynamic braking, but it is returned to the source. E must be greater than V for regenerative braking to take place. The control of the motor is used to track the back-emf of the motor in such a way that the back-emf is larger than the voltage supplied to the motor to allow power to be transferred from the motor to the supply. The motor is acting as a generator and the motor drive is operating in the inverting mode. This is done by means of phase angle control with 2 . As soon as the motor speed falls too low to provide a voltage E greater than V, dynamic braking ceases and another form of braking must be employed. It is a very energy efficient method of braking but much more sophisticated control circuitry is needed than with the other types of braking. [18] Question 2 Sketch a block diagram of a variable speed drive suitable for controlling the speed of an squirrel cage motor. [9] 10 PCE3601/201/0/2016 Question 3 A circuit of a functional block in the DC Drive Trainer and one cycle of the voltage applied to the transistor is shown in Figure 3. Vzero-cross (V) 20 18 + Vcc = 20 V 1k 10k 16 Vzero-cross iin 14 12 if 10 _ C = 0,1 μF + 8 eout 6 4 9k 2 0 1 2 3 Figure 3 4 5 6 7 8 9 10 t (ms) 3.1 Calculate eout just before application of a zero-crossing pulse. eout 20 (6) 9k (20 18)(9 103 ) 18 18 0 V 9k + 1k 0,1 106 10k 3.2 Sketch one cycle of eout . (4) [10] Question 4 Consider a DC load of 100 V. Ignore overlap and other losses. 4.1 Determine the ripple factor of a single-phase bridge rectifier. (2) 4.2 Determine the ripple factor of a three pulse zig-zag rectifier. (2) 4.3 Determine the ripple factor of a three-phase bridge rectifier. (2) 4.4 Determine the ripple factor of a twelve-pulse rectifier. (2) The ripple factor in the load voltage is defined as the ratio of the total rms value of all the alternating components to the mean value. Thus 11 ripple factor 2 V1rms V22rms Vn2rms Vmean 2 2 Vrms Vmean Vmean where Vrms is the rms value of the total wave. Vmcost Vm 0,866Vm 0,5Vm pt 0 Vrms 1 T 2 1 2 v ( t ) dt Vm cos2 t dpt 0 0 T Vm2 Vm2 2 0 0 1 V2 (1 cos 2t )dpt m 2 2 Vm2 (1 cos 2t )dpt 2 0 (1 cos 2t )dpt p sin 2t pt 2 0 p sin 2 V 1 p 2 p sin Vm 2 2 2 4 p 2 m Vmean VDC pVm sin p Vm sin p p 2-pulse: Vrms Vm 1 p 2 1 2 2 Vm sin Vm sin 2 4 p 2 4 2 2 p 2V 2 Vmean Vm sin Vm sin m p 2 2 2 Vrms Vmean ripple factor Vmean 12 Vm2 4Vm2 2 Vm2 4Vm2 2 2 2Vm 2Vm 2 PCE3601/201/0/2016 Vm 1 2Vm 2 4 2 Vm 1 2Vm 2 4 0,483 2 3-pulse: Vrms Vm 1 p 2 1 3 2 sin Vm sin 0,841Vm 2 4 p 2 4 3 p 3 Vmean Vm sin Vm sin 0,827Vm p 3 2 2 Vrms Vmean ripple factor Vmean 0,841 2 Vm2 0,827 Vm2 2 0,827Vm 0,185 6-pulse: Vrms Vm 1 p 2 1 6 2 sin Vm sin 0,9557Vm 2 4 p 2 4 6 p 6 Vmean Vm sin Vm sin 0,955Vm p 6 2 2 Vrms Vmean ripple factor Vmean 0,9557 2 Vm2 0,955 Vm2 2 0,955Vm 0,038 12-pulse: Vrms Vm 1 p 2 1 12 2 sin Vm sin 0,9887Vm 2 4 p 2 4 12 p 12 Vmean Vm sin Vm sin 0,9886Vm p 12 2 2 Vrms Vmean ripple factor Vmean 0,9887 2 Vm2 0,9886 Vm2 2 0,9886Vm 0,014 [8] Question 5 5.1 What is the cause of overlap in power electronic converters? (1) The source inductance of the supply lines causes a delay in the transfer of current from an outgoing device to an incoming device. This causes two devices to be on simultaneously which in three phase systems boils down to a line to line short of limited duration. 5.2 Sketch a circuit consisting of a Thévenin equivalent of a three phase source supplying a three-pulse controlled rectifier. (3) 13 5.3 Sketch voltage and current waveforms illustrating the effect of overlap in a three-phase half-wave controlled rectifier. (7) 5.4 The short circuit impedance of a transformer feeding a three pulse rectifier is 0,645 Ω per phase. The load current is 40 A feeding into a highly inductive load. The transformer secondary supplies 220 V 50 Hz to the rectifier. The delay angle is 15˚. Determine the angle of overlap in degrees under these circumstances. (5) Note: IL IL 3Vm cos cos 2 L 3Vm cos cos 2 L 40 3(220 2) cos cos 2(0,645) 12 12 2(0,645) 40 cos cos 12 3(220 2) 12 14 PCE3601/201/0/2016 cos 0,966 0,09575 12 cos1 (0,87025) 12 0,2533 rad 0,2533(57,3) 14,5 [16] Question 6 A DC link voltage of 220 V supplies a single pulse-width-modulated single-phase inverter. 6.1 Derive an equation for the r.m.s. voltage over a load in terms of the pulse width δ. (Note: No circuit or wave form = no marks) (7) 6.2 Plot the harmonic profile up to the 5th for a pulse width δ = 72˚. vLoad (t ) n 1,3,5... an cos nt V1 4(220) 1(72) sin 165 V 1 2 V3 4(220) 3(72) sin 89 V 3 2 V5 4(220) 5(72) sin 0 V 5 2 (8) 4E n sin cos nt 2 n 1,3,5 n 15 6.3 Determine the r.m.s. voltage of the fundamental component. V1rms Note: V1max 2 165 2 (2) 117 V vLoad (t ) 4 E n sin cos nt n 2 n 1,3,5 [17] Question 7 7.1 16 Determine the power factor of a single-phase bridge rectifier using the load voltage wave forms as reference. Sketch the wave forms. Assume level load current. (7) PCE3601/201/0/2016 Determine the power factor of a single phase bridge rectifier assuming level load current. Consider the circuit of a single phase bridge rectifier in figure 1. The load is very heavy inductive and thus the assumption of level load current can be made. The wave forms applicable to the output side and input side of the bridge rectifier is shown in figure 2 and figure 3 respectively. The power factor can be determined as follows: Considering the output waveforms: I o I mean I rms and Vmean 2Vm 2 2V where V is the rms value . Considering the input waveforms: 2 I 2 I mean 2 I mean V mean I mean and Vrms m V 2 2 2 2 I rms By definition V I PF mean mean Vrms I rms 2 2V Imean V I mean 2 2 0.9 The current is not displaced with respect to the voltage, thus 1 0 . PF I1rms I rms cos 1 Where I1rms I rms = the input distortion factor The input distortion factor is thus I1rms I rms 7.2 PF PF PF 0.9 cos 1 cos 0 1 Determine the power factor of a three-phase bridge rectifier using the load voltage wave forms as reference. Sketch the wave forms. Assume level load current. (7) 17 Considering the output waveforms: I L I mean I rms and Vmean VDC 3 3Vm 3 3 2V where V is the rms value . Considering the input waveforms: 2 I 2 I mean 2 I mean 2 mean I mean 3 3 3 2 I rms and Vrms Vm V 2 By definition V I PF mean mean 3 Vrms I rms 3 3 2V 3 V Imean 2 I mean 3 3 3 2 3 3 0,955 3 2 The current is not displaced with respect to the voltage, thus 1 0 . PF I1rms I rms cos 1 Where I1rms I rms = the input distortion factor The input distortion factor is thus I1rms I rms PF PF PF 0,955 cos 1 cos 0 1 [14] 18 PCE3601/201/0/2016 Question 8 A three-phase rectifier’s load voltage is shown below in Figure 3. Use a Fourier expansion to determine harmonic content and also to plot the harmonic profile. The ripple frequency is 150 Hz. [8] /100/ VLOAD V 311 0 Figure 3 t VLoad3 pulse 0.827Vm 0.2067Vm cos 3t 0.04726Vm cos 6t 0.0207Vm cos 9t 0.011567Vm cos12t 0.007384Vm cos15t 0.00512Vm cos18t 0.003759Vm cos 21t .... 19 VLoad3 pulse 0.827(311) 0.2067(311) cos 3t 0.04726(311) cos 6t 0.0207(311) cos 9t 0.011567(311) cos12t 0.007384(311) cos15t 0.00512(311) cos18t VLoad3 pulse 20 0.003759(311) cos 21t .... 257 64cos3t 14,7 cos 6t 6, 4cos9t 3,6cos12t 2,3cos15t 1,6cos18t 1,17 cos 21t ....