High-Efficiency Fully- and Highly-Integrated SwitchedCapacitor DC-DC Converters
by
Junmin JIANG
A Thesis Submitted to
The Hong Kong University of Science and Technology
in Partial Fulfillment of the Requirements for
the Degree of Doctor of Philosophy
in the Department of Electronic and Computer Engineering
August 2017, Hong Kong
HKUST Library
Reproduction is prohibited without the author’s prior written consent
To my parents and my wife Xun LIU
iii
ACKNOWLEDGEMENTS
ACKNOWLEDGEMENTS
The four-year Ph.D. study at in HKUST is really a wonderful experience. First of all, I
would like to express my thanks to my supervisor, Professor Wing-Hung Ki. Without his
encouragement, I could not even imagine that I could survive from the Ph.D. study with so
much tension and stress. His valuable spirits deeply influenced my attitudes to my work and
life. He has told us more than once his philosophy is to educate independent and dedicated
researchers. Although the integrated circuit design is full of risk and uncertainty, he never
restricts my imagination and always gives me his full support to explore all the possibilities.
When submitting a paper, I can always get his help. I will never forget every night when he
worked so hard to help me revise the paper and polish the vocabulary in such a detailed way.
He always checks everything to make sure every submitted paper is perfect. All of these make
me believe that joining integrated power electronics laboratory (IPEL) is the best choice for me
to explore my research and the biggest honor of my career life.
I must thank Prof. Yan Lu as well. He is a senior labmate when I first joining IPEL. He
generous gives a lot of help to adapt the new environment so quickly and smoothly. Without
his help, I could never finish my first design in my first-year study. We fight together day and
night to catch to the deadline. He told me many useful design techniques that I cannot learn
from the textbooks. After he joined the University of Macau, we also have a lot of connections.
He provides me a treasure opportunity to visit his lab and use the advanced process. His
guidelines also help quite a lot.
I am sincerely grateful to Prof. Jinyu He, Prof. Philip K. T. Mok, Prof. C. Y. Tsui, Prof.
Lilong Cai serving as my thesis examination committee, and Professor Henry S. H. Chung for
serving as my thesis external examiner, sparing their invaluable time to read my thesis in details,
and giving insightful comments for me to improve my thesis.
I would also thank my former colleagues, Ms. Jie Fu and Prof. Shu Xu. Remember four
years ago, when I was an intern in Philips Research, they encouraged me to work on switchediv
capacitors converters. Without their help and fundamental works, I could initiate my research
topic so quickly. It was an unforgettable experience. I am also grateful to my pervious
supervisor Prof. Lenian He, who bring me into the circuit design area and teach me so much
fundamental knowledge.
I would like to thank IPEL members. We helped each other and shared happiness. They
are Dr. Vincent Chan, Dr. Cheng Huang, Dr. Yonggen Liu, Mr. Xiaohao Hu, Prof. Y. K. Teh,
Dr. Lin Cheng, Dr. Fan Yang, Dr. Min Tan, Dr. Xing Li, Jiawei Zheng, Yuan Gao, Lisong Li,
Langyu Hu, Xiaodong Meng, Yuen Shing Hin, Liusheng Sun, Sijie Pan, Yasu Lu, Qiping Wan,
Xinyuan Ge, Feng Chen, Qin Kuai, Soumitra Pal, Ziang Chen, Dipyaman Modak, Darwin Yim,
and Kwun Hok Chong. Meanwhile, without the technical support from Mr. S. F. Luk, Dr. L. K.
Wong, and Dr. J. C. C. Lo, the ideas can never become be released. I appreciate their help very
much.
I would also like to thank all the IPEL alumnus, who built so good reputation over the
world. They are Prof. Dongsheng Ma, Prof. Alex Leung, Prof. Hoi Lee, Dr. Hylas Lam, Dr.
Scottie Man, and Dr. Feng Su, Dr. Xiaocheng Jing, Prof. Chenchang Zhan, Dr. Edward Ho. I
would like to express my thanks to Dr. Hylas Lam and Mr. Xugang Ke, who recommended me
and brought me the job interview opportunities.
At last, I must express my special thanks to my parents and wife Xun Liu for their
endless love and unconditional supports. Spending Ph.D. life together with my wife is a
tremendous happiness. She is always considerate, and help me release the pressure. Her advice
on writing improved my writing skills.
Looking back to the past, I have met so many crossroads. I appreciate I met so many
mentors and friends who help me point out the right direction, so I can keep moving on without
fear and hesitation. I will never forget their help and will do my best to my future work and life.
v
TABLE OF CONTENTS
TABLE OF CONTENTS
Authorization Page ...................................................................................................................... i
Signature Page ............................................................................................................................ ii
Acknowledgements ................................................................................................................... iv
Table of Contents ...................................................................................................................... vi
List of Figures ........................................................................................................................... ix
List of Tables ............................................................................................................................ xii
Abstract ...................................................................................................................................... 1
Chapter 1 Introduction .............................................................................................................. 3
1.1
Fully-Integrated Power Converters ............................................................................. 3
1.2
Challenges and Motivations ........................................................................................ 5
1.2.1
Topology Generation............................................................................................ 5
1.2.2
Tradeoff between Power Density and Efficiency ................................................ 7
1.2.3
Voltage Ripple and Full Integration ..................................................................... 8
1.3
Thesis Contribution ..................................................................................................... 8
1.3.1
Topology Generation............................................................................................ 9
1.3.2
Efficiency Improvement ....................................................................................... 9
1.3.3
Ripple Reduction ................................................................................................ 10
1.4
Thesis Organization ................................................................................................... 11
1.5
Reference ................................................................................................................... 12
Chapter 2 Review of State-of-The-Art Switched-Capacitor Converters ................................ 14
2.1
Introduction ............................................................................................................... 14
2.2
Capacitors in Special Processes ................................................................................. 14
2.3
Topological Exploration ............................................................................................ 15
2.4
Ripple Reduction ....................................................................................................... 15
2.5
Hybrid Converters ..................................................................................................... 16
2.6
Reference ................................................................................................................... 17
Chapter 3 Analysis of Switched-Capacitor Converters .......................................................... 21
3.1
Introduction ............................................................................................................... 21
3.2
Analysis of Output Voltage and Voltage Ripple ....................................................... 22
vi
3.3
Efficiency of SC Converter ....................................................................................... 26
3.4
Verification By Simulation........................................................................................ 28
3.5
Conclusions ............................................................................................................... 29
3.6
Reference ................................................................................................................... 29
Chapter 4 Fully Integrated 2-/3-Phase SC Converter With Efficiency Improvement ............ 31
4.1
Introduction ............................................................................................................... 31
4.2
Proposed 2-/3-Phase Operation ................................................................................. 32
4.3
Parasitic Insensitive Topology................................................................................... 34
4.4
Measurement Results ................................................................................................. 35
4.5
Conclusions ............................................................................................................... 36
4.6
References ................................................................................................................. 38
Chapter 5 Digital 2-/3-Phase SC Converter With Ripple Reduction ..................................... 40
5.1
Introduction ............................................................................................................... 40
5.2
Topological Analysis ................................................................................................. 42
5.2.1
Theoretical Limit of 2-Phase Operation ............................................................. 42
5.2.2
3-Phase Operation Using Two Flying Capacitors .............................................. 44
5.2.3
Output Impedance Analysis ............................................................................... 46
5.3
Digital Adaptive Ripple Reduction ........................................................................... 49
5.4
Converter Design and Implementation ...................................................................... 53
5.4.1
System Architecture ........................................................................................... 53
5.4.2
Power Stage ........................................................................................................ 54
5.4.3
Adaptive Power Cells for Ripple Reduction ...................................................... 56
5.4.4
Digital Controller ............................................................................................... 58
5.5
Measurement Results ................................................................................................. 59
5.6
Conclusions ............................................................................................................... 64
5.7
References ................................................................................................................. 65
Chapter 6 Dual-Output SC Converter For Multi-Core Application Processor ...................... 69
6.1
Introduction ............................................................................................................... 69
6.2
Dynamic Power-Cell Allocation ............................................................................... 70
6.3
Measurement Results ................................................................................................. 73
6.4
Conclusions ............................................................................................................... 75
6.5
Reference ................................................................................................................... 76
Chapter 7 A Hybrid SC Converter For AMLED Display System ......................................... 77
7.1
Introduction ............................................................................................................... 77
vii
7.2
System Architecture and Design Consideration ........................................................ 78
7.3
Hybrid Voltage Regulator ......................................................................................... 80
7.4
Display Control.......................................................................................................... 82
7.5
AMLED Array and System Integration..................................................................... 83
7.6
Measurement Results ................................................................................................. 85
7.7
Conclusions ............................................................................................................... 86
7.8
Reference ................................................................................................................... 87
Chapter 8 Conclusions And Future Works ............................................................................. 89
8.1
Thesis Conclusions .................................................................................................... 89
8.2
Future Works ............................................................................................................. 91
Appendix List of Publications .................................................................................................. 92
viii
LIST OF FIGURES
LIST OF FIGURES
Fig. 1.1. Operating Example of VCR = 2×. ............................................................................... 6
Fig. 1.2. Output voltage under zero and non-zero loading condition......................................... 6
Fig. 1.3. Circuit model of SC converter. .................................................................................... 6
Fig. 3.1. Step-down SC converter with (N-1)/N configurations: (a) 1/2×, (b) 2/3×, and (c) 3/4×.
.................................................................................................................................................. 22
Fig. 3.2. Dual-branch step-down series-parallel SC converter with voltage conversion ratio (N1)/N........................................................................................................................................... 23
Fig. 3.3. Connection of capacitors in phase 1 and the output voltage waveform. ................... 24
Fig. 3.4. Approximation for capacitors in series. ..................................................................... 24
Fig. 3.5. Simulated and calculated VO vs. IO for different topologies: (a) 1/2×, (b) 2/3×, (c) 3/4×
and, (d) 4/5×. ............................................................................................................................ 28
Fig. 3.6. Simulated and calculated efficiency vs. IO for different topologies: (a) 1/2×, (b) 2/3×,
(c) 3/4× and, (d) 4/5×. .............................................................................................................. 28
Fig. 4.1. Application of wireless powered implantable devices............................................... 31
Fig. 4.2. The architecture of proposed SC converter. .............................................................. 32
Fig. 4.3. Transistor implementation of power stage. ................................................................ 33
Fig. 4.4. P-type MOS capacitors and its equivalent circuit. ..................................................... 33
Fig. 4.5. Operation principles of the summation and subtraction modes. ................................ 34
Fig. 4.6. Measured efficiency at 100MHz and 60MHz of the summation and subtraction modes.
.................................................................................................................................................. 35
Fig. 4.7. Chip micrograph of the 2-/3-phase fully integrated SC converter. ............................ 36
Fig. 4.8. Measured efficiency vs. current loads, input and output voltages. ............................ 37
Fig. 4.9. Measured efficiency versus reverse biased voltages. ................................................ 37
Fig. 5.1. Theoretical efficiency comparison of SC converter with 4 VCRs and 6 VCRs vs. ideal
low dropout regulator. .............................................................................................................. 40
Fig. 5.2. Operating principle of 6-ratio configurations (a) topologies operating in 3-phase mode;
(b) topologies operating in 2-phase mode. ............................................................................... 43
ix
Fig. 5.3 Detailed operation principles of the 3-phase (a) 1/4x mode and (b) 3/4x mode......... 44
Fig. 5.4. Simulated steady state waveforms of output voltage VO and top and bottom plates of
flying capacitors (C1 and C2) with IO = 10mA. ........................................................................ 45
Fig. 5.5. Simulated and calculated output resistance versus frequency and unit width of
transistor under 6 VCRs. .......................................................................................................... 48
Fig. 5.6. Concept of proposed ripple reduction scheme. .......................................................... 49
Fig. 5.7. Timing diagram of operation procedure. ................................................................... 50
Fig. 5.8. The digital logic flow of adaptive ripple reduction. .................................................. 51
Fig. 5.9. The mechanism to respond the transient current. ...................................................... 52
Fig. 5.10. The timing diagram of the design for test (DFT) module. ....................................... 53
Fig. 5.11 System architecture of proposed 2-/3-phase SC converter. ...................................... 54
Fig. 5.12. Configuration of switches and flying capacitors of (a) conventional 2-phase SC
converter; (b) proposed switch reduction scheme for 2-/3-phase SC converter. ..................... 55
Fig. 5.13. Power stage implementation of proposed 2-/3-phase SC converter. ....................... 55
Fig. 5.14. (a) Layout floorplan of power cells and clock buses; (b) Switch logics. ................. 56
Fig. 5.15. Timing diagram of synchronized hysteretic control by using (a) dynamic comparator,
(b) static comparator, and (c) status of each phase. ................................................................. 57
Fig. 5.16. (a) Chip micrograph; (b) layout of synthesized digital controller; and (c) top and
bottom view of PCB for measurement with capacitor array in 0612 packing. ........................ 59
Fig. 5.17. Measured efficiency of the proposed SC converter versus loading current. ........... 60
Fig. 5.18. Measured efficiency of the proposed SC converter versus output voltages. ........... 60
Fig. 5.19. Measured power efficiency versus input voltage..................................................... 61
Fig. 5.20. Measured steady-state waveform of output ripple voltage. ..................................... 62
Fig. 5.21. Measured waveforms of light load ripple reduction under difference VCRs. ......... 62
Fig. 5.22. Measured waveforms of ripple reduction procedure and the outputs of testing data.
.................................................................................................................................................. 63
Fig. 5.23. Measured waveforms of transient response. ............................................................ 63
Fig. 6.1. Strategy of dynamic power-cell allocation and system architecture of proposed dualoutput SC converter. ................................................................................................................. 70
Fig. 6.2. Circuit implementation of dual-path VCO, delay cell of dual-path VCO and power
stage. ......................................................................................................................................... 71
Fig. 6.3. Circuit implementation of frequency comparator, bidirectional shift register and the
timing diagram of frequency comparison. ............................................................................... 72
x
Fig. 6.4. Chip micrograph. ....................................................................................................... 73
Fig. 6.5. Measured waveforms of steady state output voltages, reference tracking and loading
transient response. .................................................................................................................... 74
Fig. 6.6. Measured efficiency versus loading currents with and without dynamic power
allocation. ................................................................................................................................. 75
Fig. 7.1. System architecture of proposed micro display system. ............................................ 79
Fig. 7.2. Schematic of the hybrid voltage regulator. ................................................................ 79
Fig. 7.3. Circuit implementation of power stage in SC converter. ........................................... 80
Fig. 7.4. Floorplan of voltage regulator. .................................................................................. 81
Fig. 7.5. Structure of Pixel Drivers. ......................................................................................... 82
Fig. 7.6. (a) Cross sectional diagram of the LED µ-array with indium bumps; and (b) IV
characteristic of LED pixels. .................................................................................................... 83
Fig. 7.7. (a) SEM of LED µ-array with indium bumps after reflow process; and (b) alignment
of AMLED array and silicon substrate. ................................................................................... 83
Fig. 7.8. Chip micrographs of (a) AMLED array; (b) pixel driver and PMU and (c) integrated
system. ...................................................................................................................................... 84
Fig. 7.9. Measured waveforms of steady-state output voltages. .............................................. 85
Fig. 7.10. Measured efficiency of voltage regulator vs. input voltage. .................................... 85
Fig. 7.11. Source files (top) and its corresponding display images (bottom) shown in the blue
micro display system. ............................................................................................................... 86
xi
LIST OF TABLES
LIST OF TABLES
TABLE 1.1 COMPARISON OF THREE TYPES OF POWER CONVERTERS ............................................ 4
TABLE 3.1 COMPARISON OF SIMULATION AND CALCULATION RESULTS .................................... 29
TABLE 4.1 COMPARISON WITH PRIOR ART. ................................................................................ 38
TABLE 5.1 SUMMARY OF EQUIVALENT OUTPUT IMPEDANCE OF 6 VCRS.................................. 48
TABLE 5.2 CLOCK SELECTION OF THE SWITCH LOGICS WITH VCRS ......................................... 57
TABLE 5.3 PERFORMANCE COMPARISON WITH STATE-OF-THE-ART SC CONVERTER WORKS .. 64
TABLE 6.1 PERFORMANCE COMPARISON WITH START-OF-THE-ART WORKS ............................ 75
xii
ABSTRACT
High-Efficiency Fully- and Highly-Integrated Switched-Capacitor DC-DC Converters
by
Junmin JIANG
Department of Electronic and Computer Engineering
The Hong Kong University of Science and Technology
Abstract
Fully-integrated DC-DC power converters are in great demand for implantable,
wearable and portable devices. Switched-capacitor (SC) converters are good candidates as they
only use capacitors that can be easily built on-chip. However, designing SC converters with
high power density, high efficiency and low voltage ripple is challenging. In this research, a
systematic study of SC DC-DC converters is presented. Design techniques are proposed and
applied to various applications to tackle practical issues.
First, a 2-/3-phase fully-integrated SC DC-DC converter in 65nm bulk-CMOS is
designed for low-power implantable devices. By using 3-phase operation, an additional voltage
conversion ratio (VCR) of 1/4× is realized and improves the efficiency by 14%. A parasitic
insensitive topology is proposed and achieves an efficiency improvement of 11%. Besides, a
charge pump is used to provide high-voltage bias for integrated capacitor that reduces parasitic
and further improves the efficiency by 3%.
Second, to further take advantages of 3-phase topologies, a 2-/3-phase 6-ratio switchedcapacitor DC-DC converter in 0.13 µm bulk CMOS technology is designed. In total, there are
four 2-phase VCRs and two 3-phase VCRs (1/4× and 3/4×). The power efficiency was
improved by as much as 20% compared to 2-phase only topologies. The input voltage range is
1.6 V to 3.3 V, while the output voltage range is 0.5 V to 3 V. A digital ripple reduction scheme
1
is also introduced to reduce the output voltage ripple up to 4 times of the original value at light
load. The converter delivers a maximum power of 250 mW and achieves a peak efficiency of
91%.
Third, a fully integrated dual-output SC converter with dynamic power allocation for
application processors is presented. The power cells can be dynamically allocated according to
the loads, and improves the efficiency by 4.8% than without power-cell allocation. A dual-path
voltage-control oscillator (VCO) that works independently of the power-cell allocation is
proposed to achieve a fast and stable regulation loop. The converter achieved peak efficiency
of 83.3% and maximum combined load-currents of 100mA while maintaining minimized cross
regulation.
Finally, a fully-integrated active matrix light-emitting diode (AMLED) micro display
system is presented. The system consists of 36×64 pixel-drivers encompassed by a fully onchip hybrid voltage regulator built on the same silicon chip, then integrated with the AMLED
array by using the flip-chip bonding technology. No external passive component is needed. The
hybrid voltage regulator consists of a step-up switched-capacitor converter cascaded by a stepdown linear regulator. The hybrid voltage regulator can handle the wide input range of the
lithium-ion battery, and delivers a maximum power of 216 mW with 91% peak efficiency and
78% average efficiency.
2
Chapter 1
INTRODUCTION
1.1
Fully-Integrated Power Converters
With the increasing demand for wearable and implantable devices, system-
miniaturization is now pressing issue. Therefore, in system-level design, fully integrated power
converters are highly desirable because of two main advantages. First, with all the passive and
active components built on silicon chip, a smaller PCB area and footprint can be achieved, and
the complexity system assembly can be reduced. Second, in most cases, a high-quality power
inductor is more expensive than equivalent capacitors when handling the same level of power.
Therefore, if power inductors could be replaced by capacitors, the system cost could be much
reduced. Besides, integrating power converters together with the loads on the same chip can
also improve circuit performance such as load transient responses and dynamic voltage
frequency scaling (DVFS) responses. As the power converter could be placed closer to the load,
the current could be delivered to the loads with lower parasitic resistance, capacitance and
inductance [Lu 2017]. Thus, fully-integrated power converters are attracting more and more
attention in recent years, both in the academia and the industry [Pique 2013], [Sanders 2013].
Many research works have been published on fully-integrated power converters. They
are mostly focusing on three types: linear regulators, switching converters and switchedcapacitor (SC) converters. Linear regulators are the most convenient solution as they only need
transistors, resistors and a few capacitors. They use the power transistor as a tunable resistor to
regulate the output voltage, thus, the power efficiency may be low when the output voltage VO
is much lower than the input voltage VIN. Nowadays, in advanced CMOS technology, the
operating voltage of the core transistors has scaled down to lower than 1V, but the voltage of a
battery (e.g. Lithium-ion battery) still remains higher than 3V. Hence, a high-efficiency DCDC converter has to step down the battery voltage first before using a linear regulator to drive
the load.
3
Switching converters use power inductors and capacitors to transfer power so that the
ideal efficiency can be 100%. This could be a benefit when the power level is high. However,
as a key component, the power inductor is difficult to be implemented on silicon chip. Moreover,
inductors need a magnetic core if high power efficiency and high density are required, and they
could be very bulky and costly. Some fully-integrated buck converters were reported to use
bond-wire based inductors to achieve full integration [Huang 2013 I], [Huang 2013 II].
However, in low-voltage applications, low VO results in low efficiency as the conduction loss
through the resistive current path becomes important. Meanwhile, more and more products
prefer to use advanced packaging techniques such as flip-chip bonding rather than bond-wire
packaging, limiting the applications of bond-wire based inductors.
The switched-capacitor (SC) DC-DC converters rule out the power inductor, and they
only use flying capacitors to transfer power. By using on-chip capacitors, SC converters can be
built fully on-chip for low-power applications. It should also be noted that SC converters can
attain good efficiencies if VOUT is kept close to the predefined ideal output voltages M×VIN,
where M is the voltage conversion ratio (VCR) at zero load current.
For many applications, such as driving a light-emitting-diode (LED) display and
powering up the backlight of a liquid-crystal display (LCD) [Su 2008], a step-up power
converter is needed to provide a voltage higher than the input voltage. Linear regulators cannot
be used, and a boost switching converter requires a power inductor. Alternatively, a step-up SC
converter, often known as a charge pump, is more suitable because step-up function is easily
achieved by re-arranging the flying capacitors with appropriate switches.
The aforementioned advantages and drawbacks of the three power converters are
summarized in Table 1.1. In summary, in low and moderate power level applications, switchedcapacitor (SC) converter is a good candidate due to its feasibility of on-chip integration,
TABLE 1.1 COMPARISON OF THREE TYPES OF POWER CONVERTERS
Power Converters
Integration Efficiency Step-up Function
Linear Regulators
√
×
×
Switching Converters
×
√
√
Switched Capacitor (SC) Converters
√
–
√
4
capability of step-up conversion and moderate to good power efficiency.
1.2
Challenges and Motivations
Although SC converters have a lot of advantages, designing fully- or highly-integrated
SC converters still faces many challenges. First, the power efficiency of an SC converter with
only a few VCRs is not high over wide input- and output-voltage ranges. Second, an SC
converter has finite output impedance and its maximum deliverable power is determined by the
on-chip capacitance density, and increase in power density will always sacrifice power
efficiency. Hence, in a standard CMOS process of which the capacitance density is low, there
is tradeoff between power density and efficiency, and optimizing this tradeoff could be a
challenge. Third, the output voltage ripple is harmful for noise sensitive devices, and lowering
voltage ripple requires higher switching frequency and larger capacitance. Hence, minimizing
voltage ripple using minimum system resources and cost is also a stringent problem to solve.
1.2.1
Topology Generation
For an SC converter, the VCR is determined by the charging and discharging operations
of the flying capacitors. Fig. 1.1 shows one example. Consider there is one flying capacitor Cf1
and one loading capacitor CL. A 2-phase clock is used to drive the switches. In Ф1, Cf1 is
connected in parallel with the input voltage VIN, and with complete charge transfer, Cf1 will be
charged to VIN. In Ф2, Cf1 is put on top of VIN. The top-plate voltage of Cf1 is then 2VIN. If Cf1
is connected to CL, charge sharing will take place, Cf1 will be partially discharged with that
charge transferred to CL. In every Ф1, Cf1 is replenished by VIN, and in the steady state, CL is
charged to 2VIN. For this topology, the ideal VCR is 2×, meaning that VO=2VIN under the noload condition.
If there is a load current IO at the output, IO will consume the charge stored in CL, so the
average output voltage VO will be lower than the ideal converted voltage M×VIN, where M is
the ideal VCR. Fig. 1.2 shows that when IO is not zero, the actual VO will be lower than M×VIN
by ΔVO. The voltage drop ΔVO can be modeled by an equivalent output impedance RO that
drives the load current IO. Hence, an SC converter can be modeled as an ideal transformer with
turns ratio of 1:M, generating an ideal voltage source of M×VIN that is in series with a finite
output resistance RO, as shown in Fig. 1.3.
5
Fig. 1.1. Operating Example of VCR = 2×.
Fig. 1.2. Output voltage under zero and non-zero loading condition.
RO
1:M
IO
VO
RL
VIN
Fig. 1.3. Circuit model of SC converter.
The output voltage VO can be written as
𝑉𝑉𝑜𝑜 = 𝑀𝑀𝑉𝑉𝐼𝐼𝐼𝐼 − 𝑅𝑅𝑂𝑂 𝐼𝐼𝑂𝑂 ,
(1.1)
and the efficiency could be obtained as,
𝑉𝑉
𝜂𝜂 = 𝑀𝑀𝑉𝑉𝑂𝑂 .
𝐼𝐼𝐼𝐼
(1.2)
With only one VCR (=M), the power efficiency will decrease monotonically when VO
moves away from M×VIN. Therefore, to achieve a high efficiency over wide ranges of input
and/or output voltages, the SC converter should have many VCRs that could be reconfigured
according to the VO/VIN range, so that is always operates with the proper VCR that achieves
the maximum efficiency. However, as presented in [Makowski 1995], more topologies need
6
more flying capacitors and transistors, and combining multiple topologies in one power stage
also increases circuit complexity. To conclude, it is very challenging to attain more VCRs with
fewer flying capacitors and power transistors.
1.2.2
Tradeoff between Power Density and Efficiency
In the previous section, we learn that constructing multiple VCRs (=M) is an effective
method to cater for a smooth averaged efficiency over a range of the input voltage. But at certain
operating point, the equivalent output resistance RO restricts the maximum current that SC
converter could be delivered to the load, and a low RO is preferred to achieve a large power
density. There are three ways to reduce RO, as shown in Fig. 1.2. One factor that affects ΔVO is
the loading current IO. Intuitively, if the flying capacitors and the loading capacitor could be
charged more frequently or have large values, ΔVO and RO can be reduced. The on-resistance
RON of the non-ideal switches also result in conduction loss and voltage drop at VO. In terms of
modeling, RON can be incorporated into RO. Hence, RO is inversely proportional to the capacitor
value CFLY and the switching frequency fSW, and is proportional to the on-resistance of the
switches RON:
1
(1.3)
𝑅𝑅𝑂𝑂 ∝ 𝑅𝑅𝑂𝑂𝑂𝑂
(1.4)
𝑅𝑅𝑂𝑂 ∝ 𝐶𝐶
𝐹𝐹𝐹𝐹𝐹𝐹 𝑓𝑓𝑆𝑆𝑆𝑆
Achieving a low RO is not free: large CFLY and low RON need large silicon area; and
careful tradeoff and optimization have to be considered in practical implementation. Besides
charge redistribution loss and conduction loss, parasitic loss and switching loss become
significant when on-chip capacitors are used. There are three types of on-chip capacitors that
can be used: metal-insulator-metal (MIM) capacitor, metal-oxide-semiconductor (MOS)
capacitor and metal-oxide-metal (MOM) capacitor. The densities of these capacitors are
determined by the process. In general, the MOS capacitor has much higher density than the
other two types of capacitors, and is a good candidate for realizing large CFLY. However, the
MOS capacitor has a larger parasitic capacitance with reference to the substrate (up to 5%), and
results in large parasitic loss. Reducing RON means that power transistors have to be larger and
would occupy more silicon area and increase the switching loss. Switching at a higher fSW also
leads to a larger switching loss.
7
Due to the reasons mentioned above, increasing power density (smaller RO) is always
at the cost of a larger silicon area and/or extra power losses, instigating a tradeoff between
power efficiency and density. Hence, in practical CMOS implementation, optimizing the design
parameters to achieve a maximum product of power density and efficiency is very challenging.
1.2.3
Voltage Ripple and Full Integration
In noise sensitive applications, large ripple voltages on the power rails in general
degrade the performance of the loads. Although this side effect could be tolerated in particular
when the loading is digital circuit and its operation could be programmed to adapt to the ripple
voltage [Zimmer 2015], it may not be feasible for applications other than digital however.
In general, large voltage ripple is caused by excessive charging and discharging of the
loading capacitor. The conventional ways to reduce the voltage ripple are to increase the
switching frequency and the value of the loading capacitor. But both methods will increase the
switching loss and system cost. Multi-phase interleaving is verified to effectively reduce the
output voltage ripple [Le 2011], and a lower voltage ripple requires a larger number of power
cells. However, ripple cancellation needs an accurate clock with no phase mismatch. When the
phase number exceeds 40, clock distribution to each phase may consume large amount of power
and the layout floor-plan becomes complicated. Therefore, one target is to design an
interleaving scheme that could generate power cells as many as possible while keeping a
flexible layout floor-plan as well.
Voltage ripple may also be due to the control method. For a hysteretic controlled SC
converter, because of the intrinsic loop delay, the converter may suffer from large voltage
ripples if the charge delivered to the output is not well controlled. Suppressing this voltage
ripple needs a more intelligent control scheme that requires less system resource such as input
and output capacitance (CIN and COUT), and is challenging.
1.3
Thesis Contribution
The goal of this research is to design and implement high performance switched-
capacitor converters to tackle the practical issues of a variety of applications. Design examples
8
to be employed by implantable devices, energy harvesting sources, application processors in
smart phones and watches, and micro LED display systems are presented. New design
methodology, topologies and control techniques are proposed to improve the performance. The
key research contributions are highlighted below.
1.3.1
Topology Generation
(A)
3-Phase Topologies for Low Voltage Application
A 3-phase SC converter is proposed to generate a VCR of 1/4× by using only two flying
capacitors. Compared with 2-phase operation, one more VCR is generated without using one
more flying capacitor. Higher efficiency can thus be achieved for the low-VCR (VOUT/VIN)
region. Together with the VCR of 1/3x, the proposed SC converter could cover an input voltage
range of 2 V to 2.5 V and a low output voltage range of 0.4 V to 0.7 V. The 3-phase step-down
SC converter was fabricated and measured with good performance.
(B)
Digital 2-/3-Phase 6-Ratio SC Converter
To explore all the possible VCRs of 2-/3-phase operation with only 2 flying capacitors,
a digital 2-/3-phase SC converter is proposed. 6 VCRs are generated and could cover wide input
and output voltage ranges. This technique is especially suitable for SC converters of which
volume is limited by packaging and external components. The existing commercial products
can easily employ this technique without changing any system resources such as packaging and
numbers of pins and external capacitors. Moreover, a full digital design methodology is
employed to enhance compatibility with CMOS processes and reduce design time complexity.
1.3.2
Efficiency Improvement
(A)
Parasitic Insensitive Topology
To minimize the effects on efficiency due to parasitic capacitors of on-chip flying
capacitors, a parasitic insensitive topology is proposed. It operates in a subtraction mode and is
generated by simply changing the polarity of one flying capacitor. Compared with summation
mode topologies, subtraction mode topologies reduce the voltage swing of the bottom-plate
parasitic capacitors, which help reducing the power loss and enhancing overall efficiency. SC
converters with subtraction mode use the same number of flying capacitors and power
9
transistors as those with summation mode, and could provide the same VCR and the same
output resistance as those with summation mode. So it is a very effective method to improve
the efficiency with a minimum system cost.
(B)
High Bias Voltage
A technique of biasing the substrate using high voltage is also proposed to reduce the
parasitic capacitance in the device level. Consider using a P-type MOS capacitor as an on-chip
flying capacitor. The junction capacitance CJ of the body-well diode is the major parasitic
capacitance, and the value of CJ is reversely proportionally to its bias voltage. Now, the body
terminal of this capacitor could be isolated and individually biased by other voltages, and hence
we propose to use a high voltage as the bias to reduce CJ. The measurement results show a 5%
efficiency improvement is achieved.
(C)
Power Resources Allocation
In smart-phone and smart-watch applications, the multi-core application processor
needs many voltage rails for each core and these rails are usually provided by individual power
converters. When the loads of the cores are not balanced, the power efficiency and capacitor
utilization would be low. To increase the utilization of on-chip power resource and the overall
efficiency of all power converters, a single-input dual-output SC converter is proposed. The onchip power resources are merged together and could be dynamically allocated according to the
loading conditions. By doing so, the power and area overhead are reduced. The prototype shows
that the efficiency is improved by 4.8% and the two output voltages could operate with a
minimized cross regulation.
1.3.3
Ripple Reduction
(A)
Digital Ripple Reduction
A digitally controlled ripple reduction scheme is proposed to reduce the output voltage
ripple. As the ripple voltage is caused by intrinsic loop delay and this delay is hard to be
eliminated, modulating the output resistance is an alternative method to suppress over-charging
of the output voltage. The concept of this digital controller is to modulate the output resistance
by monitoring the duration of the discharging phase, so that it could be used under all loading
conditions. The measurement results show an up to 4 times ripple reduction at light loads.
10
(B)
Multiphase Interleaving for AMLED display
Multiphase interleaving is an effective technique to reduce the output voltage ripple and
smooth out the input current. To install multiphase power cells, a converter-ring structure is
analyzed. A distributed ring oscillator is designed not only to reduce the power of the clock tree
but also to increase the flexibility of the layout floor-plan. This structure could find a good
application in an AMLED display system where the micro display panel occupies a large area
in the center. The converter-ring encompasses the micro LED planer array so as to provide the
shortest path to each pixel.
1.4
Thesis Organization
The reset of the thesis is organized as follows.
In Chapter 2, a review of state-of-the-art SC converters on topology, implementation
and design methodology is presented. The advantages and disadvantages of existing published
works are compared.
In Chapter 3, an analysis of step-down SC converters is presented and a mathematical
model that calculates the output voltage and the power efficiency is proposed. This model takes
the top- and bottom-plate parasitic capacitance into consideration and is more suitable for onchip SC converter design. The simulation results corroborate with the calculation results very
well.
In Chapter 4, a 2-/3-phase fully-integrated SC DC-DC converter in a 65nm bulk-CMOS
process with 14% efficiency improvement is proposed. 3-phase operation is utilized for the
1/4× VCR. A parasitic insensitive topology is proposed that achieves 11% efficiency
improvement. Besides, a voltage doubler providing high voltage bias for the integrated
capacitors is implemented to reduce the parasitic and improves the efficiency by 3%. The input
voltage could range from 1.5V to 2.5V, and the output voltage could range from 0.5V t 0.7V,
to cater for energy-efficient digital circuits, and a peak efficiency of 79.5% is achieved.
In Chapter 5, a 2-/3-phase 6-ratio switched-capacitor DC-DC converter is proposed.
11
Two more VCRs are obtained using 3-phase operation than using only the conventional 2-phase
operation. The achieved maximum output voltage range over the input voltage range is up to
75.8%, and the power conversion efficiency was improved by as much as 20% compared to 2phase SC converters. A digital adaptive ripple reduction scheme is also introduced to reduce
the output voltage ripple by as much as 4 times at light load. This converter is implemented in
a 0.13 µm bulk CMOS technology and is capable of operating at a wide input range of 1.6 V to
3.3 V and a wide output range of 0.5 V to 3 V with 91% peak efficiency and delivers a maximum
power of 250 mW.
In Chapter 6, a fully integrated dual-output SC converter with dynamic power-cell
allocation for application processors is presented. The power cells can be dynamically allocated
according to load demands, and improves the efficiency by 4.8% than without allocation. A
dual-path voltage controlled oscillator (VCO) that works independently of power-cell
allocation is proposed to achieve a fast and stable regulation loop. The converter achieves 83.3%
peak efficiency and drives a maximum 100mA load while maintaining minimized cross
regulation.
In Chapter 7, a fully-integrated active matrix light-emitting diode (AMLED) micro
display system is presented. The system consists of a 36 × 64 pixel-drivers encompassed by a
fully on-chip hybrid voltage regulator built on the same silicon chip, then integrated with the
AMLED array by using the flip-chip bonding technology. As such, no external passive
component is needed. The hybrid voltage regulator consists of a step-up switched-capacitor
converter cascaded by a step-down linear regulator. Operating with a wide input range of the
lithium-ion battery (2.7V-4.2V), the voltage regulator delivers a maximum power of 216mW
with 91% peak efficiency and 78% average efficiency.
Finally, in Chapter 8 concluding remarks are drawn and future works are discussed.
1.5
Reference
[Su 2008]
F. Su and W.-H. Ki, “Component-efficient multiphase switched-capacitor
DC-DC converter with configurable conversion ratios for LCD driver
applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 8, pp.
12
753–757, Aug. 2008.
[Le 2011]
H.-P. Le, S. R. Sanders and E. Alon, “Design techniques for fully
integrated switched-capacitor DC-DC converters,” IEEE J. Solid-State
Circuits, vol. 46, no. 9, pp. 2120–2131, Sep. 2011.
[Sanders 2013]
S. R. Sanders, et al., “The road to fully integrated DC-DC conversion via
the switched-capacitor approach,” IEEE Trans. Power Electron., vol. 28,
no. 9, pp. 4146–4155, Sep. 2013.
[Pique 2013]
G. V. Pique, H. J. Bergveld, and E. Alarcon, “Survey and benchmark of
fully integrated switching power converters: switched-capacitor versus
inductive approach,” IEEE Trans. Power Electron., vol. 28, no. 9, pp.
4156–4167, Sep. 2013.
[Huang 2013 I]
C. Huang and P. K. T. Mok, “An 84.7% efficiency 100-MHz package
bondwire-based fully integrated buck converter with precise DCM
operation and enhanced light-load efficiency,” IEEE J. Solid-State Circuits,
vol. 48, no. 11, pp. 2595–2607, Nov. 2013.
[Huang 2013 II]
C. Huang and P. K. T. Mok, “A 100 MHz 82.4% efficiency packagebondwire based four-phase fully-integrated buck converter with flying
capacitor for area reduction,” IEEE J. Solid-State Circuits, vol. 48, no. 12,
pp. 2977–2988, Dec. 2013.
[Zimmer 2015]
B. Zimmer et al., “A RISC-V vector processor with tightly-integrated
switched-capacitor DC-DC converters in 28nm FDSOI,” in Proc. IEEE
Symp. VLSI Circuits, Jun. 2015, pp. 316–317.
[Lu 2017]
Y. Lu, J. Jiang, and W. H. Ki, “A multiphase switched-capacitor DC–DC
converter ring with fast transient response and small ripple,” IEEE J. SolidState Circuits, vol. 52, no. 2, pp. 579–591, Feb. 2017.
13
Chapter 2
REVIEW OF STATE-OF-THE-ART SWITCHED-CAPACITOR CONVERTERS
2.1
Introduction
Switched-capacitor (SC) converters are gaining much popularity in recent years, and
numerous papers have been published. In this chapter, review of the start-of-the-art SC
converters will be presented, and the focus is on solving the challenges mentioned in Section
1.2. The techniques that try to improve the efficiency, power density and reduce voltage ripple
will be introduced.
2.2
Capacitors in Special Processes
Flying capacitors are the key components of on-chip SC converters. In standard bulk-
CMOS processes, capacitors such as MOS, MOM and MIM capacitors have low capacitance
density that leads to low power density. Therefore, increasing capacitance density is the most
straightforward way to improve both power density and efficiency. Instead of using standard
CMOS processes, recent works use special processes to implement high-density capacitors. In
[Chang 2010], [Andersen 2014] and [Andersen 2015], deep-trench capacitors in 45nm SOI and
32nm SOI processes are used. The density of deep-trench capacitors are reported to be
extraordinary high of 200nF/mm2, and it is 10 times higher than that of the MIM capacitor in
bulk CMOS. Hence, peak efficiency of higher than 90% and power density higher than
1W/mm2 are achieved by these works.
Charging and discharging of bottom-plate parasitic capacitance will degrade the power
efficiency. To minimize this parasitic, [El-Damak 2013] used ferro-electric capacitors as flying
capacitors that were built at the very top of the chip. As a consequence, the bottom-plate
parasitic capacitance is much lower than that of the MOS capacitor, and 93% peak efficiency
was reported. [Jain 2014] used high-density MIM capacitors and achieved 84% peak efficiency
at 1.1V output voltage.
14
However, all these methods are very costly and not compatible with bulk-CMOS
processes. They may face difficulties when integrating power converters together with other
circuit blocks of a system-on-chip (SoC).
2.3
Topological Exploration
Commercial products [TI 2002], [LTC 2007] and [TI 2013] with two off-chip flying
capacitors can only realize two to three voltage conversion ratios (VCRs) such as 2/3×, 1/2×
and 1/3×. Restricted VCRs means limited efficiency over a wide range of input and output
voltages and loading currents.
The efficiency could be improved by introducing more VCRs. One concept is cascading
many power stages to achieve many finer VCRs. In [Bang 2016 I], a SAR-like SC converter
with 7-bit resolution was presented and six sub-SC converters were cascaded. The arrangement
of capacitors was improved by a recursive method in [Salem 2014]. In [Salem 2015], a gearboxing technique was introduced and five off-chip capacitors were used to construct four
stacked power stages that realized 24 VCRs. However, due to the theoretical limitation of 2phase operation, increasing VCRs needs more flying capacitors and leads to higher system cost.
Thus, the common drawback of these works is low power density, because too many transistors
are stacked in series that gives a large output resistance. To deliver even medium power, they
usually occupied a large silicon area.
An alternative method to realize more VCRs using the same number of flying capacitors
is to use multi-phase operation, such as 3-phase operation. It has been employed in realizing
step-up VCRs in [Su 2008] and [Karadi 2014] to generate a high output voltage with a very
high VCR. For these designs, many auxiliary bias voltages are required to avoid over-voltage
breakdown. Only one VCR (=6x) is realized in [Karadi 2014], and both the input voltage range
and the output voltage range are limited.
2.4
Ripple Reduction
Large ripple voltages on the power rails in general degrade the performance of noise15
sensitive loads. To reduce the output voltage ripple, multi-phase interleaving techniques have
been investigated [Breussegem 2009], [Somasekhar 2010], [Le 2011] and commonly used in
both step-up and step-down SC converters [Pique 2012], [Bang 2016 II], [Lu 2017]. However,
high-power applications use discrete capacitors, and they cannot be split into smaller capacitors
to realize multi-phase interleaving. Modulating the capacitance [Kudva 2013] could reduce the
ripple voltage by suppressing extra charge being delivered to the outputs, but again this method
is not feasible for discrete capacitors. Analog approaches that tune the on-resistance of switches
[Lee 2007], [Jain 2014] are not preferred for a digitally controlled SC converter. Cascading a
post regulator [Lu 2016], on the other hand, would degrade the overall efficiency.
2.5
Hybrid Converters
Recently, hybrid converters are becoming popular research topics, because they have a
high potential to provide a larger product of power density and conversion efficiency. 3-level
converters employ a flying capacitor to generate three voltage levels for one of the inductor
terminals while the other terminal is fixed at VOUT. Therefore, the voltage across the inductor
is reduced and consequently the inductor current ripple is reduced by a factor of two for the
same switching frequency [Kim 2012], [Liu 2016 I], [Liu 2016 II]. With the same output
voltage ripple requirement of the conventional buck converter, the multi-level converters could
use much smaller passive components such that higher loop bandwidth can be achieved. Thus,
with the advantages of both high loop bandwidth and high power efficiency, multi-level
converters found a very suitable application of envelope-tracking for the supply modulation of
the RF power amplifier [Yousefzadeh 2006], [Liu 2017].
Resonant switched-capacitor converters can also be considered as hybrid converters.
The resonant converter switches at the resonant frequency of the LC resonance tank to generate
a sinusoidal conducting current, which has the smallest root-mean-square (RMS) value
compared with any current with the same average current, and thus increase the efficiency by
reducing the conduction loss of the power switches [Stauth 2012], [Kesarwani 2014], [Schaef
2015]. However, resonant converters suffer from slow transient responses, and have restricted
topologies as each flying capacitor needs one inductor to realize soft switching. More
importantly, the use of inductor increases the difficulty to be fully integrated on silicon,
especially when the topology becomes more complicated and needs more flying components.
16
2.6
Reference
[TI 2002]
“High efficiency, 250mA step-down charge pump,” TPS60500 datasheet,
Taxes Instruments, Feb. 2002.
[Yousefzadeh 2006] V. Yousefzadeh, E. Alarcon, and D. Maksimovic, “Three-level buck
converter for envelope tracking applications,” IEEE Trans. Power
Electron., vol. 21, no. 2, pp. 549–552, Mar. 2006.
[Lee 2007]
H. Lee and P. K. T. Mok, “An SC voltage doubler with pseudo-continuous
output regulation using a three-stage switchable opamp,” IEEE J. SolidState Circuits, vol. 42, no. 6, pp. 1216–1229, Jun. 2007.
[LTC 2007]
“High efficiency inductorless step-down DC/DC converters,” LTC15031.8/LTC1503-2 datasheet, Linear Technology, Aug. 2007.
[Su 2008]
F. Su and W.-H. Ki, "Component-efficient multi-phase switched capacitor
DC-DC converter with configurable conversion ratios for LCD driver
applications," IEEE Trans. Circuit Syst. II, Exp. Briefs, vol. 55, no. 8, pp.
753-757, Aug. 2008.
[Breussegem 2009] T. Breussegem and M. Steyaert, “A 82% efficiency 0.5% ripple 16-phase
fully integrated capacitive voltage doubler,” in Proc. IEEE Symp. VLSI
Circuits, Jun. 2009, pp. 198–199.
[Somasekhar 2010] D. Somasekhar, et al., “Multiphase 1 GHz voltage doubler charge-pump
in 32 nm logic process,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp.
751–758, Apr. 2010.
[Chang 2010]
L. Chang, et al., “A fully-integrated switched-capacitor 2:1 voltage
converter with regulation capability and 90% efficiency at 2.3A/mm2,” in
Proc. IEEE Symp. VLSI Circuits, Jun. 2010, pp. 55–56.
[Le 2011]
H.-P. Le, S. R. Sanders and E. Alon, “Design techniques for fully
integrated switched-capacitor DC-DC converters,” IEEE J. Solid-State
Circuits, vol. 46, no. 9, pp. 2120–2131, Sep. 2011.
[Kim 2012]
W. Kim, D. Brooks, and G.-Y. Wei, “A fully-integrated 3-level DC-DC
converter for nanosecond-scale DVFS,” IEEE J. Solid-State Circuits, vol.
47, no. 1, pp. 206–219, Jan. 2012.
17
[Pique 2012]
G. V. Piqué, “A 41-phase switched-capacitor power converter with 3.8mV
output ripple and 81% efficiency in baseline 90nm CMOS,” in Proc. IEEE
Int. Solid-State Circuits Conf, Feb. 2012, pp. 98–100.
[Stauth 2012]
J. T. Stauth, M. D. Seeman, and K. Kesarwani, “A resonant switchedcapacitor IC and embedded system for sub-module photovoltaic power
management,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3043–3054,
Dec. 2012.
[El-Damak 2013]
D. El-Damak, S. Bandyopadhyay, and A. P. Chandrakasan, “A 93%
efficiency reconfigurable switched-capacitor DC-DC converter using onchip ferroelectric capacitors,” in Proc. IEEE Int. Solid-State Circuits Conf,
Feb. 2013, pp. 374–375.
[TI 2013]
“High efficiency switched capacitor step-down DC/DC regulator with
sleep mode,” LM2770 datasheet, Texas Instrument, May. 2013.
[Kudva 2013]
S. S. Kudva and R. Harjani, “Fully integrated capacitive DC-DC converter
with all-digital ripple mitigation technique,” IEEE J. Solid-State Circuits,
vol. 48, no. 8, pp. 1910–1920, Aug. 2013.
[Andersen 2014]
T. Andersen et al., “A sub-ns response on-chip switched-capacitor DC-DC
voltage regulator delivering 3.7W/mm2 at 90% efficiency using deeptrench capacitors in 32nm SOI CMOS,” in Proc. IEEE Int. Solid- State
Circuits Conf., Feb. 2014, pp. 90–91.
[Karadi 2014]
R. Karadi and G. V. Pique, “4.8 3-phase 6/1 switched-capacitor DC-DC
boost converter providing 16V at 7mA and 70.3% efficiency in 1.1mm3,”
in Proc. IEEE Solid-State Circuits Conf., Feb. 2014, pp. 92–93.
[Kesarwani 2014]
K. Kesarwani, R. Sangwan, and J. T. Stauth, “A 2-phase resonant
switched-capacitor converter delivering 4.3W at 0.6W/mm2 with 85%
efficiency,” in Proc. IEEE Intl. Solid-State Circuits Conf., Feb. 2014, pp.
86–87.
[Jain 2014]
R. Jain et al., “A 0.45-1 V fully-integrated distributed switched capacitor
DC-DC converter with high density MIM capacitor in 22 nm tri-gate
CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 917–927, Apr.
2014.
[Jain 2014]
R. Jain, et al., “Conductance modulation techniques in switched-capacitor
DC-DC converter for maximum-efficiency tracking and ripple mitigation
18
in 22nm Tri-gate CMOS,” in Proc. IEEE Custom Integrated Circuits Conf.,
Sep. 2014, pp. 1–4.
[Salem 2014]
L. G. Salem and P. P. Mercier, “A recursive switched-capacitor DC-DC
converter achieving 2N-1 ratios with high efficiency over a wide output
voltage range,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2773–
2787, Dec. 2014.
[Andersen 2015]
T. Andersen et al., “A feedforward controlled on-chip switched-capacitor
voltage regulator delivering 10W in 32nm SOI CMOS,” in Proc. IEEE Int.
Solid-State Circuits Conf., Feb. 2015, pp. 362–363.
[Salem 2015]
L. Salem and P. Mercier, “A battery-connected 24-ratio switched capacitor
PMIC achieving 95.5%-efficiency,” in Proc. IEEE Symp. VLSI Circuits,
Jun. 2015, pp. 340–341.
[Schaef 2015]
C. Schaef and J. T. Stauth, “A 3-phase resonant switched capacitor
converter delivering 7.7 W at 85% efficiency using 1.1 nH PCB trace
inductors,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 2861–2869,
Dec. 2015.
[Lu 2016]
Y. Lu, W.-H. Ki and C. P. Yue, “An NMOS-LDO regulated switchedcapacitor DC-DC converter with fast response adaptive phase digital
control,” IEEE Trans. Power Electron., vol. 31, no. 2, pp. 1294–1303, Feb.
2016.
[Bang 2016 I]
S. Bang, D. Blaauw, and D. Sylvester, “A successive-approximation
switched-capacitor DC–DC converter with resolution of for a wide range
of input and output voltages,” IEEE J. Solid-State Circuits, vol. 51, no. 2,
pp. 543–556, Feb. 2016.
[Bang 2016 II]
S. Bang, J. Seo, L. Chang, D. Blaauw and D. Sylvester, “A low ripple
switched-capacitor voltage regulator using flying capacitance dithering,”
IEEE J. Solid-State Circuits, vol. 51, no. 4, pp. 919–929, Apr. 2016.
[Liu 2016 I]
X. Liu, P. K. T. Mok, J. Jiang, and W.-H. Ki, “Analysis and design
considerations of integrated 3-level buck converters,” IEEE Trans.
Circuits Syst. I, vol. 63 no. 5, pp. 671-682, May 2016.
[Liu 2016 II]
X. Liu, C. Huang, P. K. T. Mok “A 50MHz 5V 3W 90% efficiency 3-level
buck converter with real-time calibration and wide output range for fastDVS in 65nm CMOS,” IEEE Symp. VLSI Circuits, Jun. 2016, pp. 1-2.
19
[Liu 2017]
X. Liu, et al., “A 2.4V 23.9dBm 35.7%-PAE -32.1dBc-ACLR LTE20MHz envelope-shaping-and-tracking system with a multiloopcontrolled AC-coupling supply modulator and a mode-switching PA”, in
Proc. IEEE Intl. Solid-State Circuits Conf., Feb. 2017, pp. 38-39.
[Lu 2017]
Y. Lu, J. Jiang and W.-H. Ki, “A multiphase switched-capacitor DC-DC
converter Ring with fast transient response and small ripple,” IEEE J.
Solid-State Circuits, vol. 52, no. 2, pp. 579–591, Feb. 2017.
20
Chapter 3
ANALYSIS OF SWITCHED-CAPACITOR CONVERTERS
3.1
Introduction
Step-down switched-capacitor (SC) converters are gaining popularity because they can
be built fully on-chip. In advanced CMOS technologies, switching at frequencies in the range
of tens to hundreds of megahertz could achieve high power density and small output ripple.
Some capacitors can be implemented using MOS capacitors that have large parasitic
capacitance coupled to the substrate. As parasitic loss will reduce the overall efficiency, its
effect has to be taken into account.
There are only a handful of papers that analyze step-down SC converters. In [Seeman
2008] an analysis focusing on the output impedance is proposed to predict the current capability
in terms of topology, switching frequency, values of flying capacitors, turn-on resistance of
switches, etc. [Henry 2011] uses state-space modeling to predict the equivalent resistance.
These methods precisely model the intrinsic loss of SC converters; however, effects of parasitic
capacitors are not included, making these methods not adequate for fully on-chip
implementation. In [Ki 2012], step-up SC converters are analyzed using charge balance law
(QBL). The derivations are complicated, but they could be simplified by using first-order
approximations while maintaining high accuracy. This method could be extended to analyze
step-down SC converters as well.
Among various step-down topologies, conversion ratios with (N-1)/N, such as 1/2×,
2/3×, 4/5× etc., are most common ones. SC converters with 1/2×, 2/3× [4] and 4/5× [5] are
designed to cover a large input voltage range and enhance the overall efficiency. Fig. 3.1 shows
21
Fig. 3.1. Step-down SC converter with (N-1)/N configurations: (a) 1/2×, (b) 2/3×, and (c)
3/4×.
some of the schemes of commonly used series-parallel (N-1)/N SC converters with voltage
conversion ratios (a) 1/2×, (b) 2/3× and (c) 3/4×, respectively.
In this chapter, a theoretical analysis of 2-phase step-down SC converters is presented,
which is especially suitable for SC converters with voltage conversion ratios of (N-1)/N. For
each flying capacitor, both the top-plate and bottom-plate parasitic capacitors are included. In
Section 3.2, the analysis of dual-branch SC converters is conducted based on QBL. Derivations
of the output voltage are presented. In Section 3.3, efficiencies of SC converters are calculated
and the optimization points are identified. In Section 3.4, accuracy of the analysis is
demonstrated by simulation results. Finally, concluding remarks are drawn in Section 3.5.
3.2
Analysis of Output Voltage and Voltage Ripple
Fig. 3.2 shows a series-parallel step-down SC converter with the voltage conversion
ratio (N-1)/N if the loading current IO is zero. The dual-branch configuration is considered to
22
Fig. 3.2. Dual-branch step-down series-parallel SC converter with voltage conversion ratio
(N-1)/N.
simplify the analysis, because the output voltage assumes only two values instead of four as in
a single-branch one. This converter consists of 2(N-1) flying capacitors C1a, C1b to CN-1a, CN-1b,
the loading capacitor CL and switches. Switches are turned on and off at the switching frequency
fSW in two non-overlapping phases (Ф1 and Ф2). For on-chip implementation, each flying
capacitor C has a top-plate parasitic capacitor αC and a bottom-plate parasitic capacitor βC
coupled to ground.
Calculation of the output voltage VO is based on QBL, which dictates that the sum of
all charges leaving a node for any instance of charge transfer is equal to zero. Fig. 3.3 shows
the connections of the capacitors and the voltage waveform of VO at the charging phase of
Branch A (Ф1), which is the same as the discharging phase of Branch B. By assuming complete
charge transfer [Ki 2012], at the beginning of Ф1, charge redistribution with ideal switches
makes VO across CL jumps up to VO1 instantly, and CL is discharged by the load current IO
towards VO2 in the rest of the half period (Ф1). Because of its symmetrical structure, the
discharging phase of Branch A (Ф2) is the same as the charging phase of Branch B, and the
whole process repeats.
As shown in Fig. 3.3, the flying capacitors of Branch A are in parallel and those of
Branch B are in series. For N capacitors connected in series to VO, there are N+1 QBL equations
23
Fig. 3.3. Connection of capacitors in phase 1 and the output voltage waveform.
Fig. 3.4. Approximation for capacitors in series.
to be solved to compute all node voltages. The equations become intractable and deem nonpractical. Hence, approximations should be made to reduce the complexity.
Fig. 3.4 illustrates how the capacitors in series are approximated by an equivalent
capacitor CSERIES. For simplicity, we assume that all flying capacitors are equal to C1. We
further assume that all parasitic capacitors except the one connected to VO could be ignored,
and this point will be justified by an equivalent capacitor CSERIES. For simplicity, we assume
that all flying capacitors are equal to C1. We further assume that all parasitic capacitors except
the one connected to VO could be ignored, and this point will be justified by simulation results
24
later. Therefore, we have
1
(3.1)
𝐶𝐶𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 ≈ 𝑁𝑁−1 𝐶𝐶1
If higher accuracy is needed, first-order approximation could be invoked, and
𝐶𝐶𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆,1 ≈
(𝑁𝑁−1)𝑁𝑁
(𝛼𝛼+𝛽𝛽)+1
2
𝑁𝑁(𝑁𝑁−1)(𝑁𝑁+1)
(𝛼𝛼+𝛽𝛽)+𝑁𝑁
6
(3.2)
𝐶𝐶1
With reference to Fig. 3.3, the QBL equation at the output node VO is given by
𝛼𝛼𝐶𝐶1 𝑉𝑉𝐷𝐷𝐷𝐷 + 𝐶𝐶1 (𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑂𝑂2 ) + 𝐶𝐶𝐿𝐿 𝑉𝑉𝑂𝑂2 − 𝐶𝐶1 𝑉𝑉𝑂𝑂2 + 𝛽𝛽𝐶𝐶1
𝐶𝐶
𝑁𝑁 − 2
𝑉𝑉𝑂𝑂2
2
1
= 𝑉𝑉𝑂𝑂1 �𝛼𝛼𝐶𝐶1 + 𝑁𝑁−1
+ 𝐶𝐶𝐿𝐿 + (𝑁𝑁 − 1)𝛽𝛽𝛽𝛽1 � − (𝑁𝑁 − 1)𝐶𝐶1 (𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑂𝑂1 ) (3.3)
In the discharging phase, all the capacitors directly connected to VO are discharged by the load
current IO:
𝐼𝐼 𝑇𝑇
𝑂𝑂
𝑉𝑉𝑂𝑂2 = 𝑉𝑉𝑂𝑂1 − 2𝐶𝐶
(3.4)
𝑇𝑇
where
𝐶𝐶𝑇𝑇 = (𝑁𝑁 − 1)(1 + 𝛽𝛽)𝐶𝐶1 + 𝐶𝐶𝐿𝐿 + 𝛼𝛼𝐶𝐶1 + 𝐶𝐶𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆
(3.5)
From (3.3) and (3.4), VO1 and VO2 could be calculated as
𝑉𝑉𝑂𝑂1 = 𝑀𝑀 × 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑅𝑅𝑂𝑂 𝐼𝐼𝑂𝑂
𝑁𝑁−1
(3.6)
𝑉𝑉𝑂𝑂2 = 𝑀𝑀 × 𝑉𝑉𝐷𝐷𝐷𝐷 − 2𝑁𝑁2 𝜏𝜏 × 𝐶𝐶
Where
1+ (𝑁𝑁−1)
𝑁𝑁−1
× � 2 + 𝑁𝑁�
𝑀𝑀 = 1 − 𝑁𝑁 ×
and
𝜏𝜏 = 1 +
𝛽𝛽
2
1
𝑁𝑁
𝛽𝛽
𝜏𝜏
𝐼𝐼𝑂𝑂
1 𝑓𝑓𝑆𝑆𝑆𝑆
𝛼𝛼
(3.7)
(3.8)
(3.9)
The parameter τ is a coefficient related to parasitic capacitors, and in the ideal case, α =
β = 0, giving τ = 1, and M is the voltage conversion ratio that is ideally equal to (N-1)/N. If α
and β are larger than 0, then τ > 1, and M is lower than (N-1)/N. With CL assigned as µC1, the
output resistance of the SC converter is given by
𝑅𝑅𝑂𝑂1 =
(𝑁𝑁−1)(𝑁𝑁𝑁𝑁−2𝛽𝛽+2µ−4)
4𝑁𝑁 2 𝜏𝜏𝐶𝐶𝑇𝑇 𝑓𝑓𝑆𝑆𝑆𝑆
25
, 𝐶𝐶𝐿𝐿 = µ𝐶𝐶1
(3.10)
Thus, the output voltage is the average of (3.6) and (3.7) and yields
(3.11)
𝑉𝑉𝑂𝑂 = 𝑀𝑀 × 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑅𝑅𝑂𝑂 𝐼𝐼𝑂𝑂
with
𝑅𝑅𝑂𝑂 =
2𝑁𝑁 2 +(𝑁𝑁−1)(2𝛼𝛼−4𝛽𝛽+4µ+3𝛽𝛽𝛽𝛽−8)
(3.12)
4𝑁𝑁 2 𝜏𝜏𝐶𝐶𝑇𝑇 𝑓𝑓𝑆𝑆𝑆𝑆
The voltage ripple is
Δ𝑉𝑉𝑂𝑂 =
3.3
(𝑁𝑁−1)(𝛽𝛽𝛽𝛽+2𝛼𝛼)+2𝑁𝑁 2
8𝑁𝑁 2 𝜏𝜏
× 𝐶𝐶
𝐼𝐼𝑂𝑂
(3.13)
𝑇𝑇 𝑓𝑓𝑆𝑆𝑆𝑆
Efficiency of SC Converter
To calculate the efficiency of a step-down SC converter, we need to tabulate the total
charge from the power supply. In half a cycle, the energy from the power supply is composed
of two parts. (1) E1: The energy that is delivered to the positive plates of C1a and αC1a when
they are charged. (2) E2: The energy supplied to C1a when its negative plate is discharged. Since
the operation of the flying capacitors is complementary in the next half cycle, the total energy
is double of E1 and E2:
EIN = 2(E1 + E2 ) .
(3.14)
First, with reference to Fig. 3.3, C1a and αC1a are discharged to VO2. The positive plates
of C1a and αC1a are charged to VDD, after charge redistribution, they are discharged to (VDD –
VO1). The extra charge ΔQ1 supplied by the power supply is:
𝑁𝑁
∑𝑖𝑖∈𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝐶𝐶𝑖𝑖 𝑉𝑉𝑖𝑖 + αC1 VO2 + ΔQ1
2
= (N − 1)C1 (VDD − VO1 ) + (N − 1)αC1 VDD .
(3.15)
Using the approximation of (3.1) and that
we have
𝑁𝑁
(3.16)
𝛼𝛼𝐶𝐶1 𝑉𝑉𝑂𝑂2 ≈ 𝛼𝛼𝐶𝐶1 𝑁𝑁−1 𝑉𝑉𝐷𝐷𝐷𝐷
𝑁𝑁
Δ𝑄𝑄1 ≈ (𝑁𝑁 − 1)𝐶𝐶1 (𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑂𝑂1 ) − 𝐶𝐶1 𝑉𝑉𝑂𝑂2 + 𝑁𝑁−1 𝛼𝛼𝐶𝐶1 𝑉𝑉𝐷𝐷𝐷𝐷 .
26
(3.17)
In the discharging phase, the negative plates of C1 to CN-1 provide the output current.
The charge ΔQ2 supplied by the power supply is:
(𝑁𝑁 − 1)𝐶𝐶1 (𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑂𝑂1 ) + Δ𝑄𝑄2 = (𝑁𝑁 − 1)𝐶𝐶1 (𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑂𝑂2 ).
(3.18)
The total charge in one switching cycle is thus
Δ𝑄𝑄𝑡𝑡𝑡𝑡𝑡𝑡 = 2(Δ𝑄𝑄1 + Δ𝑄𝑄2 ) = 2(𝑁𝑁 − 1)𝐶𝐶1 (𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑂𝑂2 ) − 2𝐶𝐶1 𝑉𝑉𝑂𝑂2 + (𝑁𝑁 − 1)𝛼𝛼𝐶𝐶1 𝑉𝑉𝐷𝐷𝐷𝐷 . (3.19)
From (3.7) and that E = VDDΔQtot we have
𝐸𝐸𝐼𝐼𝐼𝐼 = 2𝑉𝑉𝐷𝐷𝐷𝐷 𝐶𝐶1 �(𝑁𝑁 − 1)(𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑂𝑂2 ) − 𝑉𝑉𝑂𝑂2 + (𝑁𝑁 − 1)𝛼𝛼
=
1
2
2
𝛽𝛽�𝑁𝑁−2+ �+𝛼𝛼(𝑁𝑁−1− + 2 )
𝑁𝑁
𝑁𝑁 𝑁𝑁
2
𝐶𝐶1 𝑉𝑉𝐷𝐷𝐷𝐷
𝜏𝜏
The efficiency η is given by
𝜂𝜂 =
𝑉𝑉𝑂𝑂 𝐼𝐼𝑂𝑂 𝑇𝑇
𝐸𝐸𝐼𝐼𝐼𝐼
𝑁𝑁−1 𝑉𝑉𝐷𝐷𝐷𝐷 𝐼𝐼𝑂𝑂
+
𝑁𝑁𝑁𝑁
𝑓𝑓𝑆𝑆𝑆𝑆
.
𝑉𝑉𝐷𝐷𝐷𝐷
�
2𝜏𝜏
.
(3.20)
(3.21)
From (3.20), the efficiency could be derived as:
𝑉𝑉𝑂𝑂 𝐼𝐼𝑂𝑂
𝜂𝜂 = 𝜏𝜏 𝜆𝜆𝑉𝑉 2
(3.22)
𝐷𝐷𝐷𝐷 +𝑀𝑀0 𝑉𝑉𝐷𝐷𝐷𝐷 𝐼𝐼𝑂𝑂
with
1
2
2
𝜆𝜆 = �𝛽𝛽 �𝑁𝑁 − 2 + 𝑁𝑁� + 𝛼𝛼(𝑁𝑁 − 1 − 𝑁𝑁 + 𝑁𝑁2 )� 𝑓𝑓𝑆𝑆𝑆𝑆 𝐶𝐶1
𝑀𝑀0 =
𝑁𝑁−1
𝑁𝑁
.
The maximum efficiency is obtained by finding the point where dη/dδ = 0 (δ = VO /
VDD). Eq. (3.22) could be rewritten as:
𝜂𝜂 = 𝜏𝜏
𝛿𝛿
(3.23)
𝜆𝜆𝑅𝑅𝑂𝑂
+𝑀𝑀0
𝑀𝑀0 −𝛿𝛿
The optimized voltage conversion ratio Mopt is:
δopt =
And the maximum efficiency is
𝑉𝑉𝑜𝑜,𝑜𝑜𝑜𝑜𝑜𝑜
𝑉𝑉𝐷𝐷𝐷𝐷
𝜆𝜆𝑅𝑅𝑂𝑂
= 𝑀𝑀0 +
𝑀𝑀0
𝛾𝛾 = �𝑀𝑀02 𝜆𝜆𝑅𝑅0 + 𝜆𝜆2 𝑅𝑅02.
𝜂𝜂𝑀𝑀𝑀𝑀𝑀𝑀 = 𝜏𝜏 �1 −
𝜆𝜆𝑅𝑅𝑂𝑂
The corresponding output voltage and current are
−
𝛾𝛾
𝑉𝑉𝑜𝑜,𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉𝐷𝐷𝐷𝐷 �𝑀𝑀0 +
𝐼𝐼𝑜𝑜,𝑜𝑜𝑜𝑜𝑜𝑜 =
𝑉𝑉𝐷𝐷𝐷𝐷 (𝛾𝛾−𝜆𝜆𝑅𝑅𝑂𝑂 )
𝑀𝑀0 𝑅𝑅𝑂𝑂
27
.
𝛾𝛾
− 𝑀𝑀
0
(𝜆𝜆𝑅𝑅𝑂𝑂 +𝛾𝛾)2
𝜆𝜆𝑅𝑅𝑂𝑂
𝑀𝑀0
𝑀𝑀02 𝛾𝛾
𝛾𝛾
(3.24)
�
− 𝑀𝑀 �
0
(3.25)
(3.26)
(3.27)
3.4
Verification By Simulation
To verify the accuracy of the proposed model, we conduct simulations of four topologies
(N=2, 3, 4 and 5) with flying capacitor C1 = 100pF, loading capacitor CL = 200pF and switching
frequency fSW = 100MHz. The load current ranges from 1µA to 60mA. Fig. 3.5 shows the
output voltages generated by the analysis and by simulation. The parasitic parameters are
chosen as (α = 0; β = 0), (α = 1%; β = 3%) and (α = 1%; β = 5%). Simulation results show that
the output voltage and the equivalent resistance match well with analysis results and the errors
Fig. 3.5. Simulated and calculated VO vs. IO for different topologies: (a) 1/2×, (b) 2/3×, (c)
3/4× and, (d) 4/5×.
Fig. 3.6. Simulated and calculated efficiency vs. IO for different topologies: (a) 1/2×, (b) 2/3×,
(c) 3/4× and, (d) 4/5×.
28
TABLE 3.1 COMPARISON OF SIMULATION AND CALCULATION RESULTS
are less than 0.7%.
Fig. 3.6 shows the efficiencies by simulation and calculation. The predicted
optimization points are close to the simulated ones. Table 3.1 summarizes the simulation result
and the calculation result for the worst of the three cases (α = 1%; β = 5%). The errors of the
output voltage and maximum efficiency are within 0.7% and 3%. The error of the efficiency is
caused by over-counting the parasitic loss due to the series approximation. If the first-order
approximation (3.2) is used, the accuracy of efficiency can be much higher.
3.5
Conclusions
This chapter analyzes the behavior of 2-phase on-chip step down switched-capacitor
DC-DC converters and presents a unified model that covers voltage conversion ratios of (N1)/N. Parasitic capacitors of both the top- and bottom-plate of each flying capacitor are
considered for better accuracy. The simulation results match well with the analytic results from
the model.
3.6
Reference
[Seeman 2008]
M. Seeman and S. Sanders, “Analysis and optimization of switched
capacitor DC-DC converters,” IEEE Trans. Power Electron., vol. 23, no.
2, pp. 841–851, 2008.
[Henry 2011]
J. Henry and J. Kimball, “Practical performance analysis of complex
switched-capacitor converters,” IEEE Trans. Power Electron., vol. 26, no.
1, pp. 127–136, Jan. 2011.
29
[Ki 2012]
W.-H. Ki, Y. Lu, F. Su, and C.-Y. Tsui, “Analysis and design strategy of
on-chip charge pumps for micro-power energy harvesting applications,”
in VLSI-SoC, Jan. 2012, no. 379, pp. 158–186.
[Pique 2012]
G. Pique, “A 41-phase switched-capacitor power converter with 3.8mV
output ripple and 81% efficiency in baseline 90nm CMOS,” in Proc. IEEE
Int. Solid-State Circuits Conf., Feb. 2012, pp. 98–100.
[Jain 2014]
R. Jain, et al., “A 0.45-1 V fully-integrated distributed switched capacitor
DC–DC converter with high density MIM capacitor in 22 nm tri-gate
CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 917–927, Apr.
2014.
30
Chapter 4
FULLY INTEGRATED 2-/3-PHASE SC CONVERTER WITH EFFICIENCY IMPROVEMENT
4.1
Introduction
For implantable devices, achieving fully integration and low power consumption are
always highly desirable. Reducing the supply voltage of digital circuits to sub- or near-threshold
region minimizes the dynamic power consumption and achieves a better efficiency [Wang
2005]. It is widely used in energy-efficient applications, and is especially beneficial for
wirelessly powered devices such as wearable electronics, biomedical implants and smart sensor
networks that have long standby times and going battery-less is highly desirable. As shown in
Fig. 4.1, for a typical wireless power transmission system, there is a gap between the high
voltage of the rectified VIN (> 2V) and the low supply voltage VDD (< 700 mV) for the energyefficient digital circuits.
To bridge this voltage gap without sacrificing compact size, fully-integrated power
converters with a low voltage conversion ratio (VCR = VOUT/VIN) and high efficiency are
needed. For linear regulators, the efficiency decreases significantly when VCR is low. Fullyintegrated buck converters can achieve high current density [Huang 2013]. However, a low
VCR results in low efficiency as the conduction loss through the resistive current path becomes
important [Huang 2013]. Hence, in this low power application, fully-integrated switchedcapacitor (SC) power converters are good alternatives that can achieve high efficiency at low
VCR.
Fig. 4.1. Application of wireless powered implantable devices.
31
In this chapter, a fully-integrated 2-/3-phase reconfigurable step-down SC converter
with an output voltage range of 0.4 V to 0.7 V and an input voltage range of 1.5 V to 2.5 V is
proposed. The power stage only consists of 2 flying capacitors and 8 switches (Fig. 4.2). For
VIN < 2 V, the converter operates in 2-phase mode (VCR=1/3×); for high VIN (2 – 2.5 V), it
operates in 3-phase mode (VCR = 1/4x). The 1/4x topology is very similar to the 1/3 topology,
and no additional flying capacitor is needed. Thus, the efficiency at low output voltage is
improved.
4.2
Proposed 2-/3-Phase Operation
For a bulk-CMOS process, MOS capacitors have the highest capacitance density but
also have large parasitic that reduce the overall efficiency. Effective alternatives have been
reported, such as using ferroelectric capacitors [El-Damak 2013] or high density MIM
capacitors [Jain 2014]. However, special processes are required. In our proposed SC converter,
two approaches are suggested to reduce parasitic loss: (1) a built-in voltage doubler that
provides high N-well bias voltage for P-type MOS capacitors is used to reduce the N-well
parasitic capacitance; and (2) a parasitic-insensitive connection of capacitors is adopted that
could reduce the parasitic loss to one-fourth of conventional configuration. Consequently, this
design shows a 14% improvement in the peak efficiency.
The SC converter architecture is shown in Fig. 4.2. In order to reduce the output voltage
ripple while maintaining high efficiency, 9 interleaving cells are connected in parallel. Each
Fig. 4.2. The architecture of proposed SC converter.
32
Fig. 4.3. Transistor implementation of power stage.
Fig. 4.4. P-type MOS capacitors and its equivalent circuit.
cell is composed of a dual-branch power stage, 2-/3-phase clock generator, logic cells and local
deadtime drivers. To avoid phase mismatches due to long-distance clock distribution and
process variations, a local deadtime scheme is proposed to uphold the break-before-make
mechanism even at very high switching frequency. This scheme is easily extended to have more
interleaving cells without increasing the circuitry complexity. Two voltage domains, VL = 1.2
V and VH = VIN - 1.2 V, are used to tackle breakdown issue and to minimize the switching loss.
In particular, a voltage doubler that uses thick-oxide transistors is built to provide higher voltage
biases for integrated capacitors with reduced parasitic junction capacitances.
Fig. 4.3 shows the transistor implementation of the power stage. Flying capacitors C1 and
C2 are stacked with on-chip MIM, MOM and MOS capacitors in a vertical hierarchy, and
33
Fig. 4.5. Operation principles of the summation and subtraction modes.
achieves a capacitance density of ~15fF/μm2. Parasitics of MOS capacitors are dominated by
the channel capacitance CC and the well junction capacitance CW. They can be reduced by using
P-type MOS capacitors with deep N-well isolation. As shown in the equivalent circuit in Fig.
4.4, CC is shorted by resistors RW and RC and is almost eliminated. As CW is inversely
proportional to its bias voltage, the deep N-well is connected to the output of the built-in voltage
doubler. The doubler does not need to provide current, and it is very low power and area
efficient (50 μm × 100μm).
4.3
Parasitic Insensitive Topology
Fig. 4.5 shows two 1/3x configurations. In the summation mode, C1 and C2 are
connected in series in phase 1, the voltages VC1 (=1/3 VIN) and VC2 (=1/3 VIN) have the same
polarity and summed. The negative-plate of C1 is charged to 2/3 VIN and discharged to ground
in every cycle. The parasitic loss is significant especially when switching at high frequency. In
the subtraction mode, C1 and C2 are first charged to 1/3 VIN and 2/3 VIN in phase 1, respectively;
in phase 2, C1 reverses its polarity and connects to C2 in series, producing an output voltage of
1/3 VIN. Note that in every cycle, the negative-plate of C1 only switches between 1/3 VIN and
ground. As switching loss is given by CV2f, this parasitic loss in Cp1 is reduced to 1/4 of that of
the summation mode. To summarize, subtraction mode operation is more parasitic insensitive.
To verify the above qualitative analysis, both the summation mode and the subtraction
mode are implemented using the same circuit parameters for fair comparison. The measured
efficiency at various current densities with 60MHz and 100MHz operations with VIN = 2 V,
34
Fig. 4.6. Measured efficiency at 100MHz and 60MHz of the summation and subtraction
modes.
VOUT ≈ 0.6 V are shown in Fig. 4.6. The enhancement in the peak efficiency is 11.8 % and it
can even be larger in light load conditions.
4.4
Measurement Results
The proposed 2-/3-phase SC converter was fabricated in a 65nm CMOS process to
validate the above concepts, and it occupied an area of 500μm × 850μm (0.23mm2 active area).
The chip micrograph is shown in Fig. 4.7, including the comparative work for two 1/3x
topologies. Fig. 4.8 shows the measured efficiency in the 1/3x and 1/4x modes with respect to
the current density, the input and the output voltages. The results with built-in doubler enabled
(Vbias=5V) or disabled (Vbias=2V) are shown for comparison. The converter achieves peak
power efficiencies of 79.5% in 1/3x mode and 69% in 1/4x mode at 56mA/mm2. In enabling
the voltage doubler, the efficiency is increased by ~3%. Fig. 4.9 shows the conversion
efficiency versus the reverse-bias voltage generated by the built-in voltage doubler for the
integrated capacitors at current densities of 56 and 109mA/mm2, respectively. Compared to
directly biasing the capacitors by VDD, the efficiency improvement is ~3% by using of 2.5V I/O
devices. If 3.3V I/O devices are available, the enhancement could reach 4.5% at Vbias=6.6V.
35
Fig. 4.7. Chip micrograph of the 2-/3-phase fully integrated SC converter.
Table 4.1 is the comparison of recent fully-integrated power management ICs in
standard bulk-CMOS that have sub-/near-threshold output voltage range (VOUT < 700 mV).
4.5
Conclusions
This chapter discusses the design of SC converters with low voltage conversion ratio
(e.g. 2.5V to 0.5V). By introducing the 3-phase mode and the parasitic insensitive topology
with built-in doubler for CW reduction, the proposed SC converter achieves an overall 14%
efficiency improvement and shows the highest efficiency at the sub-/near-threshold region
36
Fig. 4.8. Measured efficiency vs. current loads, input and output voltages.
Fig. 4.9. Measured efficiency versus reverse biased voltages.
reported to date without using advanced processes or sacrificing the current density.
37
TABLE 4.1 COMPARISON WITH PRIOR ART.
4.6
References
[Wang 2005]
A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor
using a minimum energy design methodology,” IEEE J. Solid-State
Circuits, vol. 40, no. 1, pp. 310–319, Jan. 2005.
[El-Damak 2013]
D. El-Damak, S. Bandyopadhyay, and A. P. Chandrakasan, “A 93%
efficiency reconfigurable switched-capacitor DC-DC converter using onchip ferroelectric capacitors,” in Proc. IEEE Int. Solid-State Circuits Conf,
Feb. 2013, pp. 374–375.
[Kudva 2013]
S. S. Kudva and R. Harjani, “Fully integrated capacitive DC-DC converter
with all-digital ripple mitigation technique,” IEEE J. Solid-State Circuits,
vol. 48, no. 8, pp. 1910–1920, Aug. 2013.
[Huang 2013]
C. Huang and P. K. T. Mok, “An 84.7% efficiency 100-MHz package
bondwire-based fully integrated buck converter with precise DCM
operation and enhanced light-load efficiency,” IEEE J. Solid-State Circuits,
vol. 48, no. 11, pp. 2595–2607, Nov. 2013.
[Jain 2014]
R. Jain, et al., “A 0.45-1 V fully-integrated distributed switched capacitor
DC-DC converter with high density MIM capacitor in 22 nm tri-gate
38
CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 917–927, Apr.
2014.
39
Chapter 5
DIGITAL 2-/3-PHASE SC CONVERTER WITH RIPPLE REDUCTION
5.1
Introduction
The rising market of internet-of-everything (IoE) and wearable devices has great
demands for power management ICs. Some of the applications are powered by harvested energy
such as photovoltaic, piezoelectric, thermoelectric and RF sources [Liu 2015]. A highefficiency power converter is usually needed to regulate the harvester’s source voltage. For
low-power applications ranging from 10 mW to 250 mW, very small capacitors and integrated
capacitor array of multi-layer ceramic capacitors with very small footprint can be used; and in
handling the same power, the cost of ceramic capacitors is lower than a power inductor. Hence,
switched-capacitor (SC) power converters are preferred over inductor-based switching
converters as they do not need bulky and costly power inductors.
Fig. 5.1. Theoretical efficiency comparison of SC converter with 4 VCRs and 6 VCRs vs.
ideal low dropout regulator.
40
Fully-integrated SC converters with on-chip capacitors are becoming popular in recent
years. However, SC converters using on-chip capacitors have two limitations. First, standard
bulk CMOS processes have low capacitance density and hence low energy density, limiting the
power density of SC converters [Le 2013], [Butzen 2016]. Special technologies and processing
steps have been developed to increase the capacitance density by using exotic capacitor
technologies such as deep-trench capacitors and ferro-electric capacitors [El-Damak 2013] at
an increased processing cost. Second, the core transistors of an advanced process such as sub65nm CMOS cannot handle high input voltage directly, and stacking techniques with auxiliary
rails [Meyvaert 2015], I/O devices [Sarafianos 2015], or some designated voltage conversion
ratios (VCRs) [Le 2013], [Meyvaert 2015], [Ng 2012] may have to be used. For an energy
harvesting system, the source voltage could vary drastically according to environmental
conditions [Ramadass 2011], and a power converter with a wide source voltage range is needed.
To address the above concerns, we proposed a switched-capacitor converter that uses an offchip integrated capacitor array that only requires small area and cost overhead to handle wide
voltage range, deliver moderately high power and reduce the system cost [Jiang 2016].
The design of SC converters with off-chip capacitors faces two major challenges. Firstly,
the power conversion efficiency (PCE) is related to the number of voltage conversion ratios
(VCRs). Fig. 5.1 shows the theoretical efficiency of an SC converter with four or six VCRs
versus that of an ideal low dropout regulator. With two extra VCRs (3/4x and 1/4x), the
efficiency at certain VIN can be improved by around 20%. Thus, to obtain a high overall
efficiency, many VCRs are needed. In [Salem 2015], a gear train topology was investigated and
five off-chip capacitors were used to construct four stacked power stages that realize 24 VCRs.
However, the increased output impedance due to stacking too many transistors in series limits
the load current capability. Moreover, 2-phase operation restricts the number of VCRs that
could be realized. Now, one off-chip flying capacitor needs two IC pins, and more VCRs need
more flying capacitors that increase both the volume and the cost. Hence, commercial products
usually use two flying capacitors to minimize the pin count and only have two to three VCRs
such as 2/3x, 1/2x and 1/3x [LTC 2007], [TI 2013], [TI 2002]. Consequently, the challenge is
to realize more VCRs with fewer flying capacitors.
Secondly, large ripple voltages on the power rails in general degrade the performance
41
of noise-sensitive loads. Although this side effect could be cancelled in particular when the
loading is digital circuit and its behavior could be programmed to adapt to the ripple voltage
[Zimmer 2015], however, it may not be feasible for applications other than digital. To reduce
the voltage ripple, multi-phase interleaving techniques have been investigated [Breussegem
2009], [Somasekhar 2010], [Le 2011] and commonly used in both step-up and step-down SC
converters [Pique 2012], [Lu 2017], [Bang 2016]. However, high-power applications use
discrete capacitors, and they cannot be split into smaller capacitors to realize multi-phase
interleaving. Modulating the capacitance [Kudva 2013] could reduce the ripple voltage by
suppressing extra charge being delivered to the outputs, but again this method is not feasible
for discrete capacitors. Analog approaches that tune the on-resistance of switches [Lee 2007],
[Jain 2014] are not preferred for a digitally controlled SC converter. Cascading a post regulator
[Lu 2016], on the other hand would degrade the overall efficiency.
To tackle the above two issues, this chapter proposes a digital 2-/3-phase SC converter
with improved efficiency and reduced voltage ripple over wide input and output voltage ranges.
The paper is organized as follows. Section 5.2 discusses the principle of 2-/3-phase operation
and analyses the performance. Section 5.3 introduces the scheme of digital ripple voltage
reduction. Section 5.4 presents the design of the proposed SC converter, including its
architecture, design considerations and circuit implementation. Measurement results are shown
in Section 5.5 and then followed by concluding remarks.
5.2
Topological Analysis
5.2.1
Theoretical Limit of 2-Phase Operation
Most switched-capacitor converters use a 2-phase clock, and the number of VCRs is
limited by the number of flying capacitors [Makowski 1995], [Pique 2013]. For example, with
two flying capacitors the realizable step-down VCRs are only 1x, 2/3x, 1/2x and 1/3x only.
More VCRs need more flying capacitors, at the cost of two pins per capacitor plus more
complicated power-switch configurations, and thus a higher system cost.
42
Fig. 5.2. Operating principle of 6-ratio configurations (a) topologies operating in 3-phase
mode; (b) topologies operating in 2-phase mode.
An alternative method to realize more VCRs using the same number of flying capacitors
is to use multi-phase operation, which has been employed in realizing step-up VCRs [Karadi
2014], [Su 2008] to extend the output voltage to a very high VCR. It was applied to step-down
SC converter in [Jiang 2015] (the designs in Chapter 4) to generate a very low voltage to power
up energy-efficient digital circuits in the sub-threshold region. To add no additional flying
capacitors, 3-phase operation is especially suitable for SC converters whose volumes are limited
by packaging and external components. In this work, we discover more 3-phase topologies and
combine them with those in Chapter 4 to fully utilize the flying capacitors, and achieve a higher
43
Fig. 5.3 Detailed operation principles of the 3-phase (a) 1/4x mode and (b) 3/4x mode.
average efficiency over the input and output voltage ranges.
5.2.2
3-Phase Operation Using Two Flying Capacitors
We propose to use 2 flying capacitors C1 and C2 to generate 6 VCRs. Fig. 5.2 shows the
phase-by-phase connections of C1 and C2 and the load capacitor CL (at VO) by the switches. Fig.
5.2(a) shows how 1/4x and 3/4x are realized using 3-phase operation, and Fig. 5.2(b) shows
how 1/1x, 2/3x, 1/2x and 1/3x are realized using 2-phase operation. By monitoring VO/VIN the
appropriate VCR in maximizing the theoretical PCE will be used. As 2-phase operations are
well known, we mainly focus on 3-phase operations. The ideal VO/VIN at zero load current is
considered. Fig. 5.3(a) shows the case of realizing VCR = 1/4x. In Ф1, C1 and C2 are connected
in series between VIN and VO, and
Ф1 : 𝑉𝑉𝐼𝐼𝐼𝐼 = 𝑉𝑉𝐶𝐶2 + 𝑉𝑉𝐶𝐶1 + 𝑉𝑉𝑂𝑂
(5. 1)
In Ф2, C1 is connected to ground, and the positive nodes of C1 and C2 are connected together
with C2 stacking on top of VO, yielding
44
Ф2 : 𝑉𝑉𝐶𝐶1 − 𝑉𝑉𝐶𝐶2 = 𝑉𝑉𝑂𝑂 .
(5.2)
Ф3 : 𝑉𝑉𝐶𝐶2 = 𝑉𝑉𝑂𝑂
(5.3)
In Ф3, C1 is left floating and C2 is discharged in parallel with CL, and obviously,
By solving (5.1) to (5.3), we obtain that VO = 1/4VIN.
For the 3/4x mode, Ф1 and Ф2 operations are identical to those of the 1/4x mode. In Ф3,
C1 is left floating, and the positive node of C2 connects to VIN and the negative node to VO.
Hence, we have
Ф1 : 𝑉𝑉𝐼𝐼𝐼𝐼 = 𝑉𝑉𝐶𝐶1 − 𝑉𝑉𝐶𝐶2 + 𝑉𝑉𝑂𝑂
(5.4)
Ф3 : 𝑉𝑉𝐼𝐼𝐼𝐼 − 𝑉𝑉𝐶𝐶2 = 𝑉𝑉𝑂𝑂 .
(5.6)
Ф2 : 𝑉𝑉𝐶𝐶2 + 𝑉𝑉𝐶𝐶1 = 𝑉𝑉𝑂𝑂
(5.5)
Solving (5. 4) to (5. 6) gives VO = 3/4VIN. Note that in Ф3, C1 is floating and does not engage
in charge transfer. As large values can be used for the off-chip capacitors, the output impedance
is low even for the floating phase of C1, which will be derived in the following sections.
Charge transfer can be traced by using the charge balance law [Ki 2012]. Let the total
charge delivered to CL (VO) in one cycle be q. In Ф1, C1 and C2 are charged up by VIN and 1/4q
is delivered to VO. In Ф2, C1 discharges the charge of 1/4q to C2 which is then delivered to VO.
In Ф3, C1 is floating with no charge transfer, but for C2, the accumulated 1/2q is discharged to
VO. The ratios of the charge transferred in each element (capacitor or switch) to the total charge
delivered to the output could be used to obtain the topological factors in Section 5.2.3. Fig. 5.4
Fig. 5.4. Simulated steady state waveforms of output voltage VO and top and bottom plates of
flying capacitors (C1 and C2) with IO = 10mA.
45
shows the simulated steady state waveforms of the output voltage and the top- and bottomplate voltages of C1 and C2 when VIN = 3.3 V and IO = 10 mA. The voltage swings show that
the DC voltages across C1 and C2 after balancing are 1/2 VIN and 1/4 VIN, respectively. As a
summary, benefited by 3-phase operations, 6 VCRs are generated by using only 2 flying
capacitors.
5.2.3
Output Impedance Analysis
In order to explore the power losses of all VCRs, in this section we investigate the
charge redistribution loss, the conduction loss and the equivalent output resistance of the 2-/3phase SC converter. In [Seemn 2008], the SC converter could be modeled as an ideal DC
voltage source with a finite output resistance, and a more complete model with multiple
operating phases could be found in [Seeman 2009]. The equivalent output resistance ROUT can
be calculated by combining the slow-switching-limit (SSL) resistance RSSL due to charge
redistribution and the fast-switching-limit (FSL) resistance RFSL due to the switch resistance,
given by
𝑅𝑅𝑂𝑂𝑂𝑂𝑂𝑂 ≈ �𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆 2 + 𝑅𝑅𝐹𝐹𝐹𝐹𝐹𝐹 2
(5.7)
1
(5.8)
𝑅𝑅𝐹𝐹𝐹𝐹𝐹𝐹 = 𝐾𝐾𝑆𝑆 𝑅𝑅𝑂𝑂𝑂𝑂 ,
(5.9)
𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆 = 𝐾𝐾𝐶𝐶 𝐶𝐶
𝑓𝑓𝑓𝑓𝑓𝑓 𝑓𝑓𝑆𝑆𝑆𝑆
where KC and KS are topological factors determined by summing the charge vectors, Cfly is the
value of the flying capacitor, fSW is the switching frequency and RON is the turn-on resistance
of switches.
The topological factors KC and KS can be calculated as [Seeman 2008]:
𝐾𝐾𝐶𝐶 = ∑𝑖𝑖∈𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 ∑𝑛𝑛𝑗𝑗=1
[𝑎𝑎𝑐𝑐,𝑖𝑖 (Ф𝑗𝑗 )]2
𝐾𝐾𝑆𝑆 = ∑𝑖𝑖∈𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠ℎ𝑒𝑒𝑒𝑒 ∑𝑛𝑛𝑗𝑗=1
2
[𝑎𝑎𝑟𝑟,𝑖𝑖 (Ф𝑗𝑗 )]2
𝐷𝐷𝑗𝑗
(5.10)
,
(5.11)
where ac,i(Фj) is the capacitor charge vector of capacitor Ci in phase Фj, and ar,i(Фj) is the switch
charge vector of switch Ri in phase Фj.
Let the duration of each phase be equal, then (5.11) can be reduced to (5.12) for 2-phase
46
VCRs and (5.13) for 3-phase VCRs, respectively:
𝐾𝐾𝑆𝑆,2−𝑝𝑝ℎ𝑎𝑎𝑎𝑎𝑎𝑎 = 2 ∑𝑖𝑖∈𝑠𝑠𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤ℎ𝑒𝑒𝑒𝑒[𝑎𝑎𝑟𝑟,𝑖𝑖 (Ф𝑗𝑗 )]2
(5.12)
𝐾𝐾𝑆𝑆,3−𝑝𝑝ℎ𝑎𝑎𝑎𝑎𝑎𝑎 = 3 ∑𝑖𝑖∈𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠ℎ𝑒𝑒𝑒𝑒[𝑎𝑎𝑟𝑟,𝑖𝑖 (Ф𝑗𝑗 )]2.
(5.13)
Now, charge vectors can be determined by inspecting the charge flow in all the phases.
For the 1/4x mode, the charge vectors of capacitors ac,i(Фj) can be written below, and different
from 2-phase operation, the calculation involves three vectors:
1
𝑎𝑎𝑐𝑐 (Ф1 ) = [4
1
𝑎𝑎𝑐𝑐 (Ф2 ) = [− 4
𝑎𝑎𝑐𝑐 (Ф3 ) = [0
1
]
4
(5.14)
1
(5.15)
].
(5.16)
1
2
]
4
Referring to Fig. 5.3(a), the switch charge vector ar,i(Фj) of transistors (S1 to S10) can be obtained
as:
1
𝑎𝑎𝑟𝑟 (Ф1 ) = [4 0 0 0
𝑎𝑎𝑟𝑟 (Ф2 ) = [0 0
𝑎𝑎𝑟𝑟 (Ф3 ) = [0 0
0 0
1
2
0
1
4
1
4
0
0 0 0
0 0
1
4
0
1
4
1
4
0 0 0
0]
0]
1
].
2
(5.17)
(5.18)
(5.19)
By substituting (5.14) to (5.16) and (5.17) to (5.19) into (5.10) and (5.13), the
topological factors can be calculated. After applying this method to all 6 VCRs, the impedance
vectors can also be calculated. Table 5.1 summarizes the metrics of the 6 conversion ratios. An
interesting observation is that RSSL and RFSL of the 1/4x mode are the same as those of the 3/4x
mode, because the charge vectors of the two flying capacitors have the same values. After
getting RSSL and RFSL, ROUT could be obtained by (5.7), and the power losses including charge
redistribution loss and conduction loss can be calculated from
𝑃𝑃𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 = 𝑅𝑅𝑂𝑂𝑂𝑂𝑂𝑂 𝐼𝐼𝑂𝑂2 .
(5. 20)
Fig. 5.5 shows the calculated and the simulated output impedance with respect to the
frequency and the unit-size transistor (= 700 µm/0.33 µm), respectively. The simulated results
fit the calculated results very well in general. The mismatch between calculated and simulated
ROUT is due to the non-idealities in practical implementation. For example, the model is
inaccurate when the output has ripples [Breussegem 2012]. Besides, ideal duty cycles of 50%
and 33.3% are used in the calculation, but these values are smaller in simulations due to the
47
switching dead-times.
From Table 5.1 and Fig. 5.5, we learn that ROUT of 3-phase modes are of the same range
as those of the 2-phase modes, hence, both current driving capability and power conversion
efficiency are not affected. ROUT of the 1/1x mode and the 3/4x mode are larger because equal
sizing was adopted for an easy layout, and thus the PMOS switches have larger turn-on
resistance than the NMOS switches.
TABLE 5.1 SUMMARY OF EQUIVALENT OUTPUT IMPEDANCE OF 6 VCRS
Fig. 5.5. Simulated and calculated output resistance versus frequency and unit width of
transistor under 6 VCRs.
48
5.3
Digital Adaptive Ripple Reduction
An SC converter may suffer from large voltage ripples if the charge delivered to the
outputs is not well controlled. To reduce the ripple voltage of an SC converter multi-phase
interleaving that results in ripple cancellation was investigated in [Breussegem 2009],
[Somasekhar 2010], [Le 2011] and has been commonly used [Pique 2012], [Lu 2017], [Bang
2016]. Modulating the capacitance [Kudva 2013] reduces the ripple voltage by suppressing
extra charge being delivered to the outputs. Both techniques rely on using on-chip capacitors
that could be split into smaller capacitors. For large power applications that use discrete
capacitors, tuning the on-resistance is easier to be realized. In [Lee 2007], a three-stage
amplifier is used to drive the power transistors and the on-resistance is adjusted through
changing the gate voltages. In [Jain 2014], both gate-voltage and transistor-size modulation
were used. For a digital SC converter, tuning the gate voltage of transistors needs analog circuits
and is not preferred. Hence, in our design, transistor-size modulation was used. The concept of
the proposed light-load ripple reduction scheme is shown in Fig. 5.6. Basically, the charging
and discharging phases of an SC converter are controlled by a hysteretic comparator. Ideally,
when VO is larger than the reference voltage VREF, the comparator output should become high,
and the SC converter should instantaneously change to the discharging phase. However, there
is loop delay (td) due to the comparator and the power stage that would postpone the phase
transition. In such case, an excess charge of qover will be overcharging the output capacitor, and
results in a higher output voltage ripple that is derived as
Fig. 5.6. Concept of proposed ripple reduction scheme.
49
𝛥𝛥𝑉𝑉𝑂𝑂 ∝
𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜
𝐶𝐶𝐿𝐿
𝑉𝑉
𝑡𝑡
∝ (𝑅𝑅𝑂𝑂𝑂𝑂 − 𝐼𝐼𝑂𝑂 ) 𝐶𝐶𝑑𝑑 ,
𝑂𝑂𝑂𝑂
𝐿𝐿
(5.21)
where VON is the averaged voltage across the turn-on resistors connecting the flying capacitors
to CL, and is different for different VCRs. RON and CL are the turn-on resistance and loading
capacitor, respectively. In the hysteretic control, (VON/RON - IO) is the charging slope and is
always larger than zero. The charging slope is larger when IO is smaller, and the converter has
larger ripple at light load. Based on (5.21), reducing the delay (td) or increasing RON and CL can
help reducing the ripple voltage.
Loop delay is inherent to the system and shortening it requires power. Moreover, it
varies with process, voltage and temperature (PVT) conditions. Controlling the delay precisely
by a digital compensation loop is complicated. Therefore, for a digital SC converter using
discrete capacitors, tuning the size of power switches is a more feasible way to reduce ΔVO.
In order to achieve ripple reduction under many conditions, our proposed method senses
the loading condition and adjusts the output impedance to limit the extra charge. As shown in
Fig. 5.6, a counter in the digital controller detects the duration of the discharging phase. If it is
longer than the pre-set range, the controller will decrease the size of the power switches, and
the rising slope in the next charging phase will be reduced. In this way, the portion of the output
voltage that is higher than VREF will be smaller, yielding a suppressed overcharged ripple
voltage.
Fig. 5.7. Timing diagram of operation procedure.
50
Fig. 5.7 is a timing diagram example that illustrates the ripple reduction and the power
stage adjustment process. Initially, the power switches have a full size of 8. Due to the intrinsic
loop delay, the power stage cannot be changed to the discharging phase immediately, and the
large charging slope results in a large output ripple voltage. The digital counter senses that the
discharging period is 14 cycles of the system period, which is larger than the pre-set range. In
the next step, the controller decrease the size of the power switches by 1 bit, resulting in a
smaller charging slope. However, one step adjustment is not enough. The process will continue
until the duration of the discharging duration is within the pre-set range. Size adjustment is
activated only after the discharging duration has been out of range N times (N is chosen to be
26), as detected by a counter to avoid false triggering. Finally, the size of the power switches is
locked when the discharging duration is within 5-7 cycles of the system clock period, which
results in a higher switching frequency and smaller ripple for VO.
The logic flow of adaptive ripple reduction is shown in Fig. 5.8. After initialization, a
counter always keeps monitoring the duration of the discharging phase, and N cycles of the
Fig. 5.8. The digital logic flow of adaptive ripple reduction.
51
system clock is set as a comparison duration. After one comparison period, the value of the
counter will be compared with the pre-set threshold value. If the counter value is larger than the
threshold value, the size of the power stage will be increased. On the contrary, if the counter
value is smaller, the size of power stage will be decreased. The size will keep unchanged when
the counter value is within the pre-set range.
To avoid a large droop when light load changes to heavy load, especially when the size
of the power stage is small due to the ripple reduction scheme, the following mechanism is
installed. When light load suddenly changes to heavy load, the output voltage will drop because
there is not enough current delivered to the output capacitor. This will result in a very short
discharging phase and the counter will detect that the value is much shorter than the heavy load
detection threshold value (1-2 cycles of system clock). In this case, the power-stage size will
change to maximum to restore the output voltage.
Fig. 5.9. The mechanism to respond the transient current.
52
Fig. 5.10. The timing diagram of the design for test (DFT) module.
In the switch-reduction process, the size will be reduced by 1 bit each cycle. Once it
detects a load-increase transient, full size will be used instantaneously to ensure full capacity in
delivering the power.
The mechanism to respond to the transient current is shown in Fig. 5.9. Initially, let us
assume that the load is light and the power stage size is 2. When the load suddenly changes to
a heavy load, the output voltage will drop due to incapability to deliver the large current. This
will result in a very short discharging phase. The counter will detect that the value is much
shorter than the heavy load detection threshold (1-2 cycles of system clock). In this case, the
size of the power stage will be increased to the maximum to restore the output voltage.
To have a better monitoring of the internal status of digital registers, a design-for-test
(DFT) module is also designed to send the critical data out. The timing diagram of DFT module
is shown in Fig. 5.10. The internal register values are transferred from parallel bits to 1-bit
series output through TEST_BIT. The whole procedure needs 16 clock cycles, starting from
prefix ‘0101’ and ending with the end-bit ‘1’. The values of the registers including the power
stage size and VCR are updated at the start of the third cycle. When reading the TEST_BIT
waveform, the power stage size will be updated within 1 to 2 sampling periods of the DFT
module after the load edge.
5.4
Converter Design and Implementation
5.4.1
System Architecture
Fig. 5.11 shows the overview of the system architecture. It consists of five ratio
encoding comparators (CMP1-5), a hysteretic comparator (CMP6), a digital controller, level
53
Fig. 5.11 System architecture of proposed 2-/3-phase SC converter.
shifters, gate drivers and power stages. To determine the VO/VIN ratio, VIN is compared to VREF
by CMP1-5 and the code T2-0 indicating the VCR to be used is issued by the ratio encoder. The
driver signal generator then issues the driving signals ck1-10 to provide on/off sequences for the
power switches. Instead of manually designing the logic blocks, digital synthesis is adopted to
reduce design complexity and to accelerate the design speed.
The power stage is split into 8 cells and each cell can be adaptively enabled or disabled
by the signal P7-0. In such a way, the size of the power switches is adjusted by the adaptive
phase controller according to the load current, thus reducing the output voltage ripple especially
at light load. The input, output and two flying capacitors are implemented by one 4 × 1 μF
capacitor array [AVX 2003], and the volume is 40% smaller than using 4 discrete capacitors.
5.4.2
Power Stage
The number of switches is optimized for achieving the six reconfigurable VCRs. Fig.
5.12(a) shows a conventional 2-phase implementation of the 6 VCRs using 3 flying capacitors
and 14 switches. By using 3-phase operation, only 2 flying capacitors (C1 and C2) are needed.
To reduce the number of power switches, a switch reduction scheme is proposed in Fig. 5.12(b):
when connecting C1 to C2, only the positive plate of C2 is connected together with C1, and the
negative plate of C2 is connected to VO, VIN and GND. In this way, only two switches (S5 and
S6) are needed. Therefore, the power stage of the proposed SC converter only needs 2 flying
54
Fig. 5.12. Configuration of switches and flying capacitors of (a) conventional 2-phase SC
converter; (b) proposed switch reduction scheme for 2-/3-phase SC converter.
Fig. 5.13. Power stage implementation of proposed 2-/3-phase SC converter.
capacitors and 10 power switches, and silicon area reduction of around 28.5% compared with
the conventional 2-phase SC converter is achieved, if the size of the power transistors are the
same.
Fig. 5.13 shows the transistor-level implementation of the power stage. To cater for a
wide output voltage range, the switches S2-3, S5-6 and S8-9 that connect to VO are implemented
with complementary devices (C-switches). The switches that connect to VIN (S1 and S4) and
GND (S7 and S10) are implemented by PMOS and NMOS transistors, respectively. The signals
ck1-10 are generated by the digital controller and buffered by the level-shifters and pre-drivers.
55
Fig. 5.14. (a) Layout floorplan of power cells and clock buses; (b) Switch logics.
To enable digital adaptive ripple reduction, the power stage is split into 8 power cells with the
same configuration. The detail will be introduced in the following section.
As the polarity of C2 may change in different configurations, therefore, C2 should not
be an electrolytic capacitor but a non-polarized ceramic capacitor. Short bond-wires and small
packages are preferred because the capacitors then have lower equivalent series resistance (ESR)
and inductance (ESL) and the glitches could then be reduced. Moreover, the voltage coefficient
has to be taken into account, such that a sufficiently large capacitance is ensured when a high
DC voltage is applied.
5.4.3
Adaptive Power Cells for Ripple Reduction
The layout configuration is shown in Fig. 5.14. All power cells are identical. The turn
on/off signals of the power cells use thermometer code, and there is only 1-bit change of power
cells during the transition. As such, potential glitches due to reconnecting the power cells are
minimized. To eliminate phase mismatch during clock distribution, the H-tree structure is
56
TABLE 5.2 CLOCK SELECTION OF THE SWITCH LOGICS WITH VCRS
Fig. 5.15. Timing diagram of synchronized hysteretic control by using (a) dynamic
comparator, (b) static comparator, and (c) status of each phase.
employed, as shown in Fig. 5.14(a). The three clock phases (Φ1, Φ2 and Φ3), the VCR selection
signals and the enable signal EN are generated in the digital controller and then distributed by
clock buses.
The block diagram of switch logic is shown in Fig. 5.14(b). The logic that determines
the clocks for each transistor is placed locally close to each power cell. The dead-time
generation circuit is used to prevent shoot-through current and is placed locally at the power
cell. Table 5.2 lists the clock phase selection of each transistor (S1 to S10) under different VCRs.
For example, when VCR = 1/4x, transistors S1, S6 and S9 will be turned on in Φ1; S5, S7 and S9
will be turned on in Φ2 and S3, S7 and S10 will be turned on in Φ3; and S2, S4 and S8 will be kept
off. The selection logic is synthesized by standard digital cells.
57
5.4.4
Digital Controller
The digital controller consists of the adaptive ripple reduction circuit (discussed in
Section 5.3) and the switching controller, to be discussed below. Fig. 5.15 shows the
synchronized hysteretic control that is used to achieve voltage regulation and fast response. The
single boundary is set to be equal to VREF, representing the designed output voltage level. In
[Breussegem 2011], when the comparator detects that VO is lower than VREF, the SC converter
will switch to the next clock phase to recharge the output capacitor. A dynamic comparator that
consumes no quiescent current is used, and triggered by a high-frequency system clock. The
power consumption is low but the drawback is that it needs system clock to trigger the boundary
violation detection, meaning that the phase switching could not be triggered immediately when
VO is lower than VREF (in Fig. 5.15(a)). When the system frequency is high, the delay could be
small. However, our design uses a 10MHz system clock. In the worst case, a delay of 100ns is
needed before the system clock could trigger to flip the dynamic comparator. Therefore, the
delay may bring extra charge to the output and result in large voltage ripple.
In this design, to avoid causing extra ripple voltage after VCMP turns high, synchronized
hysteretic control is used. The system clock is set at 10 MHz, generated by an on-chip ring
oscillator. At 10 MHz, the speed requirement of the comparator is not as critical as that in
[Breussegem 2011], and a static comparator (CMP6) with 12 µA quiescent current is used
instead of a dynamic one, as shown in Fig. 5.15(b). The turn-on of the charging phase is
triggered by the system clock, while the turn-off is triggered by the comparator. Hence, the
delay due to the mismatch of the system clock can be eliminated. Then, by employing the
proposed adaptive ripple reduction technique described in Section 5.3, the undesired ripple
voltage caused by loop delay due to the static comparator, digital logic, level shifters and power
stages could be reduced.
Fig. 5.15 also shows the status of each phase in the 2-/3-phase mode. For 2-phase mode
VCRs, Ф1 and Ф2 are interchangeable. We may define the charging phase as Ф1, and the
discharging phase as Ф2. For 3-phase mode VCRs, refer to the sequence in Fig. 5.3. In Ф3, the
output capacitor receives more charge than in Ф1 and Ф2. From the perspective of the output
capacitor, VO falls in Ф1 and Ф2, and rises in Ф3. Hence, Ф1 and Ф2 are defined as the
discharging phases, and Ф3 is defined as the charging phase. For design simplicity, the transition
between Ф1 and Ф2 is triggered by the system clock.
58
Fig. 5.16. (a) Chip micrograph; (b) layout of synthesized digital controller; and (c) top and
bottom view of PCB for measurement with capacitor array in 0612 packing.
5.5
Measurement Results
The proposed SC converter was fabricated in a 0.13 µm bulk CMOS process. Fig. 5.16(a)
shows the chip micrograph with a total area of 750 µm × 1500 µm, including power switches,
comparators, the digital controller and decoupling capacitors. The layout of the fully
synthesized digital controller with an area of 80 µm × 80 µm is shown in Fig. 5.16(b), and the
PCB setup with the 0612 capacitor array is shown in Fig. 5.16(c). The capacitor array is on the
top of the PCB and the chip is bonded on the bottom, and they occupied almost the same PCB
area. The 4 × 1 µF capacitor array is mounted on the top side of the PCB, and the test chip is
wire-bonded on the bottom side. The four capacitors are the two flying capacitors and the input
and output decoupling capacitors. Other capacitors are used for testing purposes.
Fig. 5.17 shows the measured efficiency versus the load current. This design achieved
a moderately high load current capability of 120 mA in all 6 modes. The measured peak
efficiency was 91% when VIN = 3.3 V and IO = 30 mA. The results with and without the 359
Fig. 5.17. Measured efficiency of the proposed SC converter versus loading current.
Fig. 5.18. Measured efficiency of the proposed SC converter versus output voltages.
phase modes are shown for comparison. When VO = 2.3 V, by using the 3-phase 3/4x mode
instead of the 2-phase 1/1x mode, the converter achieved up to 18% efficiency improvement.
When VO = 0.8 V, it also achieved up to 8% efficiency improvement by using the 3-phase 1/4x
mode rather than the 2-phase 1/3x mode.
The measured efficiency with respect to the output voltage is shown in Fig. 5.18. It
shows that efficiency improvements of 13% and 20% were obtained when the converter worked
in the 1/4x mode and 3/4x mode, respectively. Fig. 5.19 plots the efficiency versus the input
voltage, and shows efficiency improvement when the 3-phase modes were used instead of the
2-phase modes. Benefited from 3-phase modes, the average efficiency improvement over the
entire input voltage range when VO = 1.8 V, 1.2V and 0.75V are 5.4%, 1.7% and 0.6%,
60
Fig. 5.19. Measured power efficiency versus input voltage.
respectively. When VIN = 3.3V and 2.5V, the average efficiency improvement over the output
range is 3.4%. Moreover, with two additional VCRs, the SC converter achieved a wide output
voltage range of 0.5 V to 3 V with an input voltage of 1.6 V to 3.3 V.
The measured output ripple voltage at different loading currents is shown in Fig. 5.20.
By activating the ripple reduction scheme, the measured AC coupled voltage ripples were all
lower than 50 mV for IO that ranged from 3 mA to 100 mA. Fig. 5.21 shows the effectiveness
of the ripple reduction scheme, which is enabled by the adaptive-phase-enable signal AP_EN.
Before AP_EN was enabled, large ripples and glitches around 100 mV can be observed due to
the parasitic inductance of bond-wires and PCB traces. After AP_EN was enabled, the ripple
voltage was significantly reduced. As high as 4 times ripple reduction was achieved from 90
mV to 20 mV for IO = 3 mA and VO = 1.95 V. The ripple reduction was also effective in other
conditions, also listed in Fig. 5. 21.
61
Fig. 5.20. Measured steady-state waveform of output ripple voltage.
Fig. 5.21. Measured waveforms of light load ripple reduction under difference VCRs.
To observe the status of registers in the digital controller and help debugging during the
measurement, a design-for-test (DFT) module was implemented. Parallel to series conversion
was done to reduce the number of monitoring pins. The data of registers indicating the VCR
used and the size of power stage (P[7:0]) were read out through the single TEST_BIT pin. The
sequence of the testing output is initialized by the prefix bits 4b’0101, followed by the size of
the power stage and the code of VCR, and terminated by the end bit 1b’1. Fig. 5.22 shows the
62
Fig. 5.22. Measured waveforms of ripple reduction procedure and the outputs of testing data.
Fig. 5.23. Measured waveforms of transient response.
measured procedure of ripple reduction. From period-A to period-C, the size of the power stage
was decreased from 8b’11111100 to 8b’11100000 after (AP_EN) was triggered.
The measured transient response waveforms of VO = 1.5 V (in 2-phase mode) and 2.3
V (in 3-phase mode) are shown in Fig. 5.23. Due to the hysteretic control, when the load current
63
switched from 1 mA to 90 mA and 1mA to 80 mA, ΔVOUT was around 50 mV and the recovery
time was less than 500 ns. No obvious over-shoot or under-shoot was observed. To restore
current deliverability, the power stage was fully turned on once a heavy load was detected.
Table 5.3 summarizes the performance comparison with state-of-the-art works.
Compared to commercial products with off-chip capacitors delivering similar output power
with the same number of flying capacitors, this work achieved more VCRs and hence efficiency
was improved. Moreover, this work delivered more power using fewer flying capacitors and
achieved a wider VOUT/VIN range than the recursive SC converter of [Salem 2015]. Compared
with integrated 2-phase [Lu 2017] or 3-phase [Karadi 2014], [Jiang 2015] SC converters, the
proposed SC converter achieved a wider operating voltage range. As discrete flying capacitors
with larger value were used, this work also achieved a higher output power with higher power
conversion efficiency.
5.6
Conclusions
In this chapter, a 2-/3-phase 6-ratio switched-capacitor DC-DC converter is proposed.
TABLE 5.3 PERFORMANCE COMPARISON WITH STATE-OF-THE-ART SC CONVERTER WORKS
64
The 3-phase operation is proposed and analyzed to achieve two more VCRs than the
conventional 2-phase SC converter. The achieved maximum available output voltage range
over the input voltage range is up to 75.8%, and the power conversion efficiency was improved
by as high as 20% compared to 2-phase SC converters.
A digital adaptive ripple reduction scheme is also introduced to reduce the output
voltage ripple by as much as 4 times at light load. This converter is implemented in a 0.13 µm
bulk CMOS technology and is capable of operating at a wide input range of 1.6 V-3.3 V and a
wide output range of 0.5 V-3 V with 91% peak efficiency and delivers a maximum power of
250 mW.
5.7
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68
Chapter 6
DUAL-OUTPUT SC CONVERTER FOR MULTI-CORE APPLICATION PROCESSOR
6.1
Introduction
Multi-core application processors in smart-phone and smart-watch use power-saving
techniques such as dynamic voltage and frequency scaling (DVFS) to extend battery cycle, and
each core may need a different supply voltage [Wang 2014]. High-efficiency fully-integrated
switched-capacitor (SC) power converters with no external component are promising
candidates. Typically, SC converters with different specifications are independently designed
(Fig. 6.1), leading to a large area overhead as each converter has to handle its peak output power.
Recently, multi-output SC converters are reported to tackle this issue. In [The 2016], the ondemand strategy is used to control the two outputs, each with a different loading range, and the
outputs are not interchangeable. In [Hua 2015], the two output voltages are fixed with voltage
conversion ratios (VCRs) of 2x and 3x only. In [Jung 2016], the controller is integrated, but the
three output voltages are still from three individual SC converters. Without reallocating the
capacitors in the power stages, capacitor utilization is low as margins have to be reserved to
cater for each peak output power.
In this chapter, a fully integrated dual-output SC converter with dynamic power-cell
allocation for application processors is proposed. The power cells are shared and can be
dynamically allocated according to load demands. A dual-path VCO that works independently
of power-cell allocation is proposed to achieve a fast and stable regulation loop. The converter
can deliver a maximum current of 100mA: one output can be adjusted to deliver 100mA, while
the other handles a very light load; or both outputs can be adjusted to deliver 50mA each with
over 80% efficiency.
69
Fig. 6.1. Strategy of dynamic power-cell allocation and system architecture of proposed dualoutput SC converter.
6.2
Dynamic Power-Cell Allocation
Fig. 6.1 shows the strategy of dynamic power-cell allocation. The converter consists of
two channels CH1 and CH2 with output voltages VO1 and VO2, respectively. Each output is
regulated through frequency modulation. The switching frequencies of the two channels are f1
and f2. The goal is to adjust them to be equal so that both channels have the same power density,
and the converter achieves the best overall efficiency. Assume that the two channels start with
the same number of power cells, but the load of CH1 is larger than that of CH2. To regulate the
outputs properly, we should initially have f1 > f2, and more power cells will eventually be
assigned to CH1. It means the physical boundary should go right, until f1 and f2 are
approximately equal. By balancing the power densities of the two channels with an optimal
switching frequency, both switching and parasitic losses are reduced. By dynamically adjusting
both the numbers of power cells and the optimal switching frequencies, the channels are ensured
70
to provide sufficient power to the loads, and utilization of capacitors is maximized.
The power cells are connected to either CH1 or CH2 by the channel selection switches.
The boundary of the two channels are controlled by the outputs of the bi-directional shift
register (SR) sel[1:m+n]. The direction of boundary shifting is determined by the frequency
comparator. After each comparison, the boundary will only shift along adjacent power cells as
sel[1:m+n] will only shift by 1 bit. As such, potential glitches due to reconnecting the power
cell are minimized. There are a total of 82 power cells, and they work with interleaving phases
to reduce the output ripple voltage. The VCRs of the two outputs (R1 and R2) are determined
by the ratio selector that senses VREF/VIN.
To enable the allocation while minimizing cross regulation, a dual-path voltage-controlled
Fig. 6.2. Circuit implementation of dual-path VCO, delay cell of dual-path VCO and power
stage.
71
oscillator (VCO) is proposed, as shown in Fig. 6.2. The VCO consists of 82 delay cells,
generating the clock phases for each power cell. One delay cell in CH1 (DC1[n]) has a
complementary delay cell in CH2 (DC2[n]). The phases φ1[n] and φ2[n] are chosen by the MUX
and then distributed to the power cell. If sel[n] = 1, DC1[n] of VCO (CH1) is enabled. At the
same time, DC2[n] will be shorted by the MUX and the clock phase is redirected to the next
cell. In this way, the number of delay cells in each VCO is equal to the number of its power
cells, and multi-phase interleaving can take effect to reduce the output ripple voltage. The
frequency of VCO is controlled by the error amplifier, and the two outputs are separately
regulated, regardless of the power-cell arrangement. As the speed of the regulation loop is much
faster than that of power-cell allocation, stability is ensured. Each power cell consists of 2 flying
capacitors and 8 power transistors and the VCR can be 2/3x or 1/2x. The configuration of each
power cell is optimized to minimize the parasitic loss. The channel selection switches,
controlled by sel[n], connect the local output VOL to VO1 or VO2.
Fig. 6.3 shows the control logic that consists of the frequency comparator and the power-
Fig. 6.3. Circuit implementation of frequency comparator, bidirectional shift register and the
timing diagram of frequency comparison.
72
cell shift register. First, the one-shot signals (ck1os and ck2os) control P1 and P2 to charge CC1
and CC2 for one clock period only. The ready signals (ready1 and ready2) are activated after
charging is finished, and trigger the comparison between VF1 and VF2. After a short delay CC1,
CC2 and logic are reset. For the comparison, if VF1 < VF2, meaning that f1 > f2, the direction
signal of the shift register is then set as direct = 0, and the selection signals will shift left by 1
bit. This frequency adjustment repeats until f1 and f2 are very close to each other. The frequency
comparator will then issue stop = 1, and the shift register stops shifting. To ensure accurate
charging, the current sources and capacitors (CC1 and CC2) are well matched. For robust control,
offsets are added to the comparators to form the hysteresis window. The whole process is driven
by ck1 and ck2 only, without an additional system clock.
6.3
Measurement Results
The proposed dual-output SC converter was fabricated in a 28nm CMOS process. The
active area is 1.2 × 0.5 mm2. The chip micrograph is shown in Fig. 6.4. Fig. 6.5 shows the
measured waveforms of the steady-state outputs, reference tracking and load transient. The
measured results verified that the two output voltages could be independently regulated and the
two switching frequencies were adjusted to be very close. The measured reference up- and
Fig. 6.4. Chip micrograph.
73
Fig. 6.5. Measured waveforms of steady state output voltages, reference tracking and loading
transient response.
down-tracking speeds were 500mV/µs and 334mV/µs, respectively. No obvious cross
regulation was observed at VO2 while VO1 was undergoing reference tracking. With the load at
VO1 switched from 4mA to 40mA, the settling time was within 500ns. The cross regulation at
VO2 was less than 10mV at the rising edge and negligible at the falling edge, verifying that the
dual-path VCO control could achieve minimized cross regulation.
Fig. 6.6 plots the measured efficiencies versus the load currents IO1 and IO2. The peak
efficiency was 83.3% and the split load currents were 50mA for both channels. Due to dynamic
power-cell allocation, the converter achieved over 80% efficiency and it was quite constant
when IO1 and IO2 were larger than 15mA. The efficiency with allocation is improved by 4.8%
than without allocation. Table 6.1 shows the performance comparison. By using dynamic
power-cell allocation, the proposed dual-output SC converter achieved high efficiency over a
board load range for the two outputs with minimized cross regulation.
74
Fig. 6.6. Measured efficiency versus loading currents with and without dynamic power
allocation.
TABLE 6.1 PERFORMANCE COMPARISON WITH START-OF-THE-ART WORKS
6.4
Conclusions
75
A fully integrated dual-output SC converter with dynamic power-cell allocation for
application processors is presented. The power cells can be dynamically allocated according to
load demands, improving the efficiency by 4.8% than without allocation. A dual-path voltage
controlled oscillator (VCO) that works independently of power-cell allocation is proposed to
achieve a fast and stable regulation loop. The converter achieved 83.3% peak efficiency and a
maximum 100mA while maintaining minimized cross regulation.
6.5
Reference
[Wang 2014]
A. Wang, “Heterogeneous multi-processing quad-core CPU and dualGPU design for optimal performance, power, and thermal tradeoffs in a
28nm mobile application processor,” in Proc. IEEE Int. Solid-State
Circuits Conf., pp. 180-181, Feb. 2014.
[Hua 2015]
Z. Hua, et al., “A reconfigurable dual-output switched-capacitor DC-DC
regulator with sub-harmonic adaptive-on-time control for low-power
applications,” IEEE J. Solid-State Circuits, vol. 50, no. 3, pp. 724-736, Mar.
2015.
[Jung 2016]
W. Jung, et al., “A 60%-efficiency 20nW-500µW tri-Output fully
integrated power management unit with environmental adaptation and
load-proportional biasing for IoT systems,” in Proc. IEEE Int. Solid-State
Circuits Conf., pp. 154–155, Feb. 2016.
[Teh 2016]
C. K. Teh and A. Suzuki, “A 2-output step-up/step-down switchedcapacitor DC-DC converter with 95.8% peak efficiency and 0.85-to-3.6V
input voltage range,” in Proc. IEEE Int. Solid-State Circuits Conf., pp.
222–223, Feb. 2016.
76
Chapter 7
A HYBRID SC CONVERTER FOR AMLED DISPLAY SYSTEM
7.1
Introduction
There is a growing demand for micro display systems to be implemented in wearable
devices and virtually reality (VR) applications. In recent years, active matrix light-emitting
diode (AMLED) is gaining popularity [Zhang 2012], [Chong 2014], [Tsonev 2014], [Li 2016].
Compared with the liquid crystal display (LCD), a light-emitting diode (LED) based micro
display is self-emissive that produces bright images without an external light source, and is thus
thinner and smaller. Moreover, the semiconductor-based LED has longer lifetime and better
robustness, and is produced with lower fabrication cost than technologies such as organic LED
(OLED) [Chong 2014].
An AMLED array is usually implemented using a gallium nitride (GaN) process. The
ON and OFF status of each LED pixel is controlled by a pixel driver, usually fabricated on
silicon. In some designs, the AMLED array may be bonded on the pixel driver [Li 2016], but
the power management unit (PMU) remains external [TI 2015]. Therefore, there is a strong
motivation to merge the pixel driver and the PMU IC on the same silicon chip to reduce both
the volume and the cost of the system.
Integrating the PMU with a switching DC-DC converter is a major challenge as it is
difficult to fabricate a good power inductor on-chip [Liu 2016 I], [Liu 2016 II]. By comparison,
linear regulators only need transistors and switched-capacitor (SC) converters only need
capacitors and switches that are readily available on-chip. In particular, the efficiency of an SC
converter could be high when the ratio of the output voltage VO to the input voltage VIN is
closed to the ideal voltage conversion ratio of the converter [Jiang 2015].
Another important requirement for the PMU is low output voltage ripple, especially for
driving an AMLED display, as the current of a micro LED is very sensitive to its bias voltage.
77
A large voltage ripple may result in large variation of intensity, thus degrading the uniformity
of the whole display. For an SC converter, reduced voltage ripple could be achieved by
multiphase interleaving [Lu 2017] or modulating the turn-on resistance of the switches [Jiang
2017]. For a linear regulator, the ripple voltage is much reduced through the operation of the
feedback circuit.
In this chapter, we will detail the design of a fully integrated AMLED micro display
system. From the discussion above, we propose to power up the display by a hybrid voltage
regulator that eliminates external components and achieves low voltage ripple. It consists of a
step-up switched-capacitor converter and a step-down linear regulator and covers the whole
voltage range of a Li-ion battery, that is, from 2.7V to 4.2V. The pixel driver and the PMU are
implemented on the same silicon chip, and together they are integrated with the AMLED array
by using the flip-chip technology.
This chapter is organized as follows. Section 7.2 introduces the system architecture and
design considerations of the proposed micro display system. Section 7.3 presents the design of
the hybrid voltage regulator. Section 7.4 discusses the digital control of the pixels, and Section
7.5 introduces the design of the AMLED and the method of system integration. Measurement
results are shown in Section 7.6 and then followed by the conclusion.
7.2
System Architecture and Design Consideration
Fig. 7.1 shows the architecture of the proposed micro display system. It consists of a
hybrid voltage regulator, a pixel driver and an AMLED array. The AMLED array has 36 × 64
pixels that are built on a GaN substrate, and each pixel needs a silicon pixel driver that is flipbonded on the same location as the LED pixel. The pixel driver is powered up by a voltage
regulator built on the same silicon that provides a stable internal voltage VO.
The image data are sent from a digital controller and are received by I/O pins (CCK,D,EN,
RCK,D,EN and RST) in a predetermined sequence. Row and column drivers are used to transfer
the data to all the pixels. For the I/O pins to communicate with any off-chip voltage level up to
5V, high to low level shifters are used to convert the input signal to the internal voltage level.
78
Fig. 7.1. System architecture of proposed micro display system.
Fig. 7.2. Schematic of the hybrid voltage regulator.
79
7.3
Hybrid Voltage Regulator
The operating voltage of the LED and the pixel driver (VO) of our project is 3.6V. To
cater for the Li-ion battery voltage that ranges from 2.7V to 4.2V, the voltage regulator should
achieve both step-up and step-down voltage conversion. Fig. 7.2 shows the architecture of the
hybrid voltage regulator. It can generate three voltage conversion ratios (VCRs). When the
input voltage is lower than 3.6V, the SC converter is enabled and the VCR could be adjusted to
3/2x or 4/3x. When the input voltage is higher than 3.6V, the linear regulator is enabled and the
VCR is 1/1x.
Circuit implementation of the power stage of the SC converter is shown in Fig. 7.3.
Each power cell has three flying capacitor (C1, C2 and C3) that are built from both MOS and
MIM capacitors to maximize the power density. Each cell has 11 power transistors (S1 to S11),
some of which are implemented by stacking two low-voltage transistors together to handle high
voltages. The voltage conversion ratio (VCR) is determined by the VCR detection circuit that
compares the input voltage VIN with the reference voltage VREF.
When only the linear regulator is needed (VCR=1/1x), the SC converter is disabled, and
Fig. 7.3. Circuit implementation of power stage in SC converter.
80
Fig. 7.4. Floorplan of voltage regulator.
all the flying capacitors are connected between VO and ground, making them the load capacitor.
This is particularly important for the linear regulator with the dominate pole set at the output
node, such that the compensation scheme is much simpler than capacitor-free designs. To avoid
forward conduction of the body diodes, a body-selection circuit (MP1 and MP2) is employed to
ensure that the body of the PMOS transistor (ML) is always tied to the highest voltage in the
system, especially when VO is higher than VIN.
The layout floorplan is shown in Fig. 7.4. The AMLED array and the corresponding
pixel drivers occupy the large central area. For efficient power distribution, the power stage is
divided into cascading power cells that form a ring to encircle the pixel drivers, such that current
can be delivered over the shortest path with the lowest resistance. Thick power rails are laid in
between the pixel drivers to reduce the IR drop. For ripple reduction, the SC converter has a
total of 87 interleaving phases. The number of phases and the aspect ratio of the power cell are
defined by the perimeter of the AMLED array. The maximum output current is 60mA.
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Fig. 7.5. Structure of Pixel Drivers.
7.4
Display Control
Fig. 7.5 shows the transistor implementation of the pixel drivers. Each pixel driver
measures 40µm × 40µm and consists of three transistors (M1, M2 and M3) and one capacitor
(CST). The operating principle is as follows. A logic "0" enables the row RSEL, turning on the
corresponding M1 and the display data is then written and stored in the capacitor CST. The
voltage across CST controls the status of the driving transistor M2. M3 is controlled by the global
enabled signal REN.
The display data is updated through row-by-row progressive scanning. First, the 64-bit
display information of the first row is written into the column driver serially and also loaded
into the signal lines from CDATA[0] to CDATA[63]. Then, RSEL[0] is enabled, and each CST of the
first row will store the display data from CDATA. After that, RSEL[0] is disabled and the scanning
of the first row is finished. The same procedure is then repeated for the other rows. After all
82
pixels are loaded with the display information, REN is enabled to trigger and display the
programmed image.
7.5
AMLED Array and System Integration
The AMLED array consists of 36 × 64 pixels each measures 40µm × 40µm. The aerial
view of the LED array is shown in Fig. 7.6(a). The pixels were isolated by ICP etching down
to sapphire and the trench was filled by a black mixture of three kinds of color filter, which
could suppress the crosstalk between the pixels. The array adopts a common-cathode design,
and all the LED pixels were uniformly distributed in the central area with p-type electrodes
covered on the top, while the n-type electrodes were connected to the circumference of the LED
array. The measured I-V curve of one LED pixel is shown in Fig. 7.6(b). The forward voltage
of the pixel is 2.85V at 30 µA.
Fig. 7.6. (a) Cross sectional diagram of the LED µ-array with indium bumps; and (b) IV
characteristic of LED pixels.
Fig. 7.7. (a) SEM of LED µ-array with indium bumps after reflow process; and (b) alignment
of AMLED array and silicon substrate.
83
Fig. 7.8. Chip micrographs of (a) AMLED array; (b) pixel driver and PMU and (c) integrated
system.
An Au-In metal bonding scheme is adopted to flip-chip bond together the AMLED array
and the pixel driver. After the indium deposition on the pixels' p-electrodes, the indium bumps
can be formed through a reflow process in a furnace at 170ºC for 1 second in a formic acid
ambient. The scanning electron microscope (SEM) image of the indium bumps after the reflow
process is shown in Fig. 7.7(a). The diameter of the indium bumps is around 15µm and the
height is about 7.5µm. The AMLED array is then flip-chip bonded on the silicon IC by using
Au-In metal bonding under a pressure of 10N at 170ºC for 1 minute. The two chips are aligned
by reserved alignment marks.
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7.6
Measurement Results
The silicon IC with the pixel driver and the PMU was fabricated in a 0.18µm bulk
CMOS process, and the AMLED array was fabricated in a GaN process with an area of 1.6mm
× 2.72 mm area. Fig. 7.8(a) and Fig. 7.8 (b) show the micrographs of the two chips. After flipchip bonding, the power and I/O pins were connected to the PCB by wire-bonding.
Fig. 7.9 shows the measured steady-state waveform of VO of the on-chip voltage
regulator. The ripple voltage was lower than 50mV under the full-load condition (IO = 60mA)
Fig. 7.9. Measured waveforms of steady-state output voltages.
Fig. 7.10. Measured efficiency of voltage regulator vs. input voltage.
85
Fig. 7.11. Source files (top) and its corresponding display images (bottom) shown in the blue
micro display system.
and over different VIN. Fig. 7.10 shows the measured efficiency vs the input voltage under full
and half brightness conditions. The peak efficiency was 91% when VIN = 3.7V and the SC
converter was operating in the 1/1x mode. For the 3/2x and 4/3x modes, the efficiency over the
whole range was higher than 70%. The averaged efficiency over the input range is 78%. The
voltage regulator could deliver a maximum power of 216mW.
An Arduino DUE board is used to control the display images. Four examples are shown
in Fig. 7.11. With a 4-bit grayscale control, images can be clearly rendered. Only a few dead
pixels were observed, and the bonding yield rate is higher than 99.7%. It demonstrated that the
proposed micro display system has potentials for portable display applications which require
high performance, compact size and low cost.
7.7
Conclusions
A fully integrated AMLED micro display system is presented in this chapter. The on-
chip hybrid voltage regulator consists of a step-up switched-capacitor converter and a stepdown linear regulator. It is capable of operating at a wide input range of 2.7V to 4.2V with peak
efficiency of 91% average efficiency of higher than 78%, and the maximum output power is
216mW. An AMLED array with 36 × 64 pixels was fabricated and integrated with silicon chip
by using the flip-chip bonding technique. Pixel divers are also designed to accomplish 4-bit
grayscale control. By integrating the voltage regulator, the display system could be operated
simply using a lithium-ion (Li-ion) battery without any external components.
86
7.8
Reference
[Zhang 2012]
S. Zhang et al., “Directly color-tunable smart display based on a CMOS
controlled micro-LED array,” in Proc. IEEE Photon. Conf., Sep. 2012, pp.
435–436.
[Tsonev 2014]
D. Tsonev et al., “A 3-Gb/s single-LED OFDM-based wireless VLC link
using a gallium nitride μLED,” IEEE Photon. Technol. Lett., vol. 26, no.
7, pp. 637–640, Jan. 2014.
[Chong 2014]
W. C. Chong, et al., “1700 pixels per inch (PPI) passive-matrix micro-LED
display powered by ASIC,” in Proc. IEEE Compound Semicond. Integr.
Circuit Symp., Oct. 2014, pp. 1–4.
[Jiang 2015]
J. Jiang, et al., “A 2-/3-phase fully integrated switched-capacitor DC-DC
converter in bulk CMOS for energy-efficient digital circuits with 14%
efficiency improvement,” in Proc. IEEE Int. Solid-State Circuits Conf.,
Feb. 2015, pp. 366-367.
[TI 2015]
“TPS65632: Triple-Output AMOLED Display Power Supply,” Texas
Insturments Datasheet, Mar. 2015.
[Li 2016]
X. Li, et al., “Design and characterization of active matrix LED
microdisplays with embedded visible light communication transmitter,”
IEEE J. Lightw. Technol., vol. 34, no. 14, pp. 3449–3457, Jul. 2016.
[Liu 2016 I]
X. Liu et al., “Analysis and design considerations of integrated 3-level
buck converters,” IEEE Trans. Circuits Syst. I, vol. 63 no. 5, pp. 671-682,
May 2016.
[Liu 2016 II]
X. Liu, C. Huang, P. K. T. Mok “A 50MHz 5V 3W 90% efficiency 3-level
buck converter with real-time calibration and wide output range for fastDVS in 65nm CMOS,” IEEE Symp. VLSI Circuits, Jun. 2016, pp. 1-2.
[Lu 2017]
Y. Lu, J. Jiang, and W.-H. Ki, “A multiphase switched-capacitor DC–DC
converter ring with fast transient response and small ripple,” IEEE J. SolidState Circuits, vol. 52, no. 2, pp. 579–591, Feb. 2017.
[Jiang 2017]
J. Jiang, W.-H. Ki, and Y. Lu, “Digital 2-/3-phase switched capacitor
converter with ripple reduction and efficiency improvement”, IEEE J.
Solid-State Circuits, vol. 52, no. 7, July 2017.
87
88
Chapter 8
CONCLUSIONS AND FUTURE WORKS
8.1
Thesis Conclusions
In this thesis, several switched-capacitor converters designed for a variety of
applications are presented. First, the design challenges and motivation are introduced. Then a
literature review is given to provide an overview of many design techniques proposed in stateof-the-art works. In Chapter 3, a mathematical model that includes the parasitic capacitance is
proposed to help predict the output voltage and power efficiency of step-down SC converters.
The analytic results become more important when the converters are fully-integrated. The
simulation results verified the correctness of the model.
From Chapter 4 to Chapter 7, four SC converter designs that used in applications such
as low-voltage implantable devices, energy harvesting sources, application processors and
AMLED display systems, are presented. New topologies, design methodologies and control
techniques are proposed to overcome the challenges and fulfill the requirements in each
application.
In Chapter 4, a fully-integrated SC converter is designed for low-voltage implantable
devices. By introducing 3-phase operation, the very low voltage conversion ratio of 1/4x is
realized with good efficiency. The parasitic insensitive topology with built-in doubler to reduce
CW is also proposed, and parasitic loss is significantly reduced. The design is fabricated in a
65nm CMOS process, and the measurement results show an overall 14% efficiency
improvement and a high efficiency at the sub-/near-threshold region are achieved without using
advanced processes or sacrificing the current density.
In Chapter 5, to further explore the topologies with 3-phase operation, an SC converter
using 2 flying capacitors and 2-/3-phase operations is proposed. With two more VCRs, the
achieved maximum output voltage range over the input voltage range is up to 75.8%, and the
89
power conversion efficiency was improved by as much as 20% compared to 2-phase SC
converters. A digital adaptive ripple reduction scheme is also introduced to reduce the output
voltage ripple by as much as 4 times at light load. This converter is implemented using a digital
method, that is, by writing VHDL codes and then synthesizing the circuit automatically, so the
design complexity is reduced. The converter was fabricated in a 0.13 µm bulk CMOS
technology and was capable of operating at a wide input range of 1.6 V-3.3 V and a wide output
range of 0.5 V-3 V with 91% peak efficiency and delivered a maximum power of 250 mW.
In Chapter 6, a fully integrated dual-output SC converter with dynamic power-cell
allocation for application processors is presented. To reduce the power and area overhead, due
to the load imbalance, the power cells can be dynamically allocated to achieve the maximum
power density and efficiency. This work was fabricated in a 28nm CMOS process. The
converter achieved 83.3% peak efficiency and a maximum 100mA while maintaining
minimized cross regulation. The overall efficiency was improved by 4.8% than that without
allocation.
In Chapter 7, a fully integrated AMLED micro display system is presented. The on-chip
hybrid voltage regulator consists of a step-up switched-capacitor converter and a step-down
linear regulator. It is capable of operating at a wide input range of 2.7V to 4.2V with peak
efficiency of 91%, averaged efficiency of higher than 78%, and the maximum output power is
216mW. An AMLED array with 36 × 64 pixels was fabricated and integrated with silicon chip
by using the flip-chip bonding technique. By integrating the voltage regulator on the same chip,
the display system could be operated using a lithium-ion (Li-ion) battery without any external
components.
In general, this thesis proposed several methods to tackle the challenges of designing
fully-integrated SC converters. To generate more VCRs with fewer flying capacitors, 3-phase
operation is proposed and adopted to the designs in Chapter 4 and Chapter 5. Average efficiency
is improved by having extra VCRs without consuming more system resources. To increase
system efficiency, a parasitic insensitive topology and high-voltage biasing technique is
proposed in Chapter 4. Parasitic loss is significantly reduced. An adaptive loading allocation is
proposed to enhance the power efficiency, and the technique can be employed in multi-core
processor applications (Chapter 6). To further reduce the voltage ripple, a distributed converter90
ring is built with cascading power cells to power up an AMLED display system. All the methods
have been confirmed by measurement results, and the performance are comparable to and/or
better than start-of-the-art SC converters in recent publications.
8.2
Future Works
A regulated switched-capacitor converter is a closed-loop system, and frequency
modulation is the most common method. To better control the converter, analysis of the loopgain frequency response should be performed. There are only a handful of papers that take up
this research topic. The conventional wisdom is that the power stage has only one pole, and
compensation methods could be used to improve the unity-gain bandwidth and thus the speed
of the transient response. However, detailed derivations have not been easily available.
Moreover, if a VCO is used in the loop, the frequency responses in the frequency domain and
the phase domain should also be analyzed. The analytic results could impose a clearer design
guideline for regulated SC converters.
Improving the line and load regulation is also an important research direction. Due to
the finite output resistance, SC converters usually have a poor load regulation. Similarly,
because of poor line regulation, in changing the input voltage, the output voltage could hardly
be equal to the ideally converted voltage. A conventional remedy is to switch to a higher VCR
when the output voltage is detected to be too low, but then this would result in poor efficiency.
A better solution would be to devise a method to achieve better line regulation.
91
APPENDIX
LIST OF PUBLICATIONS
Journal Publications
1.
J. Jiang, X. Liu, W. H. Ki, P. K. T. Mok and Y. Lu, “Design of Switched-Capacitor
Converter for Fully-Integrated AMLED Micro Display System”, IEEE Trans. Circuits Syst.
I: Regular Papers, to be submitted.
2.
J. Jiang, Y. Lu, W. H. Ki, S. P. U and R. P. Martins, “A Dual-Symmetrical-Output
Switched-Capacitor Converter With Dynamic Power Allocation”, in preparation.
3.
J. Jiang, Y. Lu, C. Huang, W. H. Ki and P. K. T. Mok, “A Fully-Integrated 2-/3-Phase
Switched-Capacitor Converter With Efficiency Improvement”, in preparation.
4.
J. Jiang, W. H. Ki and Y. Lu, “Digital 2-/3-Phase Switched-Capacitor Converter With
Ripple Reduction and Efficiency Improvement”, IEEE J. Solid-State Circuits, vol. 52, no.
7, pp. 1836–1848, Jul 2017.
5.
Z. Luo, Y. Lu, M. Huang, J. Jiang, S. W. Sin, S. P. U and R. P. Martins, “A Sub-1V 78nA Bandgap Reference with Curvature Compensation”, Microelectronics Journal, vol. 63,
pp. 35-40, May 2017.
6.
Y. Lu, J. Jiang and W. H. Ki, “A Multi-Phase Switched-Capacitor DC-DC Converter-Ring
with Fast Transient Response and Small Ripple”, IEEE J. Solid-State Circuits, vol. 52, no.
2, pp. 589-591, Feb 2017.
7.
X. Liu, P. K. T. Mok, J. Jiang and W. H. Ki, “Analysis and Design Considerations of
Integrated 3-Level Buck Converters”, IEEE Trans. Circuits Syst. I: Regular Papers, vol.
63, no. 5, pp. 671-682, May 2016.
Conference Publications
8.
J. Jiang, L. Sun, X. Zhang, S. H. Yuen, X. Li, W.-H. Ki, C. P. Yue and K. M. Lau, “FullyIntegrated AMLED Micro Display System With a Hybrid Voltage Regulator”, in Proc.
IEEE Asian Solid-State Circuits Conf. (A-SSCC), submitted.
9.
J. Jiang, Y. Lu, W. H. Ki, S. P. U and R. P. Martins, “A Dual-Symmetrical-Output
Switched-Capacitor Converter with Dynamic Power Cells and Minimized Cross
92
Regulation for Application Processors in 28nm CMOS”, in Proc. IEEE Intl. Solid-State
Circuits Conf. (ISSCC), Feb. 2017, pp. 344-345.
10. J. Jiang, Y. Lu, C. Huang, W. H. Ki and P. K. T. Mok, “A 2-/3-Phase Fully-Integrated
Switched-Capacitor DC-DC Converter in Bulk-CMOS for Energy-Efficient Digital
Circuits With 14% Efficiency Improvement”, in Proc. IEEE Intl. Solid-State Circuits Conf.
(ISSCC), Feb. 2015, pp. 366-367.
11. J. Jiang, Y. Lu and W. H. Ki, “A Digitally-Controlled 2-/3-Phase 6-Ratio SwitchedCapacitor DC-DC Converter with Adaptive Ripple Reduction and Efficiency
Improvements”, in Proc. 42nd European Solid-State Circuits Conference (ESSCIRC), Sep.
2016, pp. 441-444.
12. Y. Lu, J. Jiang, W. H. Ki, C. P. Yue, S. W. Sin, S. P. U and R. P. Martins, “A 123-Phase
DC-DC Converter-Ring with Fast-DVS for Microprocessors”, in Proc. IEEE International
Solid-State Circuits Conference (ISSCC), Feb. 2015, pp. 364-365.
13. J. Jiang, Y. Lu and W. H. Ki, “Analysis of Two-Phase On-Chip Step-Down Switched
Capacitor Power Converters”, in Proc IEEE Asia Pacific Conf. Circuits Syst. (APCCAS),
Nov. 2014, pp. 575-578.
14. X. Liu, J. Jiang, P. K. T. Mok, W. H. Ki, “Methods for Measuring Loop-Gain Function of
High-Frequency DC-DC Converters”, in Proc. IEEE Asia Pacific Conf. Circuits Syst.
(APCCAS), Oct. 2016, pp. 247-249.
15. Y. Lu, R. Yao, D. Huang, J. Su, J. Jiang and W. H. Ki, “A Low-Dropout Regulator with
Power Supply Rejection Improvement by Bandwidth-Zero Tracking”, in Proc. IEEE Asia
Pacific Conf. Circuits Syst. (APCCAS), Japan, Nov. 2014, pp. 105-180.
Patents
16. J. Jiang, et al., “Two-Phase, Three-Phase Reconfigurable Switched-Capacitor Power
Converter”, PCT/CN2017/075412, application filed.
17. J. Jiang, et al., “Switched Capacitor Converter”, PCT/EP2015/068324 (WO2016026724),
application filed.
18. J. Jiang, et al., “Driver Circuit with Extended Operation Range”, PCT/EP2015/053143,
(WO2015124514, CN106063099A, EP3111726A1, US20170055322 A1), application
filed.
93