USB 2.0 PHY Design Compatible to UTMI Specification POSTECH High Speed CMOS IC Lab. Nam Jang Jin http://asic.postech.ac.kr High Speed CMOS IC Lab. Contents • • • • • Introduction USB2.0 Device Architecture UTMI Specification Review Design Example: USB2.0 PHY Conclusions High Speed CMOS IC LAB 2/116 Introduction 병렬 인터페이스 표준 개발년도 Bit수 Max. Bandwidth Bus speed 용도 IDE 1986 8bits 1/3MB/s 1/3 Mbps HDD interface SCSI 1986 8bits 5MB/s 5Mbps PC interface ISA 1987 16bits 0.5/2.5MB/s 0.5/1.25Mbps 286PC/AT bus EISA 1988 32bits 33MB/s 8.25Mbps 386 PC bus VL 1.0 VL 2.0 1992 1994 32bits 64bits 132MB/s 167MB/s 33Mbps 50Mbps 486 PC bus PCI 1992 32bits 132/264MB/s 33/66Mbps Pentium PC bus IDE : Integrated Drive Electronics SCSI : Small Computer System Interface ISA : Industry Standard Architecture EISA: Extended Industry Standard Architecture VL : VESA(Video Electronics Standards Association) Local bus PCI : Peripheral Component Interconnect High Speed CMOS IC LAB 3/116 Introduction 직렬 인터페이스 표준 개발년도 동작 속도 특징 용도 RS232-C 1969 20kbps 50ft. Max length Pc와 모뎀 연결 ACCESS.bus . 100kbps 2-pair shielded 8m max length 저속의 I/O device 연결 IrDA 1993 2.4k/115.2kbps, 4Mbps peak wavelength (0.85 ~ 0.90um) PDA, notebook PC, printer 등의 데이터 전송 USB1.1 USB2.0 1994 2000 1.5/12Mbps 1.5/12/480Mbps 2-pair cable 5m max length PC와 주변기기 인터페이스 IEEE1394 IEEE1394.b 1995 . 100/200/400Mbps 0.8/1.6/3.2Gbps 2-pair twisted 4.6m max length 디지털 AV 용 인터페이스 IrDA : Infrared Data Association USB : Universal Serial Bus High Speed CMOS IC LAB 4/116 Introduction IEEE1394 vs. USB2.0 IEEE1394 USB2.0 동작 속도 100/200/400Mbps 1.5/12/480Mbps Royalty O X Promote group Apple Intel, Lucent, Compaq, Micro Soft, Phillips, NEC, Hewlett Packard PC 장착 Optional O Device driver 제품마다 driver 필요 Windows driver 지원 연결 방식 peer-to-peer Host-Device System 구현 Complex simple 비 고 Data 전송속도는 빠르지만, loyalty 문제 존재. 저속의 주변 장치 인터페이스로 사용하기에는 비 효율적 전송속도가 IEEE1394 수준으로 향상되어 고속 데이터 전송이 필요한 주변 장치 연결 에도 효율적인 수단 제공 High Speed CMOS IC LAB 5/116 Introduction IEEE1394 vs. USB2.0 1394 DV camcorders, D-VHS, HDTV, digital setset-top, digital home A/V USB (All Speeds) Printers, scanners, external storage, HID devices, mice, keyboard, digital still and PC video conf camera Consumer Digital A/V PC USB is …… PC Connectivity!! Firewire is …… Consumer Connectivity!! High Speed CMOS IC LAB 6/116 Introduction Application areas of USB2.0 Peripheral Desired BW Comments Conference Cameras 75-150Mbs Allows up to MPEG-2 quality without compression Scanners 50-100Mbs+ Higher resolution, more colors Printers 50-100Mbs+ Higher resolutions, more colors. Or elimination of line/page buffers allows lower cost External Storage Up to 240Mbs CD-RW, ZIP*, MO, Flash card reader, HDD, ... Broadband Connection 10-100Mbs High Speed CMOS IC LAB Cable, DSL, Ethernet, HPNA, ... 7/116 Introduction Key Features of USB2.0 특 징 내 용 Fully compatible to USB1.1 같은 cable/connector 사용, USB1.1 protocol 지원 Low Cost royalty free, simple hardware Hot pluggable 자동적으로 device 인식 및 환경 설정 Single connector type 주변기기 종류에 무관하게 한 종류의 connector 사용 127 device/USB Hub extention 사용하여 총 127개까지 device 연결 가능 Flexible speed modes Device 종류에 따라 적합한 동작 속도 선택 가능 Cable power 500uA suspend, 100mA unconfigured, 500mA configured No system resource required PC의 I/O, Memory address space 및 IRQ 필요 없음 Error detection/handling CRC 기능을 적용하여 데이터 전송 error 검출 Power conservation Suspend state(절전모드) 지원 Support four types of transfer Bulk, Isochronous, Interrupt, Control High Speed CMOS IC LAB 8/116 Contents • • • • • Introduction USB2.0 Device Architecture UTMI Specification Review Design Example: USB2.0 PHY Conclusions High Speed CMOS IC LAB 9/116 USB2.0 Device Architecture USB2.0 Topology Client Driver Client Driver System SW USB USB 2.0 2.0 Host Host Controller Controller High Speed Only HS HS Hub Hub USB USB 1.1 1.1 Device Device USB1.1 USB1.1 Hub Hub USB USB 2.0 2.0 Device Device USB USB 2.0 2.0 Device Device Full/Low Speed High Speed CMOS IC LAB 10/116 USB USB 1.1 1.1 Device Device (2 x 12Mb/s Capacity) USB2.0 Device Architecture USB2.0 Data Flow •Issues requests to USB driver via IRP(IO Request Packets) •Knows USB target devices’ characteristics •Set up transactions •Schedules transactions by building a series of transaction list High Speed CMOS IC LAB 11/116 USB2.0 Device Architecture USB2.0 Device Architecture D+ D- USB2.0 USB2.0 Transceiver Transceiver Serial Serial Interface Interface Engine Engine Protocol Protocol Controller Controller Transceiver Peripheral Component Integrated Microprocessor Custom ASIC Four Implementation Options!! High Speed CMOS IC LAB 12/116 Real World In/Out USB2.0 Device Architecture I/O Device Design Options System on a Chip of a USB 2.0 Function 1.1 SIE Serial Interface Engine Application Specific Logic USB backend (endpoint configuration, system bus interface, DMA etc.) HS PIE Parallel InterfaceEngine Micro-Processor Clock circuitry, system logic High Speed CMOS IC LAB 13/116 Rx: Tx: DLL, NRZI, BS, SYNC detect S-->P P-->S, BS, NRZI, SYNC gen. USB FS/LS Analog Transceiver USB D+ USB HS Analog Transceiver D- USB2.0 Device Architecture How To Make Architectural Partitioning? • • Purpose: Speed up the time to market for USB chips and USB application This can be achieved by – Reusing existing cores / blocks (from 1.x) – Reducing risks due to functional errors (through FPGA-based prototyping) – Making reusable IP cores (for different application environments) High Speed CMOS IC LAB 14/116 USB2.0 Device Architecture Implementation option 1 • Use a discrete UTMI transceiver – Has good TTM characteristics – Concentrate on product function FPGA FPGA FPGA Application Application Specific Specific Logic Logic Discrete IC IC MicroProcessor Processor USB backend Discrete IC 1.1 SIE Serial Interface Engine HS PIE Parallel Interface Engine USB USB 2.0 2.0 (FS/HS) (FS/HS) Analog Analog Transceiver Transceiver ++ Low -Level Low-Level Digital Digital Logic Logic ++ Clocking Clocking Standard Interface High Speed CMOS IC LAB 15/116 USB USB2.0 Device Architecture Implementation option 1 • • Has to be a parallel interface on function side 8-bit parallel interface difficult to connect to – Has to run at 60MHz – Hard to do with FPGAs – Pay attention to TxReady, Rx Valid & ValidH • 16-bit parallel interface severely pin constrained – Package cost increases compared to silicon cost – Easy to connect to (runs at 30MHz) High Speed CMOS IC LAB 16/116 USB2.0 Device Architecture Implementation option 2 • Use a generic device controller(UTM + SIE) – Has good TTM characteristics – Interfaces to product function with general purpose bus interface – Quickly enables existing product to USB 2.0 FPGA FPGA Application Application Specific Specific Logic Logic USB backend Discrete IC MicroProcessor Generic Interface High Speed CMOS IC LAB 1.1 SIE Serial Interface Engine HS PIE Parallel Interface Engine Generic Device Controller 17/116 USB USB 2.0 2.0 (FS/HS) (FS/HS) Analog Analog Transceiver Transceiver ++ Low -Level Low-Level Digital Digital Logic Logic ++ Clocking Clocking USB USB2.0 Device Architecture Implementation option 3 • Use an Enhanced Device Controller – Flexibility with integrated uP – Lower cost for high volume product FPGA FPGA Application Application Specific Specific Logic Logic Discrete IC MicroProcessor USB backend 1.1 SIE Serial Interface Engine HS PIE Parallel Interface Engine Enhanced Device Controller High Speed CMOS IC LAB 18/116 USB USB 2.0 2.0 (FS/HS) (FS/HS) Analog Analog Transceiver Transceiver ++ Low -Level Low-Level Digital Digital Logic Logic ++ Clocking Clocking USB USB2.0 Device Architecture Implementation option 4 • Full ASIC design – Longer design/qualification times – Lowest cost for high volume product ASIC FPGA FPGA Application Application Specific Specific Logic Logic Discrete IC MicroProcessor High Speed CMOS IC LAB USB backend 1.1 SIE Serial Interface Engine HS PIE Parallel Interface Engine 19/116 USB USB 2.0 2.0 (FS/HS) (FS/HS) Analog Analog Transceiver Transceiver ++ Low -Level Low-Level Digital Digital Logic Logic ++ Clocking Clocking USB USB2.0 Device Architecture Comparison of I/O Device Design PHY+SIE PHY + SIE + Internal uP ASIC MEDIUM MEDIUM High HIGH Time to market LONG MEDIUM SHORT LONG NRE costs LOW MEDIUM High HIGH Parts cost MEDIUM MEDIUM MEDIUM LOW Pin count HIGH MEDIUM LOW LOW Design effort High Speed CMOS IC LAB External PHY 20/116 USB2.0 Device Architecture Decision points for Mass Production • When to use Integrated ASIC/ASSP – Minimum board part count is important – Familiar with ASIC/ASSP design flows – Function can be added to existing ASIC/ASSP • When to use Standalone Transceiver – If integration risk is high – Gives added debug points of observation – Volume may not justify integrated solution ASSP:Application Specific Standard Product High Speed CMOS IC LAB 21/116 USB2.0 Device Architecture USB2.0 Cable Assembles Upstream High Speed CMOS IC LAB Downstream 22/116 USB2.0 Device Architecture USB2.0 Cable Spec • • • • • Propagation delay skew < 100 ps Attenuation spec extended to 400 Mhz Shield resistance specified Delay per cable <26 ns; delay per m < 5.2 ns Zdiff - 90 ohms +/- 15%, Zcm - 30 ohms +/- 15% Frequency(MHz) Attenuation(dB/cable) 8 ~ 12 0.67 12 ~ 24 0.95 48 ~ 96 1.90 96 ~ 200 3.20 200 ~ 400 5.80 High Speed CMOS IC LAB 23/116 Contents • • • Introduction USB2.0 Device Architecture UTMI Specification Review – Block Level Descriptions – Signal Definitions – Macrocell Functions • • Design Example: USB2.0 PHY Conclusions High Speed CMOS IC LAB 24/116 UTMI Specification Block Level Descriptions UTMI Functional Block Diagram DP HS XCVR RCV HS DLL EBUF M U Status/ control To Bus NRZI Decoder X Receive State Machine Xmit Bit unStuffer Rx Shift Reg Rx Hold Reg Dout Tx Shift Reg Tx Hold Reg Din To SIE DM FS XCVR RCV FSDLL /CDR Transmit State Machine Status/ control NRZI Encoder Xmit Analog Front_End External Crystal Bit Stuffer CLK Clock Multiplier Control Logic High Speed CMOS IC LAB 25/116 Control UTMI Specification Block Level Descriptions UTMI Main Features Supports HS/FS, FS Only, LS Only 8 or 16bits parallel interface to SIE SYNC/EOP generation and checking Data/clock recovery from serial data stream Bit stuffing/unstuffing, bit stuff error detection Supports low level protocol Resume assertion/detection, Reset detection, Suspend detection Speed detection signaling Ability to switch between FS and HS data transmission Supports USB2.0 Test mode High Speed CMOS IC LAB 26/116 UTMI Specification Block Level Descriptions Analog Front End +3.3V Rpu_Enable HS_Drive_Enable HS_Data_Input LS/FS_Data_Input Single_Ended_Zero LS/FS_Driver_Output_Enable High Speed Current Driver Legacy Driver HS Differential Data Receiver Squelch Transmission Envelope Detector HS_Disconnect Disconnection Envelope Detector FS/LS Diff._Receiver_Output Legacy Data Receiver SE_Data-_Receiver_Output High Speed CMOS IC LAB Rpu Rs HS_Diff._Receiver_Output SE_Data+_Receiver_Output Rs Single Ended Receivers 27/116 Data+ Data- UTMI Specification Block Level Descriptions High Speed Differential Current Driver High Speed Signaling Current High Speed Signaling Current 17.78ma RTERM 45Ohm Data+ DataZo=90Ohm, differential High Speed Differential Receiver High Speed CMOS IC LAB RTERM 45Ohm High Speed Differential Receiver 28/116 UTMI Specification Block Level Descriptions Source /Load Termination • • Use of terminations at source and load enable high signal integrity Reflection coefficient = (RT - Z0) / (RT + Z0) Example: 1. Z0 = 52 Ohms, RT = 40 Ohms Î reflection coefficient = -13% : source terminated link: 13% additive/subtractive ISI 존재 2. Both source and load terminations with 40 Ohms Î the effect is reduced to (13%)2, or 1.7% : Double terminations reduce the effects of connector and board related discontinuities High Speed CMOS IC LAB 29/116 UTMI Specification Block Level Descriptions USB2.0 Dual Termination Single Termination • • Dual Termination Simulation assumes ideal transceivers and terminations 2.7X increase in eye opening, 2.7X decrease in jitter Dual Termination Makes USB 2.0 Speeds Possible on USB 1.X Cable Assemblies High Speed CMOS IC LAB 30/116 UTMI Specification Block Level Descriptions Termination Scheme • • • Full-speed drivers asserting SE0 look like resistance to ground ZDRV + RS = 45 Ohms, +/- 10% RS may be integrated on-die or placed off-chip High Speed Signaling Current Full Speed Drivers Provide Termination Levels Rs Z DRV Z DRV DataRs High Speed Differential Receiver High Speed CMOS IC LAB Data+ 31/116 UTMI Specification Block Level Descriptions Speed Selection +3.3V Rpu = 1.5K Rpu_Enable D+ D- • • HS mode : RPU is disconnected It is recommended that switching elements be attached to both lines to achieve balanced parasitics High Speed CMOS IC LAB 32/116 UTMI Specification Block Level Descriptions High Speed Differential Receiver Data+ Data+ Data Data-- • • • Required to receive differential signaling with amplitude as small as +/- 200mV Guideline: Tolerant of common mode voltages from –50mV to +500mV Reception of data is qualified by envelope detection High Speed CMOS IC LAB 33/116 UTMI Specification Block Level Descriptions Transmission Envelope Detector Differential !Squelch • • • • • Squelch when differential amplitude is < 100mV !Squelch when differential amplitude is > 150mV Must incorporate filtering to prevent indication of Squelch during crossover Should react in less than 4 bit times Guideline: Tolerant of common mode voltages from –50mV to +600mV High Speed CMOS IC LAB 34/116 UTMI Specification Block Level Descriptions Disconnection Envelope Detector Disconnection Threshold Detector Disconnect Detection Q D Clocked During Last Byte of uSOF EOP • • • Disconnect threshold detector goes high when signals above disconnect threshold(575mV) are detected Output is sampled during last 8 bits of 40 bit uSOF EOP This prevents spurious disconnect detection in the presence of allowable signaling overshoot High Speed CMOS IC LAB 35/116 UTMI Specification Block Level Descriptions High-speed Bus States/Levels Idle State High speed termination, but no signaling current being driven, Soft SE0 Squelch State Amplitude of differential voltage is below Squelch threshold(Vsq=125mV) J, K State High-speed signaling levels. Current driven into D+ or D- with High speed terminations ChIRP J, K Current driven to D+ or D- with Full speed termination Disconnect Amplitude of differential voltage is above Disconnect threshold(Vdis=575mV), due to device terminations being removed High Speed CMOS IC LAB 36/116 UTMI Specification Block Level Descriptions Clock Multiplier Generates internal clocks and system clock(CLK:30MHz) for Macrocell and SIE Clock accuracy Î +/- 500ppm HS / FS operation 9 HS mode (8bit Interface) - CLK is 60MHz 9 FS mode(8bit Interface) - 40 CLK cycles per byte time(5 CLK cycles per FS bit time) - No changes in CLK freq. when UTMI is switched between HS to FS HS DLL(High Speed Delay Line PLL) HS DLL extracts clock and data from the data received over the USB2.0 interface High Speed CMOS IC LAB 37/116 UTMI Specification Block Level Descriptions Elasticity Buffer • EB accounts for clock differences between Rcv and Xmit – +/- 500 ppm + jitter Î +/- 12 bits 9 1K byte packet Æ 9644 bits Æ +/- 10 bits 9 Timing margin (including host jitter) Æ +/- 2 bits – EB size needs at least 24 bits to prevent over/underflow 9 Xmit clock may be slower or faster than Rcv clock 9 Xmit starts when EB has at least 12 bits – Resync during interpacket gap EB Size Must Account for Clock Accuracy and Host Jitter MUX • Connect the data from the HS or FS receivers to the shared receive logic • Selected by XcvrSelect input High Speed CMOS IC LAB 38/116 UTMI Specification Block Level Descriptions NRZI Encoder • Same encoding as LS and FS modes • 데이터 ‘0’ : transition, 데이터 ‘1’ : no transition Bit Stuffer • ‘1’ 이 연속으로 6번 반복되면 ‘0’ 을 한 bit 강제로 추가 Î Data rate mismatch 문제 발생 • • • • • • 8번의 stuffing 발생시 한 CLK 동안 data 전송을 중지 수신단 DLL의 클럭 정보 유지가 목적 SYNC pattern(H’8000) 시작 시점에서 부터, bit stuffing 이 시작 SYNC pattern 의 마지막 bit인 ‘1’부터, counting 됨 HS mode : EOP(H’0xFE) 의 경우는 bit stuffing 하지 않음 FS mode : 예외 없이 항상 적용됨 High Speed CMOS IC LAB 39/116 UTMI Specification Block Level Descriptions Data Encoding Sequence Data Rate Mismatch should be controlled!! Raw Data Packet data Sync Pattern Stuffed Bit Bit Stuffed Data Packet data Sync Pattern Six Ones Encoded Data Idle High Speed CMOS IC LAB Packet data Sync Pattern 40/116 UTMI Specification Block Level Descriptions Tx Shift/Hold Register Transmit Error Reporting • FS mode: buffer under_run등의 이유로 전송이 불가능하면, 강제로 bit stuffing error를 유발시켜서 전송을 중단시킨다 ÎSIE가 OpMode를 (2:Disable Bit Stuffing)로 전환시키고, 최소 1 byte 동안 ‘0’을 인가 • HS mode: 전송 중 error 발생시, SIE는 CRC의 complemented version을 전송 High Speed CMOS IC LAB 41/116 UTMI Specification Block Level Descriptions NRZI Decoder • • Same decoding as LS and FS modes 한 주기 이전 데이터와 현재 데이터가 같으면 ‘1’, 다르면 ‘0’ 출력 Bit unStuffer • 추가된 ‘0’을 수신 data stream에서 제거 • • Î Rate Mismatch 발생 8번 ‘0’을 제거 시, 1 CLK 동안 데이터 수신 중지 Bit stuff error 검출 - FS mode: RXError 신호 발생 시킴 HS mode: EOP 신호로 간주함. RXError 신호 발생되지 않음. High Speed CMOS IC LAB 42/116 UTMI Specification Block Level Descriptions Rx Shift/Hold Register Receive Error Reporting • Possible sources of receive error - Bit stuff error during FS mode - Elasticity buffer overrun/underun - Loss of Sync by the DLL - EOP not on a byte boundary High Speed CMOS IC LAB 43/116 Contents • • • Introduction USB2.0 Device Architecture UTMI Specification Review – Block Level Descriptions – Signal Definitions – Macrocell Functions • • Design Example: USB2.0 PHY Conclusions High Speed CMOS IC LAB 44/116 UTMI Specification Signal Definitions System Interface Signals Symbol CLK Type O Description System Clock • +/- 500ppm for freq. & 50 +/- 5% duty cycle • No transition of ‘CLK’ should occur until it is ‘usable’ • CLK_Usable: defined as a frequency accuracy of +/-10% 60MHz - HS/FS, 8bit interface, 30MHz - HS/FS, 16bit interface 48MHz - FS Only, 8bit interface, 6MHz - LS Only, 8bit interface Reset I Reset all state machine in the UTM XcvrSelect I Transceiver Select 0: HS mode, 1: FS mode • Selects the receiver – source for MUX block • Selects HS or FS Driver • Switch internal UTM clock to shared logic High Speed CMOS IC LAB 45/116 UTMI Specification Signal Definitions System Interface Signals Symbol Type Description TermSelect I Termination Select 0: HS mode, FS driver is forced to assert an SE0 1: FS mode, 1.5K pull-up on to the DP signal SuspendM I 0: Power down mode. Term_Select must always be in FS mode LineState[1:0] [DM:DP] O They directly reflect the current state of DP[0] and DM[1] signals. 0 - SE0 1 – J state 2 – K state 3 – SE1 OpMode[1:0] [op1:op0] I These signals select between various operational modes 0 – normal operation 1 – non driving 2 – Disable bit stuffing and NRZI encoding 3 – Reserved High Speed CMOS IC LAB 46/116 UTMI Specification Signal Definitions Line states • Used by the SIE for detecting RESET, Speed signaling, Packet timing, and to transition from one behavior to another • Synchronization - To minimize unwanted transitions to the SIE CLK_Usable=‘1’ Î LineState 는 CLK에 동기 CLK_Usable=‘0’ Î LineState 는 DP/DM 신호의 조합 • Signaling Levels - FS mode, LineState 는 Single Ended Receiver의 출력 HS mode, LineState 는 HS differential Receiver의 출력 To minimize unwanted transitions : In HS mode, Squelch can be used to force LineState to a J state ( LineState is always ‘J’ whenever a packet is on the USB ) : Chirp mode, LineState 는 HS differential Receiver의 출력 High Speed CMOS IC LAB 47/116 UTMI Specification Signal Definitions Line states • BUS Packet Timing - SIE : Packet 의 시작과 끝의 판별을 위해 ‘LineState’ 이용 HS mode (XcvrSelect & TermSelect =‘0’) : Idle state(SE0) to non-Idle state(J or K) : packet 시작 : non-Idle state(J or K) to Idle stste(SE0) : packet 끝 - FS mode(XcvrSelect & TermSelect =‘1’) : Idle state(J state) to K state : packet 시작 : SE0 to J state : packet 끝 High Speed CMOS IC LAB 48/116 UTMI Specification Signal Definitions Line states Mode Full speed High speed Chirp Invalid XcvrSelect 1 0 0 1 TermSelect 1 0 1 0 SE0 SE0 Squelch Squelch Invalid J state J !Squelch !Squelch & HS Differential Receiver Output Invalid Invalid Invalid Line State K state K Invalid !Squelch & HS Differential Receiver Output SE1 SE1 Invalid Invalid High Speed CMOS IC LAB 49/116 UTMI Specification Signal Definitions UTM Operational Mode • • Controlled by OpMode[1:0] signal from SIE Normal Operation(OpMode=0) – Standard encoding and decoding of serial stream • Non-Driving(OpMode=1) – Tri-states all transmitters and termination on the bus • Unencoded Data (OpMode=2, needed for test modes) – Disable Bit Stuffing and NRZI encoding – Stop to generate SYNC/EOP pattern – HS Chirp signaling(speed mode detection) High Speed CMOS IC LAB 50/116 UTMI Specification Signal Definitions Data Interface Signals Symbol Type DataBus16_8 I 1 : 16bit interface, CLK=30MHz 0 : 8bit interface, CLK=60MHz DataIn[0:15] I DataBus16_8 = 1 : low byte 8bit interface DataBus16_8 = 0 : 16bit interface Txvalid I Low byte DataIn is valid. 전송 패킷의 시작과 끝을 표시. ‘1’ : SYNC 패턴 생성 ‘0’ : EOP 패턴 생성 TxvalidH I DataBus16_8=1 Î high byte DataIn is valid O Packet Flow Control Signal ‘1’ : SIE로 부터 CLK에 동기된 데이터를 TX Holding Register에 loading ‘0’ : SIE는 이전 데이터를 DataIn Bus에 hold 함 8번 bit stuffing 발생시 한 CLK동안 ‘Low’ 유지 Txready High Speed CMOS IC LAB Description 51/116 UTMI Specification Signal Definitions Data Interface Signals Symbol Type DataOut[0:15] O DataBus16_8 = 1 : low byte 8bit interface DataBus16_8 = 0 : 16bit interface O 수신 데이터의 시작과 끝 표시 SYNC 검출 Î ‘1’ Rxerr/EOP 검출 Î ‘0’ HS mode : Idle 상태 검출 후 3~8 CLK 이내에 반드시 ‘Low’ 연속된 수신 패킷 사이에서 최소 1 CLK 동안 ‘Low’ 유지 FS mode : Idle 상태 검출 후 1~2 CLK 이내에 반드시 ‘Low’ 연속된 수신 패킷 사이에서 최소 4 CLK 동안 ‘Low’ 유지 Rxvalid O Low byte DataOut is valid Packet Flow Control Signal 8번 bit unstuff 발생시 1 CLK 동안 ‘Low’ RxvalidH O DataBus16_8=1 Î high byte DataOut is valid Rxerr O Indicates that a receive error has been detected Rxactive High Speed CMOS IC LAB Description 52/116 UTMI Specification Signal Definitions Interface Options 8-Bit Interface DataIn(0-7) TXValid 16-Bit Interface DataIn(8-15) DataIn(0-7) DataOut(0-7) TXReady TXValid TXValidH RXActive RXValid Reset SusepsndM XcvrSelect TermSelect OpMode(0-1) High Speed CMOS IC LAB DataOut(8-15) DataOut(0-7) TXReady RXActive CLK RXError DP DM LineState(0-1) DataBus16_8 RXValid RXValidH Reset SusepsndM CLK RXError XcvrSelect TermSelect DP DM OpMode(0-1) 53/116 LineState(0-1) Contents • • • Introduction USB2.0 Device Architecture UTMI Specification Review – Block Level Descriptions – Signal Definitions – Macrocell Functions • • Design Example: USB2.0 PHY Conclusions High Speed CMOS IC LAB 54/116 UTMI Specification Macrocell Functions Macrocell Functions • Packet Engine – Automatically handles SYNC Pattern and EOP • Flow Control – Compensates for Bit Stuffing and Data Rate Tolerance • Primitives for Full Protocol Support – – – – – • • • Resume Assertion Resume Detection Suspend Detection Reset Detection HS Detection Handshake Speed Switching Clock Generation Power Control High Speed CMOS IC LAB 55/116 UTMI Specification Macrocell Functions Packet Engine- Transmit • • • Automatically handles SYNC Pattern and EOP TXValid - Frames Packet TXReady - Provides Flow Control CLK TXValid DataIn(7:0) PID Data Data Data Data CRC CRC TXReady DP/DM High Speed CMOS IC LAB SYNC PID Data 56/116 Data Data Data CRC CRC EOP UTMI Specification Macrocell Functions Packet Engine- Receive • • RXActive - Frames Packet RXValid - Provides Flow Control CLK DP/DM SYNC PID Data Data EOP RXActive RXValid DataOut(7:0) High Speed CMOS IC LAB PID Data Data 57/116 UTMI Specification Macrocell Functions Flow Control-Transmit • 8번의 bit-stuff 발생시 one-clock 동안 데이터 전송이 중지 CLK TxValid DataIn(7:0) Invalid Data Data Inv Data Data Data Data TxReady High Speed CMOS IC LAB 58/116 Inv Data CRC CRC UTMI Specification Macrocell Functions Flow Control-Receive • 8번의 bit-unstuff 발생시 one-clock 동안 데이터 전송이 중지 CLK RXActive DataOut(7:0) Invalid Data Data Inv Data Data Data Data RXValid High Speed CMOS IC LAB 59/116 Inv Data CRC CRC UTMI Specification Macrocell Functions Protocol primitive support • • • • • Resume Assertion Resume Detection Suspend Detection Reset Detection HS Detection Handshake High Speed CMOS IC LAB 60/116 UTMI Specification Macrocell Functions SE0 Handling • SE0 Types – Soft SE0 : DP and DM lines are pulled down by 15K Rpd – Driven SE0 : pulled down by 45Ohm Rs • SE0 Handling – FS/LS 9 Idle : J state 9 EOP : SE0 for 2 low-speed bit time (<1.3us) 9 Reset : SE0 ( > 2.5us) – HS 9 Idle : Soft SE0 , Rpu 연결 시 ‘J’ state로 변화(Suspend Mode Detection) 9 Idle/Reset : Driven SE0, Rpu 연결해도 여전히 SE0 유지(Reset Detection) High Speed CMOS IC LAB 61/116 UTMI Specification Macrocell Functions Resume Assertion • • • Place Macrocell in “Disable Bit Stuffing and NRZI encoding” mode Transmit ‘0’ data for K’s (‘1’ data for J’s) Wait for SE0 T0 T0< T1 <10ms T1+1ms < T2 < T1 + 15ms T3 = T1 + 20ms SuspendM T4=T3+1.33us XcvrSelect & TermSelect OpMode Mode 0 Mode 2 Mode 0 TXValid DP/DM FS idle(‘J’) FS K FS Mode High Speed CMOS IC LAB 62/116 SE0 HS idle(SE0) Downstream port assert SE0 HS Mode UTMI Specification Macrocell Functions Resume Detection • Listen to LineState • Use J to K transition to disable SuspendM • Enter HS mode after K to SE0 transition – Assert XcvrSelect and TermSelect – Assume the device was in HS mode before the suspend 20ms 1.25us SuspendM XcvrSelect TermSelect Mode 0 OpMode LineState FS idle(‘J’) FS K FS Mode High Speed CMOS IC LAB 63/116 SE0 HS idle(SE0) HS Mode UTMI Specification Macrocell Functions Suspend Detection • • • Watch LineState for 3ms of inactivity (SE0) Switch to FS mode If J asserted, then enter Suspend State – Assert SuspendM T0 3~3.125ms T4=T0+10ms T1 100~875us T2 SuspendM Xcvr Select Term Select LineState Soft SE0 ‘J’ State Last Activity High Speed CMOS IC LAB 64/116 Transceiver suspended UTMI Specification Macrocell Functions DC Condition during Suspend(Soft SE0) VTERM (3.3 +/- 0.3 V) RPU (1.5k +/- 5%) - DC Voltage at D+/D VD- = 0V VD + = VTERM ⋅ D+ lines: Z HSDRV || R PD ≈ 0V R PU + Z HSDRV || R PD - FS Mode 전환 후 DOFF ZHSDRV OFF VD + = VTERM ⋅ R PD (15k +/- 5%) Host/Hub High Speed CMOS IC LAB VD- = 0V Device 65/116 R PD ≈ 3.3V R PU + R PD -FS 전환했을 경우, Line State = ‘J’ Î Suspend 로 간주 UTMI Specification Macrocell Functions Reset Detection • SE0 is the Idle state in HS mode • After 3ms of inactivity (SE0) switch to FS mode • If SE0 asserted then enter Reset – Initiate HS Handshake Detection T0 T1 3~3.125ms T2 HS Handshake Detection Process 100~875us Xcvr Select Term Select DP/DM Last Activity High Speed CMOS IC LAB Driven SE0 Driven SE0 ’SE0' State SE0 66/116 UTMI Specification Macrocell Functions DC Condition during RESET(Driven SE0) VTERM (3.3 +/- 0.3 V) RPU (1.5k +/- 5%) - DC Voltage at D+/D - lines: VD- = 0V VD + = VTERM ⋅ Z HSDRV || R PD ≈ 0V R PU + Z HSDRV || R PD D+ - VD+ (min, typ, max) = (79, 96, 120) mV DON ZHSDRV (45 ohm +/- 10%) OFF RPD (15k +/- 5%) Host/Hub High Speed CMOS IC LAB VTERM = 3.3 ± 0.3V, Z HSDRV = 45Ω ± 10% R PU = 1.5kΩ ± 5% , R PD = 15kΩ ± 5% - This offset voltage is termed “Tiny- J” Device 67/116 -FS Mode 전환 후에도, 여전히 SE0 State Î Reset으로 간주 UTMI Specification Macrocell Functions High Speed Detection Handshake • Turn on HS Transceivers with FS Terminations • Drive a “Chirp K” • Detect Chirp K/J Sequence from the Hub • Assert HS Terminations T0 T1<6ms T9=T0+10ms HS Detection Handshake Process XcvrSelect TermSelect TXValid DP/DM Chirp K SE0 K Device Chirp High Speed CMOS IC LAB J K K J J K Hub Chirp Sequence HS Mode 68/116 J SE0 SOF UTMI Specification Macrocell Functions High Speed Detection Handshake • • Signaling during reset with the high-speed driver in a full-speed configuration Chirp K/J to distinguish from normal HS/FS/LS signaling Device RPU D+ Hub RS Chirp K Generated by HS Device IHS RS D- High Speed CMOS IC LAB 69/116 UTMI Specification Macrocell Functions High Speed Detection Handshake • • : -0.9 – -0.5 V (differential) : 0.7 – 1.1 V (differential) Chirp K Chirp J RPU RS IHS Chirp K Generated by HS Hub RS D- High Speed CMOS IC LAB 70/116 Device Hub D+ UTMI Specification Macrocell Functions Voltage Level during Speed Signaling D+ 3.0 V 900 mV 800 mV 800 mV Squelch: 100-150 mV differential Tiny J (96 ~ 120mV) D- 0 mV FS Idle FS SE0 Chirp K "Tiny J" High Speed CMOS IC LAB 71/116 FS SE0 Alternating Chirp K & J FS SE0 HS Idle UTMI Specification Macrocell Functions Voltage Level during Speed Signaling Tiny-J level Squelch threshold 150 mV 120 mV 100 mV 79 mV High Speed CMOS IC LAB 72/116 UTMI Specification Macrocell Functions Host/Hub should ignore the Tiny-J • • • During reset, hub/host is looking for a chirp-K Potentially, it can receive a valid chirp-J Hub/host should ignore this chirp-J – It should not reject or decide that the attached device is not highspeed capable at this time Transceiver Design Guidelines • To ensure that tiny-J is not interpreted as a valid J – ensure squelch threshold higher than tiny-J, by: – Increasing (doubling) squelch threshold during chirping period (will this violate spec?) OR – Designing squelch threshold voltage to be 120-150 mV (tough?, no noise margin) High Speed CMOS IC LAB 73/116 UTMI Specification Macrocell Functions Clock Generation • • • • Macrocell supplies clocks to the SIE +/- 500ppm for freq. & 50 +/- 5% duty cycle No transition of ‘CLK’ should occur until it is ‘usable’ Frequency depends on implementation – HS/FS 9 60 MHz 8-bit uni-directional 9 30 MHz 16-bit uni- or bi-directional – FS Only 9 48 MHz 8-bit uni-directional – LS Only 9 6 MHz 8-bit uni-directional High Speed CMOS IC LAB 74/116 UTMI Specification Macrocell Functions Power Control • SuspendM signal from SIE – Draws 500uA stand-by current – Shuts down clocks – Maintains terminations • Vendor determined Drive Current Control – Enabled during transmits – Enabled by receives – Always on HS_Data_Driver_Input DP DM HS_Current_Source_Enable HS_Drive_Enable High-speed Current Driver High Speed CMOS IC LAB 75/116 UTMI Specification Macrocell Functions Data Encoding Examples: FS SYNC High Speed CMOS IC LAB 76/116 UTMI Specification Macrocell Functions Data Encoding Examples: FS EOP High Speed CMOS IC LAB 77/116 UTMI Specification Macrocell Functions Data Encoding Examples: HS SYNC High Speed CMOS IC LAB 78/116 UTMI Specification Macrocell Functions Data Encoding Examples: HS EOP High Speed CMOS IC LAB 79/116 Contents • • • • • Introduction USB2.0 Device Architecture UTMI Specification Review Design Example: USB2.0 PHY Conclusions High Speed CMOS IC LAB 80/116 Design Examples Top Block Diagram Device Hardware Device Device Specific Specific Logic Logic Serial SerialInterface InterfaceEngine Engine Endpoint Logic Endpoint Logic Endpoint Logic SIE Control Logic HS Interface (480MHz) NRZI Bit NRZI Bit Encoder Encoder Stuffer Stuffer DP To USB DM HSCDR Parallel Parallel to to Serial Serial 16 16 Elastic Buffer BIAS Osc (12MHz) M U X CONTROL Serial Serial NRZI Bit NRZI Bit 16 16 to to Decoder Decoder unstuffer unstuffer Parallel Parallel FSCDR FS Interface (12MHz) High Speed CMOS IC LAB USB 2.0 PC USB USB2.0 2.0 Transceiver Transceiver Shared Logic 81/116 To SIE Design Examples Main Features 16-bit unidirectional interface with 30MHz System Clock Supports 480Mbps High Speed and 12Mbps Full Speed Data rates Supports Low level Protocol(SYNC/EOP generation and detection) Bandgap Reference Bias generation Burst mode Clock Data Recovery with Elasticity Buffer NRZI encoding/decoding, Bit stuffing/unstuffing Supports the Primitive Protocol - Suspend detection, Resume Assertion, Resume Detection - Reset Detection, Speed mode signaling Supports for test modes defined in the USB2.0 specification High Speed CMOS IC LAB 82/116 Design Examples Chip Layout XCVR CDR 0.95mm Unstuffer Unstuffer STP STP codec codec Stuffer Stuffer PTS PTS FIFO 1.92mm High Speed CMOS IC LAB UTMI v1.03 Compatible 83/116 Anam0.25um process 120Pin TQFP Power: 220mW @ HS Tx Area : 1.8mm2 Design Examples Operation Mode OpMode [1:0] Xcvr 0 Term TxValid Hsoe Fsoe Rpu hterm 0 0 0 0 1 HS 수신 1 1 0 0 1 HS 송신 Nomal 1 10 비고 0 00 01 Mode X 0 0 0 0 1 0 FS 수신 1 0 1 1 0 FS 송신 X 1 0 0 0 Non driving 1 1 0 1 0 Force Chirp 0 0 0 1 0 Chirp 수신 1 X 1 High Speed CMOS IC LAB 84/116 Soft disconnection(Idle) Disable Bit_stuffing & NRZI encoding SYNC/EOP는 생성되지 않음. Design Examples Analog Front End Rpu_sel Hsoe Tx_Data Hterm Fsoe Tx_data +3.3V High Speed Current Driver Legacy Driver Rpu Hsrxd HS Differential Data Receiver Squelch Transmission Envelope Detector Fsrxd Legacy Data Receiver Sep Sen High Speed CMOS IC LAB Single Ended Receivers 85/116 Data+ Data- Design Examples Cable Modeling – Segmented T model • • • Cable skin effect losses are the dominant source of inter-symbol interference The following model is a 1ns section (T1 and T2 are 45 Ohms, 500ps) 26 sections cascaded are slightly more lossy than the USB 2.0 cable specification allows Left L1 T2 2.04n R1 L2 L3 L4 L5 L6 L7 1.41n 1.07n .928n .682n .727n .827n R2 R3 R4 R5 R6 .259 .273 .154 0 .068 .101 Frequency Specification dB Model dB 12 -0.67 -0.46842 25 -0.95 -0.89587 48 -1.35 -1.50408 100 -2.30 -2.50573 200 -3.20 -4.14796 400 -5.80 -6.79082 High Speed CMOS IC LAB -8.89569 86/116 Right R9 2.33 0 0 800 .97 T1 0 Design Examples Cable Modeling – W model • • 5m UTP USB cable 의 특성을 network analyzer로 measure W-전송선 모델로 fitting L0 C0 R0 G0 Rs Gd 172.125nH 85pF 0 0 2.5e-4Ohm 9e-12Mho wcp n=1 in 0 out 0 RLGCfile=para.rlc l=5 in L=5m High Speed CMOS IC LAB out 87/116 Design Examples HS mode equivalent loading diagram • • CHSLOAD < 10pF : die load=5pF, package load=5pF 40.5 Ω < ZDRV + RS < 49.5 Ω Chip Boundary Legacy Driver Output Impedance = ZDRV Rs Data+ Data- Rs USB Connector Reveivers, Reveivers, Rpu Rpu pull pull up, up, and and HS HS Driver Driver CHSLOAD High Speed CMOS IC LAB CHSLOAD 88/116 Design Examples USB Termination Scheme High Speed CMOS IC LAB 89/116 Design Examples Linearity of MOS Transistor High Speed CMOS IC LAB 90/116 Design Examples Impedance Control Scheme Io Io 20 x Io 17.78mA 10 x Io Vref=0.4V rs 10 x rs rext=450 10 x Io W High Speed CMOS IC LAB 10W 91/116 Design Examples High Speed Driver Va=0.4V W1 Io 20W1 W1 Vb 20 Io = 17.78mA dn dp rs rext=450 m5 rs1 rs2 10W2 W2 10 Io Vr High Speed CMOS IC LAB outn outp rext 92/116 Design Examples High Speed Driver Simulation Results W High Speed CMOS IC LAB T modeling 93/116 modeling Design Examples High Speed Differential Receiver OUT DP High Speed CMOS IC LAB DN 94/116 Design Examples Transmission Envelope Detector curerent mode schmitt trigger voltage mode schmitt trigger inp level shifter pp inn level shifter nn Vsq level shifter vr1 O1 One_shot GND level shifter vr2 High Speed CMOS IC LAB nmos R 95/116 squelch O2 C Design Examples Transmission Envelope Detector current mode schmitt trigger hysteresis level control I3 3 out 4 4 Ih Ih I1 vb1 nn pp vref High Speed CMOS IC LAB 96/116 vr1 vr2 Design Examples Transmission Envelope Detector Simulation Results 150mV High Speed CMOS IC LAB 100mV 97/116 Design Examples Clock Data Recovery • • • SYNC 패턴 입력 4bit 이내에 클럭/데이터 동기화가 요구됨 Tracking-style CDR - Low jitter - 구조가 간단 - Fast locking이 어려움 - No reference clock : DC 데이터 입력에 민감 Oversampling-style CDR - 양자화 jitter 존재 - 구조가 다소 복잡 - Fast locking이 어려움 - Reference clock : DC 데이터 입력에 둔감 High Speed CMOS IC LAB 98/116 Design Examples Clock Data Recovery • Burst-mode CDR – Instantaneous clock align to a incoming NRZ data sequence (normally within 1bit time) – Simple to implement – Require a reference clock 9 Insensitive to DC data input – Large data defendant jitter 9 Canceled by EB(Elasticity Buffer) followed by CDR – Usually applied to optical communication system requiring multi bit rates such as SONET, OFDM. High Speed CMOS IC LAB 99/116 Design Examples Clock Data Recovery Incoming Data From Analog Front_End D D F/F D1 VCO1 vctrl D2 VCO2 vctrl D VCO3 vctrl Clk1 recovered data to Elastic Buffer recovered clock Clk2 reference clock(12MHz) /40 Charge Pump D1 D2 Clk1 Clk2 recovered clock recovered data High Speed CMOS IC LAB Q 100/116 PFD Design Examples Lock Detector c0 D Q dff_reset q1 D Qb r reset 16 counter dff_reset reset q2 asm2 lock c90 c0 c90 reset counting q2 lock • No transition of ‘system clock’ until it is usable, where usable is defined as a frequency accuracy of +/- 10% • +/- 10% accuracy : 12MHz(80ns) 의 경우, 0.8ns/clock drift 하므로 10진 counter 필요 Î 16진 counter 사용 High Speed CMOS IC LAB 101/116 Design Examples CDR Simulation Results rec_data rec_clk o2 o1 hsrxd High Speed CMOS IC LAB 102/116 Design Examples Elasticity Buffer • 송신단 과 수신단 사이의 clock difference 보상 Î 24bit depth • CDR의 data defendant jitter 제거 • Pointer는 초기에 12번째에 setting Î Latency = 12 • Underun/overrun 은 RxError 발생 data_put (from CDR) clk_put control cell #1 clk_get full Full Detector cell #2 cell #24 ASM error control data_get (to digital block) Empty Detector High Speed CMOS IC LAB 103/116 empty Design Examples Line State Control Scheme • • • Synchronization - To minimize unwanted transitions to the SIE CLK_Usable=‘1’ Î LineState 는 CLK에 동기 CLK_Usable=‘0’ Î LineState 는 DP/DM 신호의 조합 Signaling Levels - FS mode, LineState 는 Single Ended Receiver의 출력 - HS mode, LineState 는 HS differential Receiver의 출력 Minimizing Transitions - HS mode, Squelch can be used to force LineState to a J state ( LineState is always J whenever a packet is on the USB ) (예외) Chirp mode, LineState 는 HS differential Receiver의 출력 High Speed CMOS IC LAB 104/116 Design Examples Line State Control Scheme vdd 0 jjmux2 vss lp2 0 1 0 sep 1 squelch 1 jjmux2 jjmux2 hsrxd 2 LP jjmux2 4 1 D Q 1 lp1 0 xcvr clk30 term lock 0 jjmux2 sen 3 1 5 jjmux2 1 vss D Q ln1 1 ln2 LN jjmux2 0 0 Xcvr Term Squelch LP LN 1 1 X Sep Sen 0 1 0 hsrxd hsrxdb 1 0 0 0 1 0 1 0 0 0 High Speed CMOS IC LAB 0 105/116 비고 Lock 이면, CLK30에 동기된 출력 Chirp K/J detection HS mode에서의 transition 최소화 Design Examples Test Setup Random Data Generator/ Pattern Generator Oscilloscope/ Logic Analyzer TP4 TP3 D D U U TT Transceiver TP2 USB Cable D D U U TT Transceiver A Connector B Connector Device Circuit Board High Speed CMOS IC LAB TP1 Hub / Motherboard 106/116 Design Examples HS mode Eye-opening Spec. TP1: Transmitter TP4: Receiver • Level1 : 475mV ~ 525mV • Level1 : 575mV • rise/fall time : 600ps • rise/fall time : 400ps • voltage margin : 300mV • voltage margin : 150mV • jitter spec : 200ps • jitter spec : 800ps High Speed CMOS IC LAB 107/116 Design Examples Output Driver Test Mode PRBS Pattern Generator txp In[15:0] Tx Transceiver Out[15:0] High Speed CMOS IC LAB FIFO 108/116 CDR Rx Cable Design Examples Eye-opening Test Results 2.5V 2.5V Full Speed Driver Output 300mV 1.8nS High Speed Driver Output High Speed CMOS IC LAB Full Speed Receiver Input 150mV 1.2nS High Speed Receiver Input 109/116 Design Examples CDR Test Mode txp In[15:0] Tx Transceiver Out[15:0] FIFO CDR PRBS Pattern Generator High Speed CMOS IC LAB 110/116 Rx Cable Design Examples CDR Data Pattern Test 입력 데이터 복원 클럭 복원 데이터 복원 데이터 수신데이터와 복원데이터 파형 High Speed CMOS IC LAB 복원된 데이터와 클럭의 timing 관계 111/116 Design Examples Digital Block Loop Back Test Mode External test clock Cable In[15:0] Tra Out[15:0] Rec High Speed CMOS IC LAB txp Tx FIFO 112/116 CDR Rx Cable Design Examples Digital Block Loop Back Test Results Full speed Mode Host 전송 Data Device 수신 Data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3FFC(x5);1234(x2);1F87; 431B; High Speed CMOS IC LAB 0 1 1 1 1 1 1 1 8000 ; SYNC FE ; EOP 3FFC(x5);1234(x2);1F87; 431B; 47A0;8C8D;FC12 113/116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 FE ; EOP 8000 ; SYNC 47A0;8C8D;FC12 Digital Block Loop Back Test Results Full speed Mode Host 전송 Data Device 수신 Data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8000 ; SYNC 7E3F;7F7E(x5);9249(x2);1F87; 431B; 47A0;8C8D;F2A6 High Speed CMOS IC LAB 0 1 1 1 1 1 1 1 FE ; EOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 8000 ; SYNC FE ; EOP 7E3F;7F7E(x5);9249(x2);1F87; FE1B; 47A0;8C8D;F2A6 114/116 Design Examples Design Spec. Comparison Cypress CY7C6800 Kawasaki KL5KUSB201 SMSC GT3100 POSTECH process 0.35um CMOS 0.18um CMOS 0.18um CMOS 0.18um CMOS supply 3.3V 3.3V/1.8V 3.3V/1.8V 3.3V/1.8V power 630mW 162mW 165mW 220mW 1.0625mm2 1.8mm2 core area - - package 56pin 80pin 64pin 120pin interface 16/8bit 16bit 16/8bit 16bit Isuspend 15uA 1uA 125uA 10uA termination On chip Off chip On chip On chip external Xstal 24MHz 48MHz 12MHz 12MHz High Speed CMOS IC LAB 115/116 Conclusions • • Brief USB2.0 System Review UTMI Spec. Overview with Design consideration – Block level 에서의 UTMI 구성 9 Analog Front End 설계 시 유의사항 9 각 블록의 Function 기술 – Interface Pin definition 및 설계 시 고려사항 9 Line State, Op Mode, Packet Flow Control Signal…. – UTM Main Function Review 9 SIE와의 데이터 인터페이스 timing 고려 9 Primitive Protocol에 대한 이해 • Design Examples – – – – System 구성 Cable Modeling Front_End 설계 방법 테스트 결과 High Speed CMOS IC LAB 116/116