A Design of a New Resistor String DAC for phones
applications in 130nm Technology
Fouad Farah, Mustapha El Alaoui ,Karim El Khadiri,
Hassan Qjidaa
Ahmed Lakhassassi
Electronics, Signals, Systems and Computer Science
Laboratory (LESSI)
Faculty of Sciences, Sidi Mohamed Ben Abbellah University,
Fez, Morocco
Fouad.farah@usmba.ac.ma
Department of Computer Science and Engineering
Abstract— This paper presents a design of a new resistor string
digital-to-analog converter (DAC) in 130-nm CMOS technology for
phones applications. The proposed DAC was designed with a
resistor string architecture for high frequency, high speed, high
accuracy and low glitches, optimized deglitch circuit is adopted for
the selection of resistor string. The layout occupies a small active
area of 32.80um x 46.90um in CMOS 130nm, the power
consumption is only 361.574 uW, the measured integral
nonlinearity (INL) and the measured differential nonlinearity
(DNL) respectively are ±0.00026LSB and ± 0.00034LSB.
CMOS process. Schematic simulation and Post-Layout
simulations are tabulated and the designed DAC's static
performance parameters such as Gain Error Integral NonLinearity (INL), Offset Error, Differential Non-Linearity
(DNL) with Power and Area of design are measured using
Cadence [1]-[2]-[3].
Keywords—Resistor string;
(DAC); phones applications.
Digital-to-Analog
Converter
I. INTRODUCTION
A device that converts discrete digital binary code into a
continuous varying analog signal. DAC is implemented as
integrated circuits. It is used in several fields, and specifically
in the applications of phone, LCD television and music
players [1].
The DAC converter is used in phones to convert a digital
audio signal into an analog audio signal, as we know We can't
hear a digital audio and ours phones can't store analog audio,
so the Audio signal is converted into a digital copy because it's
easier to compress and stored. Therefore, when we play our
music for example, it has to pass through a DAC to get the
analog signal.
The performance criteria of a DAC for a different
application is determined by tradeoff among 6 mains
parameters: Active area, cost, resolution, accuracy power
consumption, and finally speed. 3-bit Resistor String DAC is
formed of a series of resistors, which are connected to an
OPAMP buffer through an analog multiplexer. Based on the
digital inputs, the switch multiplexer selects the corresponding
voltage from the resistor string (which acts as voltage divider
within the referenced voltage range) and gives it to the Opamp
buffer, which simply buffers the signal to drive a high capacity
load.
Based on the inputs and design specifications, schematics
and layout for different blocks of DAC mentioned above are
designed in Cadence Custom IC Design Tools using 130-nm
Université du Québec en Outaouais (UQO)
B-2014, Pavillon Lucien-Brault, Canada
Ahmed.lakhssassi@uqo.ca
II.
CIRCUIT
DESIGN
The proposed 3-bit Resistor String DAC is shown in figure
1, which are connected to an OPAMP buffer through an
analog multiplexer. Based on the digital inputs, the switch
multiplexer selects the corresponding voltage from the
resistor string (which acts as voltage divider within the
referenced voltage range) and gives it to the Opamp buffer,
which simply buffers the signal to drive a high capacity
load.
The output of an ideal N-bit binary resistor string DAC is
given by:
(1)
Where ¨R is the mismatch error and Vi,ideal is:
(2)
Figure 1. Proposed 3-bits DAC structure
978-1-5386-4396-9/18/$31.00 ©2018 IEEE
As the same way we will calculate the others parameters using
these equations:
A. Two-Stage CMOS OPAMP Buffer
• First stage (Input Gain Stage):it is composed of
Transistors M1, M2, M3, M4 and M5. At this stage, the
current of transistor M1 is copied by the current mirror
[M3; M4] and subtracted by the differential peer [M1;
M2] from the current giving by transistor M2. The bias
current of the input differential pair is furnished by M5
(figure 2) [4].
•
•
Second stage (Common Source Gain Stage): it is
composed of the current sink load inverter [M6; M7], it
receives the signal from transistor M2 and buffer it via
transistor M6. Generally, this stage used to provide the
voltage gain and also to produce high output
resistance.
Biasing Circuit: A simple resistor divider circuit is
used to apply bias voltage to gate of M9
S3= (W / L) 3= I5 / (K‘3) [VDDíVin(max)í‫פ‬VT03‫(פ‬max)+VT1(min)]2
S3 = S4
gm1 = GB* Cc
gm2 = gm1
(4)
(5)
S2 = (g m2) 2 / K '2 I 5
S 1=S2
VDS5 (sat) =Vin(min)íVSSíI 5ȕ1íVT1(max)
(6)
B. D-Flip Flop
• The edge-triggered flip flop is composed of two D-type
level-triggered latches. Each Latch have tow
transmission gates and tow inverters. Both latches are
enabled with complementary clock signal: The second
slave latch is driving by the clock signal, while the
master latch is enabled by the complemented clock.
The master latch is transparent whilst the clock signal
is low, and the current value of the D input is
propagated to the input of the slave latch. Now, the
input transmission-gate of the slave latch is nonconducting. thus, the flip flop stores its current value
(figure 3).
Figure 2. Circuit diagram of an OPAMP Buffer
• Equations
Firstly, we need to choose the length of each component to
ensure constant modulation parameter and to have a good
matching for current mirrors.
L1 =L2 =480nm; L3 =L4= 480nm; L5 =L8= 360nm; L6 =L7
=L9= 120nm; W9= 160nm.
We will choose the minimum value of Cc for a phase margin
equal to 60°. This assumes that z • 10GB (Cc > (2.2/10) CL).
We choose:
Cc= 2.5*0.22*CL
CL = 1.25 pF
Cc = 0.6875 pF
Secondly, from the largest of the two values, we will calculate
the minimum value of the current I5.
I5 = SR. Cc
(2)
I3 = I4= I5 /2
(3)
Figure 3. Circuit diagram of a D-Flip Flop
C. Control Signals Logic
•
Control Logic block is realized as 3 to 6 Decoder,
which takes 3 Input bits and buffers out those signals
along with their complement signals. It has 3 D-Flip
Flop in Parallel in Parallel Out fashion. A
Transmission Gate is added to Clock Signal to
compensate the delay caused by Inverter component.
(figure 4).
The layout of our DAC has been designed using a 130-nm
CMOS technology. The active area is equal to 62.415um*
38.64um (figure 7).
The results, this DAC has one of the best power
efficiencies of published work. Moreover, it achieves the
lowest power consumption and a high speed, also this DAC
has a smallest active area.
Figure 4. Circuit diagram of a control signals logic
D. Resistor String Ladder
•
The design approach follows, determination of
suitable R value for the DAC, based on which Width
and Length of resistor is decided. The "W" and "L"
values determine the mismatch factor for the Resistor
String (figure 5). With R= 1.8109 Kȍ, W= 2.6 um,
L= 5.1 um and Mismatch Factor = 0.018.
Figure 7. Resistor String DAC Layout
IV. CONCLUSION
Figure 5. Circuit diagram of the resistor string ladder
III. SIMULATION RESULTS
The simulation and the analyses of the resistor string DAC
has been developed by cadence spectre simulations, with an
analog power supply equal to 1.2 V.
The output voltage of DAC and the voltage of each bit are
showing in figure 6.
A low cost, low size and low power effective 3-bit Resistor
String DAC has been designed and implemented in 130 nm
CMOS process. the results of the resistor string DAC are
presented as follows:
The measured integral nonlinearity (INL) is ±0.00026LSB, the
measured differential nonlinearity (DNL) is ± 0.00034LSB
and settling time less than 19.82 ns. The active area equal to
32.80um x 46.90um in CMOS 130nm.
ACKNOWLEDGMENT
This work was supported by: The National Center of
Scientific and Technical Research (CNRST Morocco) under
the PPR2 program.
Figure 6. output voltage of Resistor String DAC
REFERENCES
[1]
J.Wiknerand N. Tan, “Modeling of CMOS Digital-to-AnalogConverters
for Telecommunication," IEEETrans. Circuits Syst.ll,vo1.46, no. 5,
May1999.
[2] R.vandePlassche, CMOS Integrated Analog-to-Digital and Digital-to
Analog Converters. Kluwer Academic Publishers,2003.
[3] P.Jespers, Integrated Converters, D to A and A to D Architectures,
analysis
and
Simulation.
Oxford
Univer-sity
Press,200l.B.Razavi,Principles of data conversion system design. Wiley
IEEE Press,1995
[4] Anchal Verma, Deepak Sharma, Rajesh Kumar Singh and Mukul Kumar
Yadav“Design of Two-Stage CMOS Operational Amplifier”
International Journal of Emerging Technology and Advanced
Engineering Volume 3, Issue 12, December 2013
[5] JA Fisher, R Koch “A highly linear CMOS buffer amplifier ” - IEEE
Journal of Solid-State Circuits, 1987
[6] Mohd. Marufuzzaman, H. N. B. Rosly, M. B. I. Reaz, L. F. Rahman, H.
Hussain “Design of Low Power Linear Feedback Shift Register ” Journal
of Theoretical and Applied Information Technology. 20th March 2014.
Vol. 61 No.2.
[7] K.Doris.D. Leenaerts and A.van Roermund, “Mismatch-based timing
errors in current steering DACs” ISCAS, vo1.1 ,pp.I-977 980, May2003
[8] K. El khadiri and H. Qjidaa, “Design of a 5-bit 2Gsps CMOS DI A
Converter for DS-CDMA UWB transceivers,” in International
Conference on Multimedia Computing and Systems, pp. 1087 - 1090,
may 2012
[9] MM Mano, CR Kime, T Martin, “Logic and computer design
fundamentals ” 2008J.Bastos, "Characterization of mos transistor
mismatch for analog design, "Ph.D.dissertation, ISBN90-5682-11 05,ApriI1998.
[10] LR Smith, DM Thomas Dummy/trim DAC for capacitor digital-toanalog converter- US Patent 4,947,169, 1990