5/23/22, 9:39 PM 1.3.6. Blocking Cap Optimization 1.3.6. Blocking Cap Optimization AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission View More Search this document Document Table of Contents Document Table of Contents 1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission 1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission 1.1. PCB Material Selection 1.2. Stackup Design 1.3. Channel Design 1.4. Summary 1.5. Document Revision History for the AN 672: Transceiver Link Design Guidelines for HighGbps Data Rate Transmission 1.1. PCB Material Selection 1.1.1. Loss Tangent and Dissipation Factor 1.1.2. Dielectric Constant 1.1.3. Fiberglass Weave Skip To Main Content 1.1.4. Copper Surface Roughness 1.3. Channel Design 1.3.1. BGA Channel Breakout https://www.intel.com/content/www/us/en/docs/programmable/683624/current/blocking-cap-optimization.html 1/6 5/23/22, 9:39 PM 1.3.6. Blocking Cap Optimization 1.3.2. Channel Routing Design 1.3.3. Edge Coupling 1.3.4. Broadside Coupling 1.3.5. Transparent Via Design 1.3.6. Blocking Cap Optimization 1.3.7. Connectors Optimization 1.3.2. Channel Routing Design 1.3.2.1. Trace Width Selection 1.3.2.2. Loose vs. Tight Coupled Traces 1.3.2.3. Crosstalk Control 1.4. Summary 1.4.1. PCB Material Selection 1.4.2. Stackup Design 1.4.3. Channel Design 1.4.4. References 1.3.6. Blocking Cap Optimization Search this do Skip To Main Content 1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission 1.1. PCB Material Selection 1.2. Stackup Design 1.3. Channel Design 1.3.1. BGA Channel Breakout 1.3.2. Channel Routing Design 1 3 3 Ed C li https://www.intel.com/content/www/us/en/docs/programmable/683624/current/blocking-cap-optimization.html 2/6 5/23/22, 9:39 PM 1.3.6. Blocking Cap Optimization 1.3.3. Edge Coupling 1.3.4. Broadside Coupling 1.3.5. Transparent Via Design 1.3.6. Blocking Cap Optimization 1.3.7. Connectors Optimization 1.4. Summary 1.5. Document Revision History for the AN 672: Transceiver Link Design Guidelines for HighGbps Data Rate Transmission 1.3.6. Blocking Cap Optimization Transceiver channels often incorporate DC blocking capacitors to control the common mode voltage at the receiver. However, the presence of the blocking capacitors in the channel creates an abrupt discontinuity where the trace meets the capacitor. Similar to via optimization, the layout footprint for the blocking caps can be optimized to minimize their impact on the channel. Because the larger capacitor pad results in lowering its characteristic impedance, one way of increasing this impedance to better match the trace impedance is to increase the distance to the reference by making cut-outs underneath the body of the capacitor footprint. Figure 23. DC Blocking Capacitor Plane Cut-out Skip To Main Content https://www.intel.com/content/www/us/en/docs/programmable/683624/current/blocking-cap-optimization.html 3/6 5/23/22, 9:39 PM 1.3.6. Blocking Cap Optimization By cutting out the first reference plane directly below the capacitor, the impedance increases as it references the second plane further away. However, if this second reference plane is close to the first reference plane, the increase may still not be enough. In this case it also becomes necessary to cut out the second, third, or even more successive planes underneath to further increase the impedance. Figure 24. Additional Plane Cut-outs Underneath DC Blocking Cap Normally, determining the proper plane cutout size and the number of layers below the capacitor to cut is determined by extensive 3-D simulations. However, a formulaic approach based on simulations for determining this cutout is also possible. Figure 25. DC Blocking Capacitor Compensation Skip To Main Content Wt Plane1…… ..PlaneN Wc Where, Wt NpL DC Blocking Capacitor 1pL cL Wg Wc Lc Wg Wp1 Lp1 WpN LpN = = = = = = = = Trace width Component width Component length 0.7 x (Wc -Wt) Wc +2Wg Lc +2mil Wp1 + 10mil x (N-1) Lp1 Wp1 WpN 1. Cut out any plane underneath the capacitor whose proximity is within 0.75 Wc. 2. Set the side gap of the cut-out for plane 1 (Wg) = 0.7 (Wc – Wt). 3. Set the cut-out width of plane 1 (Wp1) = Wc+2 Wg. 4. Set the cut-out length of plane 1 (Lp1) = Lc+2 mils. https://www.intel.com/content/www/us/en/docs/programmable/683624/current/blocking-cap-optimization.html 4/6 5/23/22, 9:39 PM 1.3.6. Blocking Cap Optimization 5. Set the cut-out width of successive plane N (WpN) = Wp1 + 10 (N-1). 6. Set the cut-out length of successive plane N (LpN) = Lp1. The following example compares the time-domain reflectometer (TDR) results of the DC blocking capacitor layout with and without the plane cutout improvements. With the plane cutouts properly applied using the above guidelines, the large discontinuity at the trace to DC blocking capacitor junction is eliminated. Figure 26. DC Blocking Capacitor Layout with and without Plane Cutouts Skip To Main Content Figure 27. TDR Plot for DC Blocking Capacitor with and without Plane Cutouts Related Information Optimizing Impedance Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs 1.3.5. Transparent Via Design 1.3.7. Connectors Optimization Company Overview Contact Intel https://www.intel.com/content/www/us/en/docs/programmable/683624/current/blocking-cap-optimization.html 5/6 5/23/22, 9:39 PM 1.3.6. Blocking Cap Optimization Contact Intel Newsroom Investors Careers Corporate Responsibility Diversity & Inclusion Public Policy Skip To Main Content © Intel Corporation Terms of Use *Trademarks Cookies Privacy Supply Chain Transparency Site Map Intel technologies may require enabled hardware, software or service activation. // No product or component can be absolutely secure. // Your costs and results may vary. // Performance varies by use, configuration and other factors. // See our complete legal Notices and Disclaimers . // Intel is committed to respecting human rights and avoiding complicity in human rights abuses. See Intel’s Global Human Rights Principles . Intel’s products and software are intended only to be used in applications that do not cause or contribute to a violation of an internationally recognized human right. https://www.intel.com/content/www/us/en/docs/programmable/683624/current/blocking-cap-optimization.html 6/6
