University of Tripoli, Computer Engineering, EC383 Digital Systems II, Spring 2022, Instructor: Muharrem Drebi
EC383 PROJECT GUIDELINES
IEEE 754 SINGLE PRECISION FP ADDER
SPRING 2022
University of Tripoli, Computer Engineering, EC383 Digital Systems II, Spring 2022, Instructor: Muharrem Drebi
PROJECT DETAILS
• Using Verilog language design and verify a FP adder using single
precision IEEE 754 format.
• The inputs are assumed to be normalized and your design should
generate a normalized output.
• The adder can be of any type however to get higher grade, design a
faster adder.
• You can further speed up your design using pipelining ( To be
discussed in class).
• Your grade is determined by the following criteria
Design is working correctly?
70%
Design is parameterized?
10%
How fast? Tpd?
20%
University of Tripoli, Computer Engineering, EC383 Digital Systems II, Spring 2022, Instructor: Muharrem Drebi
PROJECT DETAILS
• You can use the following diagram
as a guide while writing your
Verilog code.
• Start by designing fast fixed point
adder and then as we progress in
class we will be discussing ASMD
charts then you can build complete
data-path and control unit for the
FP adder.
University of Tripoli, Computer Engineering, EC383 Digital Systems II, Spring 2022, Instructor: Muharrem Drebi
PROJECT DETAILS
• While coding your design you can use QuestaSim or incisive tool from
cadence or even an online portal like edaplayground.com
• Your design should be well documented.
• Module names and variable names should be indicative or
meaningful.
• Code sharing between students are not allowed.
• Project deadline (Four weeks from today date).
• Pick a date to present your design from 1st to 5th of August.
• Seven students at most per day is possible, so reserve your date ASAP.
• No time extension is possible.
Today date: 6th of July 2022