DSP6655 SRIO (RAPIDIO) HW+SW MODULES BASIC GUIDE AGENDA 1. DSP6655 Top Level Hardware Architecture 2. RapidIO Architectural Hierarchy 3. Hardware Introduction 1. 2. 3. 4. Multicore Navigator QMSS PKTDMA Memory Descriptors 4. Software Introduction 1. 2. 5. General Overview Gen3 LSW Specific Lab Examples DSP6655 TOP LEVEL HARDWARE ARCHITECTURE DSP6655 TOP LEVEL HW ARCHITECTURE RAPIDIO ARCHITECTURAL HIERARCHY ABOUT RAPIDIO From Wikipedia: • RapidIO architecture is a high-performance packet-switched electrical connection technology. • RapidIO supports messaging, read/write and cache coherency semantics. • RapidIO fabrics guarantee in-order packet delivery, enabling power- and area- efficient protocol implementation in hardware. • RapidIO can be used as a chip-to-chip, board-to-board communication - like PCIe. Full description: https://en.wikipedia.org/wiki/RapidIO RAPIDIO ARCHITECTURAL HIERARCHY RapidIO is defined as a three-layer architectural hierarchy. • Logical layer: Specifies the protocols, including packet formats, s, which are needed by end points to process transactions. • Transport layer: Defines addressing schemes to correctly route information packets within a system. • Physical layer: Contains the device-level interface information, such as the electrical characteristics, error management data, and basic flow control data. In the RapidIO architecture, one specification for the transport layer is compatible with different specifications for the logical and physical layers. RAPIDIO ARCHITECTURAL HIERARCHY – LOGICAL LAYER • Logical layer: Specifies the protocols, including packet formats, needed by endpoints to process transactions. Note: The exchange of control symbols (for example RETRY, RFR) takes less than < 200 nSec. Quicker than Ethernet. RAPIDIO ARCHITECTURAL HIERARCHY – TRANSPORT LAYER • Transport layer: Defines addressing schemes to correctly route information packets within a system. Note: Logical layer: See software introduction HARDWARE INTRODUCTION SRIO DEVICE TO DEVICE INTERFACE DIAGRAMS Support for 1.25, 2.5, 3.125, and 5 Gbps rates DSP6655 TOP LEVEL HW ARCHITECTURE MULTICORE NAVIGATOR (MCNAV) - DEFINITION MCNAV – DETAILED ARCHITECTURE Three main parts: 1. Transmit Side 2. Receive Side 3. Rx/Tx Streaming I/F Control MCNAV – QUEUE MANAGER SUB-SYSTEM (QMSS) For example: SRIO Queues Range: 672-687 MCNAV – PACKET DMA (PKTDMA) MCNAV – MEMORY DESCRIPTOR TYPES MCNAV – MEMORY DESCRIPTOR EXAMPLE MCNAV – MEMORY DESCRIPTOR EXAMPLE MCNAV – DATA MOVEMENT - TX MCNAV – DATA MOVEMENT - RX MCNAV – DATA MOVEMENT SOFTWARE INTRODUCTION SRIO LLD DRIVER ARCHITECTURE SRIO LLD DRIVER ARCHITECTURE Register Layer - The register layer is the IP block memory mapped registers which are generated by the IP owner. The SRIO LLD driver does not directly access the MMR registers but uses the SRIO CSL Functional layer for this purpose. SRIO LLD DRIVER ARCHITECTURE CSL Functional Layer - The SRIO LLD driver uses the CSL SRIO functional layer to program the device IP by accessing the MMR (Memory Mapped Registers). SRIO LLD DRIVER ARCHITECTURE Operating System Abstraction Layer (OSAL) - The The SRIO LLD is OS independent and exposes all the operating system callouts via this OSAL layer - Not fully Implemented (HINO) . SRIO LLD DRIVER ARCHITECTURE Device Specific SRIO layer - This layer implements a well defined interface which allows the core SRIO driver to be ported on any device which has the same SRIO IP block. This layer changes for every device. SRIO LLD DRIVER ARCHITECTURE This is the core SRIO device driver. The device driver exposes a set of well defined API which is used by the application layer to send and receive data via the RapidIO peripheral. The driver also exposes a set of well defined OS abstraction API which is used to ensure that the driver is OS independent and portable. The SRIO driver uses the CSL SRIO functional layer for all SRIO MMR accesses. The SRIO driver also interfaces with the CPPI and QMSS libraries to be support the Type9 and Type11 protocols. SRIO LLD DRIVER ARCHITECTURE Application Code - This is the user of the driver and its interface with the driver is through the well defined API set. Applications users use the driver API’s to send and receive data via the RapidIO peripheral SRIO LLD DRIVER - EXAMPLE SRIO LLD DRIVER ARCHITECTURE Application Code - This is the user of the driver and its interface with the driver is through the well defined API set. Applications users use the driver API’s to send and receive data via the RapidIO peripheral LEARNING MATERIAL Introduction to Multicore Navigator (QMSS+PKTDMA) Training This videos are prerequisite to understand the way how SRIO is designed and used in TI C6000™: • https://training.ti.com/keystone-i-training-multicore-navigator-overview • https://training.ti.com/keystone-i-training-multicore-navigator-queue-manager-subsystem-qmss • https://training.ti.com/keystone-i-training-multicore-navigator-packet-dma-pktdma Introduction to Serial RapidIO® (SRIO) Training • This video presents an educational overview of the RapidIO architecture and ecosystem. The RapidIO architecture is a high-performance packet-switched, interconnect technology for interconnecting chips on a circuit board, and circuit boards to each other using a backplane. This technology is designed specifically for embedded systems, primarily for the networking, communications, and signal processing markets. • https://www.youtube.com/watch?v=IilIWos4EgE • Also read here: • file:///C:/ti/pdk_c665x_2_0_16/packages/ti/drv/srio/docs/SRIO_SDS.pdf THANK YOU
