From 473fdbffca7d300519e1d29a6db6c05c8b775cb1 Mon Sep 17 00:00:00 2001
From: Skrilax_CZ <skrilax@gmail.com>
Date: Wed, 10 Jun 2020 11:45:44 -0700
Subject: Overclock CPU to 2 GHz, GPU to 1 GHz
---
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 18 +++++++++---------
drivers/soc/tegra/tegra210-dvfs.c | 12 ++++++------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
index 483de0d1..0ec7dc7d 100644
--- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
@@ -105,7 +105,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
[6] = 2014500000UL,
[7] = 1734000000UL,
[8] = 1683000000UL,
-[9] = 1555500000UL,
+[9] = 2014500000UL,
[10] = 1504500000UL,
};
@@ -199,8 +199,12 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
{1224000000UL,{1081943, 0, 0} }, \
{1326000000UL,{1090000, 0, 0} }, \
{1479000000UL,{1090000, 0, 0} }, \
-{1555500000UL,{1162000, 0, 0} }, \
-{1683000000UL,{1195000, 0, 0} }, \
+{1555500000UL,{1140000, 0, 0} }, \
+{1683000000UL,{1140000, 0, 0} }, \
+{1734000000UL,{1195000, 0, 0} }, \
+{1836000000UL,{1195000, 0, 0} }, \
+{1912500000UL,{1227500, 0, 0} }, \
+{2014500000UL,{1227500, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
@@ -279,7 +283,7 @@ struct cvb_table tegra210_cpu_cvb_tables[] = {
.speedo_id = 9,
.process_id = 0,
.min_millivolts = 900,
-.max_millivolts = 1162,
+.max_millivolts = 1227,
CPU_CVB_TABLE_EUCM2,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
@@ -291,7 +295,7 @@ struct cvb_table tegra210_cpu_cvb_tables[] = {
.speedo_id = 9,
.process_id = 1,
.min_millivolts = 900,
-.max_millivolts = 1162,
+.max_millivolts = 1227,
CPU_CVB_TABLE_EUCM2,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
@@ -805,7 +809,6 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
struct rail_alignment align;
const struct thermal_table *thermal;
unsigned long max_freq;
-u32 f;
bool ucm2;
of_id = of_match_device(tegra124_dfll_fcpu_of_match, &pdev->dev);
@@ -822,9 +825,6 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
return -ENODEV;
}
max_freq = fcpu_data->cpu_max_freq_table[speedo_id];
-if (!of_property_read_u32(pdev->dev.of_node, "nvidia,dfll-max-freq-khz",
- &f))
-max_freq = min(max_freq, f * 1000UL);
soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
if (!soc)
diff --git a/drivers/soc/tegra/tegra210-dvfs.c b/drivers/soc/tegra/tegra210-dvfs.c
index 1f3d664c..7ff79ec6 100644
--- a/drivers/soc/tegra/tegra210-dvfs.c
+++ b/drivers/soc/tegra/tegra210-dvfs.c
@@ -331,6 +331,10 @@ static struct dvfs cpu_dvfs = {
{1479000000UL,{ 2519460, -105063, 1611 } }, \
{1555500000UL,{ 2639809, -108729, 1626 } }, \
{1683000000UL,{ 2889664, -122173, 1834 } }, \
+{1734000000UL,{ 3386160, -154021, 2393 } }, \
+{1836000000UL,{ 5100873, -279186, 4747 } }, \
+{1912500000UL,{ 5100873, -279186, 4747 } }, \
+{2014500000UL,{ 5100873, -279186, 4747 } }, \
{0, { } }, \
}
@@ -399,14 +403,14 @@ static struct cpu_dvfs cpu_fv_dvfs_table[] = {
.speedo_id = 9,
.process_id = 0,
.min_mv = 900,
-.max_mv = 1162,
+.max_mv = 1227,
CPU_PLL_CVB_TABLE_EUCM2,
},
{
.speedo_id = 9,
.process_id = 1,
.min_mv = 900,
-.max_mv = 1162,
+.max_mv = 1227,
CPU_PLL_CVB_TABLE_EUCM2,
},
{
@@ -2029,10 +2033,6 @@ static void init_gpu_dvfs_table(struct device_node *node,
for (ret = 0, i = 0; i < table_size; i++) {
struct cvb_dvfs *d = &cvb_dvfs_table[i];
unsigned long max_freq = d->max_freq;
-u32 f;
-
-if (!of_property_read_u32(node, "nvidia,gpu-max-freq-khz", &f))
-max_freq = min(max_freq, (unsigned long)f);
if (match_dvfs_one("gpu cvb", d->speedo_id, d->process_id,
gpu_speedo_id, gpu_process_id)) {
-- 2.20.1