PROJECT REPORT
Design and optimization of 555 timer-based Multivibrators
for the partial fulfilment for the award of the degree of
Bachelor of Technology
Submitted By
Chinnapogula Dinesh(B180065EC)
Khushbu Gupta(B180065EC)
Under the Supervision of
Dr. Sanjay Kumar Jana
Assistant Professor & HOD
Department of Electronic and Communication Engineering
NATIONAL INSTITUTE OF TECHNOLOGY SIKKIM
MAY 2022
CERTIFICATE BY THE SUPERVISOR
This is to certify that the project report entitled” DESIGN AND
OPTIMIZATION OF 555 TIMER BASED MULTIVIBRATORS” is being
Submitted by Chinnapogula Dinesh (Roll No. B180065EC) Khushbu Gupta
(Roll No. B180093EC), students in the Department of Electronic and
Communication Engineering, National Institute of Technology Sikkim, for
the award of the degree of Bachelor of Technology (B.Tech). It is carried out
by them under my supervision and guidance. The results embodied in this report
have not been submitted to any other University or Institute for the award of any
degree.
Dr. Sanjay Kumar Jana
Assistant Professor HOD
Department of Electronic and Communication Engineering
National Institute of Technology Sikkim
Ravangla - 737139, Sikkim, India
CERTIFICATE BY THE STUDENT
We hereby declare that the work presented in the report entitled” Design and
optimization of 555 timer-based Multivibrators” is a Bonafide record of the
work done by us under the supervision of Dr. Sanjay Kumar Jana,
Department of Electronic and Communication Engineering and that no part
thereof has been presented for the award of any other degree.
• We have followed the guidelines provided by the institute in writing the report.
• The report does not contain any classified information.
• Whenever, we have used materials from other sources, we have given due
credits to those by citing them in the text of the report and giving the details in
the references.
• Whenever we have quoted written materials from other sources, I have put them
under quotation marks and given due credits to the sources by citing them in the
text of the report and giving their details in the references.
Chinnapogula Dinesh
Roll no. B180065EC
CERTIFICATE BY THE STUDENT
We hereby declare that the work presented in the report entitled” Design and
optimization of 555 timer-based Multivibrators” is a bonafide record of the
work done by us under the supervision of Dr. Sanjay Kumar Jana,
Department of Electronic and Communication Engineering and that no part
thereof has been presented for the award of any other degree.
• We have followed the guidelines provided by the institute in writing the report.
• The report does not contain any classified information.
• Whenever, we have used materials from other sources, we have given due
credits to those by citing them in the text of the report and giving the details in
the references.
• Whenever we have quoted written materials from other sources, I have put them
under quotation marks and given due credits to the sources by citing them in the
text of the report and giving their details in the references.
Khushbu Gupta
Roll no. B180093EC
ACKNOWLEDGEMENT
We are tremendously indebted to our supervisor Dr. Sanjay Kumar Jana, Head
of the Department and of the Department of Electronic and Communication
Engineering, National Institute of Technology Sikkim for his invariable guidance
and assistance through the project. His guidance have been prized in the
development and progress of the content. Furthermore, the skills and knowledge
which we have gained through this project We perceive as very valuable and
significant for my future. I would like to extend my special thanks of gratitude to
my departmental faculty members, research scholars and friends for their able
guidance and support in completing my project and the skills and knowledge
which we have gained through this project.
Chinnapogula Dinesh
Roll No: B180065EC
Khushbu Gupta
Roll No: B180093EC
Electronic and Communication Engineering
National Institute of Technology Sikkim
Ravangla - 737139, Sikkim, India
Table of Contents
CHAPTER 1
1.1. Abstract......................................................................................................................................8
1.2. Introduction...............................................................................................................................8
1.3. Objective....................................................................................................................................8
1.4. Literature Survey...................................................................................................................9-10
1.5. Internal Architecture of IC 555 timer.......................................................................................11
CHAPTER 2
2.1 . Pin description and its function..........................................................................................11-12
2.2. Working principle of IC 555 Timer.......................................................................................12-15
2.3. Proposed architecture.........................................................................................................15-16
2.4. Result and discussion...............................................................................................................17
CHAPTER 3
3.1 Different operating modes: Monostable Mode.................................................................17-21
3.2 Bistable Mode....................................................................................................................22-24
3.3 Astable Mode....................................................................................................................25-28
CHAPTER 4
4.1. Transistor level design of 555 timer...................................................................................29-30
4.2. Design of voltage comparator............................................................................................30-36
4.4. Design of SR flip flop...............................................................................................................37
4.5. Final design of bjt level 555 timer circuit................................................................................38
CHAPTER 5
5.1. Monostable Mode of bjt based 555 timer circuit.................................................................39-41
5.2. Astable Mode of bjt based 555 timer circuit.........................................................................41-44
5.3. Bistable mode of bjt based 555 timer circuit.........................................................................44-46
,
CHAPTER 6
6.1. improvements........................................................................................................................46
6.2. Applications............................................................................................................................46
6.3. Conclusion..............................................................................................................................47
6.4. Future work............................................................................................................................47
6.5. Referances..............................................................................................................................47
CHAPTER 1
555 Timer design
1.1 Abstract: In this paper we are going to express about the basic principle of IC 555
Timer, its working and its applications. 555 Timer plays a key role in many electronics project.
It is highly useful IC whose applications range from simply making a light blink on and off to
creating an astable multivibrator. From the time of its invention the usage of IC increased by
varying the technology and maintaining the useful specifications. This IC is used in various
applications depends upon its need.
1.2 Introduction: The 555 Timer IC is an integrated circuit (chip) used for implementing a
variety of timer, multivibrator PWM applications. The IC was designed by Hans R. Camenzind
in 1970 and brought to market in 1971 by Signetics (later acquired by Philips). The original
name was the SE555 (metal can)/NE555 and the part was described as "The IC Time Machine".
It has been expressed that the 555 gets its name from the three 5 kΩ resistors connected in
series voltage divider and consists of several transistors, resistors, capacitors, diodes, flip flops
and other elements. It is a highly stable device for generating accurate time delays and
oscillations.
1.3 Objective: The 555 Timer is extremely useful and stable 8 pin device it is used in various
applications like monostable, Astable multivibrator, generating PWM and rectangular wave. I
this paper I am going to express the 555-timer working process, different modes of it and
simulation of generating rectangular wave using the 555 timer.
Fig 1. 555 timer with pin configuration [ 1 ]
1.4 Literature survey
As 555 timer is robust and stable circuits which generates a square wave with a duty cycle at
range from 50% to 100%. 555 timer IC got its name because of connection of three 5 kilo-ohm
resistor in series which divides voltage equally among the resistors. The NE555 Iis used to
design the 555 timer which includes 8 pin dip package IC which performs array of timing tasks
in the electronic circuits. The 555 Timer IC has basically three functional parts. They are
Comparator: It is used to compare two different voltages at input terminals, at inverting level
and non-inverting level. Voltage Divider: As the input resistance is infinite in the comparator
so the voltage gets divided equally among all three resistors and the Value across each resistor
is Vin/3.Flip/Flop: it stores single bit information. When S is high Q output is high and if R is
high Q output is low. In this circuit, they have used the NE555 IC as an astable multivibrator
and when power is provided to circuit, the LEDs will start blinking which will show that the
IC is working. The blinking rate of LEDs can be changed by increasing or decreasing the values
of resistor R1 and R2 and capacitor C1. can calculate the time duration with the help of formula
given below: T = 0.7(R1+2R2) *C1 in seconds. As soon as power supply is provided, C1 will
start charging through R1and R2. When the voltage across C1 rises above 2/ 3 of supply
voltage, the internal Flip Flop toggles. As a result, pin 7 becomes low and C1 starts discharging.
When the voltage across C1 goes below 1/ 3 of supply voltage, the internal Flip Flop resets and
pin 7 goes high. The C1 again starts charging. All this will happen only when your IC is in
good condition. According to the frequency as set with the help of resistor R1, R2 and capacitor
C1 charging and discharging take place and LED1 and LED2 will flash accordingly. The 555
Timer has three operating modes Monostable Mode: In this mode, the 555 functions as a “oneshot” pulse generator.
Applications include timers, missing pulse detection, bounce free switches, touch
switches,frequency divider, capacitance. measurement, pulse-width modulation (PWM) ,etc.
Astable (free-running) mode: The 555 can operate as an oscillator.it include LED and lamp
flashers, pulse generation, logic clocks, tone generation, security alarms, pulse position
modulation etc. Bistable mode or Schmitt trigger: The 555 can operate as a flip-flop, if the DIS
pin is not connected and no capacitor is used. It include uses of bounce-free latched switches
The IC was designed in 1971 by Hans R. Camenzind under a contract to signetics which was
later acquired by Philips.it has been in wide use ever since It was the very first commercial
timer IC to be designed at that time and It is a highly stable device for generating accurate time
delays or oscillation.The IC 555 timer consists of two comparators which are basically an
Opamps that compares the voltages at two different input terminals..
The input impedance must kept at very high so that the voltages can get divided equally among
three 5kohm resistors.it also consist SR flip flop which stores single bit information, it give
high output when S is high and R is low and low output when R is high and S is low. Different
modes of 555 timer, Monostable Mode The output is low at first, and the transistor is turned
on. As a result, there is no short circuit path for the capacitor. It's time to charge. When the
patient is given a negative pulse, The trigger comparator on pin 2 recognises this input and The
state of the flip flop is set. So the production shifts from low to high.The transistor is turned
off because the voltage is too high. The brief The capacitor begins to charge when the circuit
path is disconnected. Via R1 up to VCC When the capacitor's voltage is taken into account.
The output becomes after the flip flop is reset. Application of IC 555 timer includes, Speed
control of brushed DC motor for low cost electric cars, A voltage-controlled oscillator (VCO)
, Ramp Generator Circuit-using 555 Timer; , Detection of Over Speeding Vehicles on
Highways;, A Hygrometer, Power Alarm, Dark Detector, IC 555 Timer in a Novel
Microprocessor-Controlled Active-R Multifunction Network, LM555 Timer-Based Inverter
Low Power Pure Sinusoidal AC Output, IC 555 Timer to turn on an LED, IC 555 Timer as a
Frequency Divider, Digital sensor for miniature medical thermometer, and body temperature
monitor” uses CMOS 555 timer as the multivibrator circuit.
Fig 2. Internal architecture of 555 timer [ 1 ]
Fig 3. Internal architecture of 555 timer at transistor level [ 5]
CHAPTER 2
2.1 Pin description of IC 555 timer and its function:
1.Ground: The ground pin is the most-negative supply potential of the device, which is
normally connected to circuit common when operated from positive supply voltages.
2.Trigger: Trigger. when this voltage falls below 1/3Vcc, the output goes high and timing
starts. As long as it is low, the output will remain high
3.Output: This pin drives the circuit to either low state (less than 0.5 v) or high state (above
2 volts) this pin drives up to 200mA of current.
4.Reset: This pin is used to reset the latch and return the output to a low state. The reset
voltage threshold level is 0.7 volt, and a sink current of 0.1mA from this pin is required to reset
the device. In short, the reset pin is used to reset the flip-flop that controls the state of output
pin 3.
5.Control Voltage: This pin allows direct access to the 2/3 V+ voltage-divider point, the
reference level for the upper comparator. It also allows indirect access to the lower comparator,
as there is a 2:1 divider from this point to the lower-comparator reference input,Use of this
terminal is the option of the user. A voltage applied to this pin will vary the timing of the RC
network.
6.Threshold: This pin is the one of the input to the upper comparator is used to reset the flip
flop which makes output goes low. By applying voltage above /3Vcc to this terminal we can
reset the flip flop by making upper comparator high. The DC current typically flow in this
terminal is 0.1uA.
7.Discharge: This pin is connected to the open collector of a N channel transistor the emitter
of which goes to ground, so that when the transistor is turned "on", pin 7 is effectively shorted
to ground. Usually, the timing capacitor is connected between pin 7 and ground and is
discharged when the transistor turns "on". It is "on" (low resistance to ground) when the output
is low and "off" (high resistance to ground) when the output is high.
8.Vcc(supply): This pin connects positive power supply (Vs) and voltage is varied between
4.5V to 15V.but it has commonly 5V DC when it is working in digital IC
2.2 Working Principle of 555 Timer:
In the internal block diagram of 555 timer consists a voltage divider circuit, two comparators,
one flip flop, discharging transistor and output stage.
In Voltage divider circuit we have three identical 5Kohm resistor which will create the two
reference voltages are 2/3Vcc, 1/3Vcc which are given to the input of comparators and the Vcc
is maintained between 5V to 15V.
Fig 4. Voltage divider circuit in 555 timer [8]
Next, we have two comparators. A comparator is used to compare two analog input voltages
at its positive(non-inverting) and negative(inverting) input terminal. If the input voltage at the
positive terminal is higher than the input voltage at the negative terminal the comparator will
output 1(high). Vice versa, if the voltage at the negative input terminal is higher than the
voltage at the positive terminal, the comparator will output
Fig 5. symbol for comparator [1]
In above internal schematic of 555 timer, we have two comparators. The first comparator
negative input terminal is connected to the 2/3 reference voltage at the voltage divider and the
external “control” pin, which is used to control the voltage while the positive input terminal to
the external “Threshold” pin. Output pin is connected to the R terminal of the SR
Flip flop. On the other hand, the second comparator negative input terminal is connected to the
“Trigger” pin, while the positive input terminal to the 1/3 reference voltage at the voltage
divider. Output is connected to the S terminal of SR flip flop.
Fig 6. Connection of comparator to the SR flip flop [8]
By applying the voltage to these three pins through Vcc, Trigger, Threshold and Control, we
can control the output of the two comparators which are then connected to the R and S inputs
of the flip-flop. The flip-flop will output 1 when R is 0 and S is 1, and vice versa, it will
output 0 when R is 1 and S is 0. Additionally, the flip-flop can be reset via the external pin
called “Reset” which can override the two inputs, thus reset the entire timer at any time.
Fig 7. symbol of SR flip flop [ 1]
The Q-bar output of the flip-flip goes to the output stage or the output drivers which can either
source or sink a current of 200mA to the load. The output of the flip-flip is also connected to a
transistor that connects the “Discharge” pin to ground.
Fig 8: Output of SR flip flop is connected to the output load along with transistor [8]
Fig 9 shows the proposed architecture of 555 timer in this circuit we used npn and pnp bjt
transistors and resistors to build internal components like voltage comparator, SR flipflop,
discharge circuit and output circuit etc. Here we used 25 bjt transistors and 15 resistors used
to build the circuit. Q1 to Q8 transistors are used design the threshold comparator, Q9 to Q13
are used to design the trigger comparator, Q15 to Q20 is used to design SR flip flop, Q14 is
used for discharge circuit, Q21 and Q22 is used for output circuit Q25 is used for reset pin
and rest of the transistors are used for designing of other circuitary in the design.
Fig 9: Design of 555 timer at BJT level simulated in LTspice
Fig 10: Design of square wave using 555 timer
Fig 10 shows the design of generation of square wave using the 555-timer schematic in Ltspice
simulator in this design we given vcc dc voltage is 8v supply and trigger pin and threshold pin
is shorted this is connected to discharge pin through r2 resistor and it is connected to Vcc trough
R1 resistor and control voltage is connected to the charging capacitor and output is taken from
ouput terminal
2.3 Results and discussion
Fig 11: output of 555 timer which is square wave
Fig 11 shows the square wave of amplitude of 8v and time period is 2.5 sec and tigger wave
form of 555 timers
CHAPTER 3
3.1Operating modes of of 555 Timer: Monostable Mode
Fig 12: Monostable mode of 555 timer
The trigger input is held high in this mode by connecting it to VCC through a resistor R2.
Because of the high voltage at the comparator's negative terminal, the trigger comparator will
output 0 and the flip-S flop's input will be 0. However, because the Threshold pin is low, the
output of the Threshold comparator is also 0. The threshold pin is already Low since the flipQ-bar flop's output is in the High state (1), which activates the transistor and causes it to
discharge, allowing the voltage from the source to reach the ground.
To set the 555 Timer output state to High (1), connect the trigger pin to ground, which sets the
input terminal of the trigger pin to 0, and the comparator output to 1 on the flip-S flip's input.
The Q-bar output will become Low(o) while the 555 Timer output will become High (1). At
the same time, the discharge transistor is turned off, indicating that the capacitor C1 will now
begin to charge through the resistor R1.
Until the voltage across the capacitor exceeds 2/3 of the provided voltage, the 555 Timer will
remain in the high state. In this situation, the Threshold input voltage will be greater (1), and
the comparator output will be 1, causing the R input of the flip-flip to be high. This will reset
the circuit to its original condition. The Q-bar output will become high, activating the discharge
transistor and making the IC output Low again, allowing the 555 timer to operate in monostable
mode.
Fig 13: input and output characteristics of 555 timer when operated in monostable mode.[5]
In Fig 13 shows the input trigger pulse of of monostable mode which is seen at trigger terminal
of circuit and output voltage is seen at output terminal which is high at every trigger pulse.
Here we capacitor voltage is seen at CL
So, the length of time the 555 Timer's output is High is determined by how long the capacitor
takes to charge to 2/3 of the provided voltage, which is determined by the values of both the
capacitor C1 and the resistor RA. This time can be calculated using the formula T=1.1*CL*RA.
Fig 14: Monostable mode of 555 timer schematic in LT spice
In figure 14 shows the monostable mode of 555 timer schematic is simulated in LT spice. In
this circuit Vcc is connected with 5 volts and trigger pulse of 5v amplitude and 1ms delay is
given to the trigger pin of 555 timer. Discharge and threshold pin is shorted and control voltage
is connected to the discharge capacitor of capacitance of 0.01uF and transient analysis is done
up to 100ms
Fig 15: Input voltage Vs time ( Vn002 vs time) in monostable mode of schematic 555 timer
In fig 15 shows the graph of trigger pulse vs time which is applied at trigger pin in monostable
mode of schematic 555 timer circuit
Fig 16: Output voltage Vs time ( Vn004vs time) in monostable mode of schematic 555 timer
In Fig 16 shows the output voltage vs time graph which is seen from the output terminal of the
monostable mode of schematic 555 timer circuit
Fig 17: power dissipation graph in monostable mode of schematic 555 timer
In Fig 17 shows the power dissipation of resistor which is connected at the output terminal of
schematic 555 timer circuit which is 2.5mWatt
3.2 Bistable Mode
Fig 18: Bistable mode of 555 timer
In the circuit above, we utilised two resistors and two push buttons to create the bistable mode
of the 555 timer. The IC's Trigger and Reset pins are connected to the source voltage Vcc via
two resistors, ensuring that they remain high during the simulation. Because the two
pushbuttons are connected to these pins and the ground, if we keep them pushed, the input state
will go low. Because the outputs of the two comparators are initially zero, the flip-flop will be
in the previous state, as will the 555 Timer's output. When we hit the Trigger button, the Trigger
input becomes Low (0), which causes the trigger comparator output to become High (1).
Flip-flip Q-bar output will become Low (0). The output stage will flip this, and the 555 Timer's
ultimate output will become High (1). Because the flip-flop inputs R and S will be 0 if the
trigger pushbutton is not pressed, the output will remain high until the trigger pushbutton is
pressed, putting the flip-flop in the prior state. To make the output Low, hit the Reset button,
which will reset the flip-flop as well as the entire IC.
Fig 19: input and output characteristics of Bistable mode of 555 timer [10]
In Fig 19 shows the input and output characteristics of bistable mode of 555 timer. In this
input is high then output also high until the next input high signal after that output go to low
in this way sor for every trigger input the output changes alternatively.
Fig 20: Bistable mode of 555 timer schematic in LT spice
In Fig 20 shows the Bistable mode of schematic 555 timer circuit implemented in the LT spice.
In this circuit Vcc is given with 12v of dc voltage and trigger pulse of 12v amplitude and 4ms
delay is given at trigger terminal of the circuit which 10ms far from the voltage axis. Another
trigger pulse is given to the reset pin which is 12v amplitude ,4ms delay and 50ms far from the
voltage axis and transient analysis done for 100 ms
Fig 21: Bistable mode input voltages vs time graph of 555 timer schematic in LT spice
In Fig 21 shows the input tigger pulses vs time graph which as 12v amplitude and time between
two pulse is 40ms
Fig 22: Bistable mode output voltages vs time graph of 555 timer schematic in LT spice
In Fig 22 shows the output voltage of bistable mode of schematic 555 timer here the voltage is
dropped between the two trigger pulse
3.3 Astable Mode
Fig 23: A stable mode of 555 timer [5]
The IC will operate as an oscillator in this mode. It does not have a steady state, and the output
alternates between high and low without the use of an external trigger signal. Only two resistors
and a capacitor are required. There is no need for an external trigger pulse because the Trigger
and Threshold pins are shorted to each other. At first, the voltage
The capacitor will be charged by the source via the resistors R1 and R2. Because the input
voltage at the Trigger pin is still less than 1/3 of the Vcc, the Trigger comparator will output
high (1) when charging. That is, the Q-bar output is low (0), and the transistor connected to the
flip flop's output resistor is closed. The 555 Timer's output is now set to High.
The Trigger comparator will output 0 once the voltage across the capacitor reaches 1/3 of the
provided voltage, but this will have no effect because the R and S inputs of the flip-flop are
both 0. As a result, the voltage across the capacitor will continue to rise, and the Threshold
comparator will output 1 to the R input of the flip-flop once it reaches 2/3 of the provided
voltage. The discharging transistor will now be active, and the capacitor will begin to discharge
through the resistor R2 and the discharging transistor.
The output of the 555 Timer is currently Low. While discharging, the voltage across the
capacitor drops, and the Threshold comparator immediately outputs 0, which has no effect
because both the R and S inputs of the flip-flop are now 0. The Trigger comparator will output
1 when the voltage across the capacitor decreases to 1/3 of the provided voltage. The discharge
transistor will be turned off, and the capacitor will begin to charge again. As a result, the
charging and discharging operations between 2/3 and 1/3 of the given voltage will continue to
run on their own, resulting in a square wave on the 555 Timer output.
Fig 24: input and output characteristics of Astable mode of 555 timer[9]
In Fig 22 shows the input and output voltage charcteristics of astable mode of 555 timer. In
which input voltage is varied from one third of Vcc to two third of Vcc .In this way whenever
input voltage goes from one third of Vcc to two third of Vcc the output is high and when input
voltage goes from two third of Vcc to one third of Vcc the output voltage is low.
Using the formulas presented, we can determine when the output is High and Low. The High
time is determined by Ra and Rb resistances, as well as the capacitance of the capacitor. The
Low time, on the other hand, is solely determined by Rb's resistance and the capacitor's
capacitance. The Period of one cycle is calculated by adding the High and Low timings. The
frequency, on the other hand, is the number of times this occurs in one second, therefore one
over the Period gives the frequency of the square wave output
Fig 25: Astable mode of 555 timer schematic in LT spice
In Fig 25 shows the Astable mode of schematic 555 timer circuit which is implemented in Lt
spice In this circuit Vcc is given with DC voltage of 5v, trigger terminal and threshold terminal
is shorted 5k ohm resistor is placed between Vcc and discharge and 3k ohm is connected
between the discharge and shorted circuit of trigger and threshold terminal. capacitor of 0.15uF
is connected between 3k ohm and ground.10 k ohm resistor is connected between output
terminal and Vcc
Fig 26: Input voltage Vs time of Astable mode of 555 timer
In Fig 26 shows the input voltage pulse vs time which is seen between 3k ohm resistor and
capacitor of 0.15uF of bistable mode of schematic 555 timer circuit
Fig 27: Output voltage Vs time of Astable mode of 555 timer
In Fig 27 shows the output voltage Vs time graph which is seen at Out terminal of astable mode
of schematic 555 timer circuit. Where the output is not stable it is fluctuating between 5v
amplitude and ov amplitude
Fig 28: power dissipation of Astable mode of 555 timer
In Fig 28 shows the power dissipation at 10k ohm resistor which is attached between Vcc and
output terminal of astable mode of schematic 555 timer which is 2.5mWatt
CHAPTER 4
4.1 Transistor (BJT) level design 555 Timer design
Now we are living in the world of technology. The electronics is the back bone of all the new
technologies. The electronics field is a vastly growing field. Are you think about that? What is
the main turning point in the electronic field. Everybody say that it is the discovery of
transistors, most precisely the discovery of INTEGRATED CIRCUIT. We call it as IC, in short
form. Basically, what is an IC, Is it a discrete component like capacitor, transistor, resistor,
etc... Are you think about it. For solving this question, I did research and studied many books
related to analog chip designing to know about IC chip. Then after some days I found that, that
IC chip is the building block of many electronic devices and circuits. So, I wondered about it.
I search much more about it and find that, it is not a discrete component it is a circuit (as the
name indicates), it contains the basic components like resistors, capacitors, transistors, etc... So
here I design a discrete chip by using the basic components like transistors, resistors, capacitors
and ground in LTspice which is the famous 555 timer chip. I make its original circuit using
basic components like bjt transistors. So first we discuss something about the 555 and then start
to make us on discrete 555.
The world's most popular IC is the 555. It used in all the equipment from the small playing
toys to the big aircrafts. It is a very useful IC. It is used as oscillator, modulator, electronic
switch, PWM generator, astable stable and bi-stable multi vibrator, light are dark detector etc...
I. It is an 8 pin IC. It is in DIP or in the smd package. It contains 23 transistors, 2 diodes and
16 resistors. In the following section explain more about it.
The 555 is not a discrete component. It is a circuit by using transistors, resistors, etc... in a
single silicon chip. The IC chip making is a special technique that contain several complex
steps. It is complex because the size of the chip is very small. The 555 ic is a circuit by using
transistors, diodes and resistors in a single chip. By using reverse engineering technique, we
are finding the exact component level circuit. Here the component level circuit is given. It is a
BJT realization circuit. It is also available in CMOS version. In the die image the large three
identical structures is the output driver transistors and discharge transistor. These are large
because it handles more current than others. In the BJT circuit image the colour boxes represent
the corresponding block names.
Fig 29: internal schematic of bjt level 555 timer [ 4]
I will modify above circuit based on to get low power consumption IC which is very useful for
many applications. It was done by adding transistors and using the low value of resistors and
increasing the gain paths converting diodes to transistors like connecting collector terminal to
base
terminal
of
transistor.
If we look on above schematic diagram which the actual circuit of 555 timer. If we design as
like above circuit, we won't get appropriate results for us So, I ignored the actual design and
implemented based on my favourable conditions
4.2 Designing of voltage comparator
The first and foremost important circuit in 555 timer IC is comparator. Here we use two types
of voltage comparators they are trigger and threshold comparator.
The main circuit in the comparator is differential amplifier in which we use to give two different
input voltages like comparator and we will get one output voltage
Differential amplifier is an extremely popular connection used in Integrated circuits the circuit
has two separate inputs and two separate outputs, and that the emitters are connected together
whereas many differential circuits use two separate voltage supplies, the circuit can also
operate using a single supply
A number of input signal combinations are;
Fig 30: differential amplifier circuit in comparator
In figure 30 If an input signal is applied to the only input terminal with fixed voltage with the
other input terminal connected to ground, the operation is defined as “single-ended.”
If two input signals are applied to two different opposite voltages, the operation is defined as
“double-ended.”
If the both inputs are applied with same voltage, the operation is called “common-mode.
In single-ended operation, a single input signal is applied. However, due to the common emitter
connection, the input signal operates both transistors, resulting in output from both collectors.
In double-ended operation, two input signals are applied, the difference of the inputs resulting
in outputs from both collectors due to the difference of the signals applied to both inputs.
In common-mode operation, the common input signal results in opposite signals at each
collector, these signals cancelling, so that the resulting output signal is zero.
As a practical matter, the opposite signals do not completely cancel, and a small signal result.
The main feature of the differential amplifier is the very large gain when opposite signals are
applied to the inputs as compared to the very small gain resulting from common inputs. The
ratio of this difference gain to the common gain is called common-mode rejection
It was quite surprise at common mode input the output was balanced but not good as op amp
even if two transistors are not matched there is no problem it will work as voltage comparator
here, we only need the circuit to be operated in digital mode like output should be either high
power rail or low power rail so matching of transistors has no impact in the differential mode
of comparator.
By using only this circuit we will face many problems in our comparator like
1.Output state of small common mode input is not stable
2.if we vary the Vcc the currents through the both emitters will change these leads to unstable
conditions
3.The gain of the above circuit is low
4.low input impedance
5.No single ended output
To overcome the above problems we have to add one active current sink source to the both the
emitters of the bjts instead of the tail resistor
Fig 31: differential amplifier circuit with constant current sink transistor to the emitter
In Fig 31 After adding the constant current sink to the emitters of the bjts input impedance
got slightly higher which is we want in the comparator also by changing the common mode
input the output remain in stable conditions than before and by varying the Vcc the steering
current remains constant
Now we have increase the gain and amplifying the output this can be happened by adding the
current mirror circuit in the place of both collector resistors here current mirror can act like as
earlier resistor did .
Fig 32: current mirror circuit in comarator
In Fig 32 The current in the left transistor controls the current through the load. The control
side is the transistor, which has its base and collector connected. Because the voltage of the
transistor's base is dropped when the resistor reduces the voltage toward ground, the transistor
begins to turn on. The current then flows through the transistor, raising the base voltage until
the amount of current flowing through the transistor and resistor is balanced. Because the bases
of the two transistors are connected, the second transistor turns on as well, but only to the same
extent as the first. As a result, the current of the left transistors will control the current in the
right transistor
This current mirror circuit balance the collector current of the transistor and it helps to get
single ended output for differential output because one side is used to control the current and
other side is used to get the output in this way it amplifies the output
Fig 33: current mirror circuit connected to collector terminals of differential amplifierIn
Fig 33 let us make the input at Q1 higher than the Q2 in this case Q1 transistor turn ON
harder than the Q2 which will make the voltage drop at the collector terminal of the Q1 since
it is connected to the base of the above pnp current mirror circuit here the voltage at base is
very low it make current mirror on now same current flow in the Q2 as flown in Q1 but
initially Q2 is OFF but current mirror circuit make the large amout of current flow in the
collector terminal of the Q2 this leads to drastically increase in the voltage that output is
considered as high
Now make the input at Q2 higher than Q1 now in this situation the current mirror is in off state
because of no proper voltage at base of the current mirror because the Q1 is off and its collector
is disconnected from Vcc and Q2 is ON collector is grounded then output at collector is low
From above we conclude that input at Q1 is non-inverting and input at Q2 is inverting terminals
of voltage comparator
Now the diff. amp. works much better; it is balanced much better, it has only one output, and the output
has been amplified some. The diff. amp. with a current mirror makes a good differential stage for an
OP amplifier, but it still isn't optimal for a comparator. When the input voltages become close, the
output still doesn't have a sharp transition. The way to improve that is to amplify the input. To add the
Darlington
stage
to
the
both
differential
input
Fig 34: Darlingtone stage at input of differential amplifier
In fig 34 the darlingtone stage at both the inputs the transistor are designed to get very high
input impedance and initially current flow through the first transistor and again this current will
flow to the second transistor through the emitter teminal of first transistor to the base of second
transistor which amplifies the further The result is a gain approximately equal to the gain of
the first transistor multiplied by the gain of the second. Now each input is amplified by two
transistors
Till now we improved the input impedance, input gain, getting single mode output these things
will balance the comparator but there is small problem the output voltage is op amp rather than
comparator with sharp voltage transition that means sometimes the ouput reaches to less
voltage than Vcc to overcome this we have add one pnp transistor at the output terminal these
leads to get output voltage close to Vcc
Fig 35: Final design of voltage comparator
In Fig 35 we got the final design of voltage comparator with the connection differential
amplifier, current mirror ,darlingtone pair ciruits and this comparator is used in the 555 timer
circuit
4.2 Designing of RS flip flop
In designing the RS flip flop, we use two transistors and two buffer transistors to decrease the
ouput impedance to get proper digital value
Fig 36: Design of RS Flip flop with bjt transistors
In fig 36 shows the bjt level design of Rs flip flop. In this circuit we used two transistors for
two inputs R and S and 100k ohm resistors is connected between R, S and base terminals of
two bjts. Here Q ,S are shorted and R , Qbar is shorted output is taken from the collectors of
another bjt transistor which acts like buffer which is used to get proper digital output
4.3 Final design of bjt level 555 timer circuit
Fig 36: bjt level design of 555 timer
In figure 36 is my final design of 555 timer using bjts and resistors . by usign this design I
implemented the monostable, Astable and bistable mode of 555 timer and decreased the power
dissipation of device as compared to the schematic operations are simulated in LTspice. But as
compared to proposed architecture here I used more transistors to get efficient output and
power dissipation. Here we used 32 transistors and 12 transistors In this Q1 to Q9 and Q17,
Q16 are used to design of Threshold comparator and Q9 to Q15 are used to design of trigger
comparator, Q18 to Q21 are used to design of RS flip flop Q22 to Q26 are used to make the
reset of the circuit, Q27 and Q29 are used for discharge the circuit Q29 to Q32 is used to design
the output portion of the circuit
Chapter 5
5.1 Monostable mode of bjt based 555 timer circuit
Fig 37: bjt level design of 555 timer’s monostable mode
In Fig 37 shows the monostable mode of bjt level 555 timer. In this circuit Vcc is connected to
5v dc supply and trigger pulse is applied at trigger pin of circuit which as time delay of 1ms
and discharge and threshold is shorted. 4.7k ohm is connected between Vcc and shorted circuit
of discharge and threshold terminal, 0.01uf capacitor is connected between control voltage
terminal and ground 10k ohm resistor are connected to output terminal of the circuit.
Output
Fig 38: input trigger pulse for monostable mode at bjt level
In Fig 31 shows the Input trigger pulse of 5v amplitude and 1ms delay which is taken at trigger
terminal of bjt level 555 timer monostable mode circuit
Fig 39: Output voltage for monostable mode at bjt level
In Fig 39 shows the output volatge vs time graph of 3.5v amplitude and delay of 1.25ms which
is seen at output terminal of bjt level 555 timer monostable circuit.
Fig 40: power dissipation graph for monostable mode at bjt level
In Fig 40 shows the power dissipation at 10k ohm resistor which is the 1.25mWatt at the output
terminal of the bjt level of 555 timer monostable circuit
5.2 Astable mode of bjt based 555 timer circuit
Fig 41: bjt level design of 555 timer’s astable mode
In Fig 41 shows the astable mode of bjt level 555 timer circuit. In this Vcc is connected to 5v
DC voltage supply, Threshold and trigger pin is shorted ,5k ohm resistor is connected between
Vcc and Discharge ,3k ohm resistor is connected between discharge and shorted circuit of
threshold and trigger terminals and 0.15uF capacitor is connected between 3k ohm resistor and
ground
Output
Fig 42: input voltage pulse of astable mode of bjt level 555 timer
In Fig 42 shows the input voltage of astable mode of bjt level 555 timer which is seen between
3k ohm resistor and capacitor of 0.15uF of bistable mode of schematic 555 timer circuit
Fig 43: Output voltage pulse of astable mode of bjt level 555 timer
In Fig 43 shows the the output voltage Vs time graph which is seen at Out terminal of astable
mode of schematic 555 timer circuit. Where the output is not stable it is fluctuating between
5v amplitude and ov amplitude
Fig 44: power dissipation of astable mode of bjt level 555 timer
In Fig 44 shows the power dissipation at 10k ohm resistor which is attached between Vcc and
output terminal of astable mode of bjt level 555 timer which is 2.5mWatt
5.3 Bistable mode of bjt based 555 timer circuit
Fig 45: bjt level design of 555 timer’s bistable mode
In Fig 45 shows the Bistable mode of bjt level 555 timer circuit implemented in the LT spice.
In this circuit Vcc is given with 12v of dc voltage and trigger pulse of 12v amplitude and 4ms
delay is given at trigger terminal of the circuit which 10ms far from the voltage axis. Another
trigger pulse is given to the reset pin which is 12v amplitude ,4ms delay and 50ms far from the
voltage axis and transient analysis done for 100 ms
Output
Fig 46: input trigger voltages of bistable mode of 555 timer at bjt level
In Fig 46 shows the input voltage pulse vs time which is seen between 3k ohm resistor and
capacitor of 0.15uF of bistable mode of bjt level 555 timer circuit
Fig 47: Output trigger voltages of bistable mode of 555 timer at bjt level
In Fig 47 shows the output voltage of bistable mode of bjt level555 timer here the voltage is
dropped between the two trigger pulse
CHAPTER 6
6.1 Improvements
By observing the above graphs finally, we conclude that power dissipation in the monostable
mode of bjt level 555 timer is less than the power dissipation in the monostable mode of
schematic 555 timer from above conclusion we can use this bjt level 555 timer in various
applications where low power dissipation in the circuit
6.2 Applications
1. Dark detectors
2. power alarms
3.schmitt trigger
4.Ramp generator
5. generating the square wave
6.3 Conclusion: 555 Timer is an integrated circuit used in various applications like timer,
pulse generation and oscillator, PWM applications. It is used to provide time delays and also
as a flip-flop element. It is cheap, stable, and user-friendly makes it the most popular IC ever
used. It can be connected with other external devices as well to design various electronic
circuits making it an ideal IC to be used in practical applications.
6.4 Future Work: 555 timer have various applications in the design of the electronic
circuits so still we have to design the architecture of 555 timer which has efficient power
consumption, usage of less transistors, efficient technology node to decrease the dimensions
and leakage currents in the device by implementing these parameters properly we can get
more stable 555 timer using the CMOS technology
6.5 Referances:
[1]. Jain, Monika, et al. "Detection of over speeding vehicles on highways." International Journal of
Computer Science and Mobile Computing 4.4 (2015): 613-619.
[2]. Shahid, Zeeshan, et al. "LM555 timer-based inverter low power pure sinusoidal AC output." World
applied science Journal (2014): 141-143.
[3]. Goyal, Himani. "Understanding of ic555 timer and ic 555 timer tester." International Journal of
Inventive Engineering and Sciences 3.2 (2015): 4-6.
[4]. Camenzind, Hans R., and Richard B. Kash. "A low-voltage IC timer." IEEE Journal of Solid-State
Circuits 13.6 (1978): 847-852.
[5].“Signetics analog data manual,” pp. 243-245; 717-733, 1977.
[6]. Bohare, Abhishek. "Study of Timer IC 555."
[7]. Shakir, Muhammad, et al. "555-timer and comparators operational at 500° c." IEEE Transactions on
Electron Devices 66.9 (2019): 3734-3739.
[8]. Abrar, Md Moyeed. "Design and implementation of astable multivibrator using 555 timer." IOSR J.
Electr. Electron. Eng 12.1 (2017): 22-29.
[9] Ravishankar, M. K., and M. Satyam. "Optically/electrically (symmetrically) triggerable bistable
multivibrator." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 43.7
(1996): 610-612.
[10].To, Hing-Yan, and Mohammed Ismail. "Mismatch modeling and characterization of bipolar transistors
for statistical CAD." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
43.7 (1996): 608-610.