MODULE 1
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Syllabus
Evolution of Microprocessor, 8086 Microprocessor -Architecture
and signals, Memory organisation , Minimum and maximum
mode of operation, Minimum mode Timing Diagram.
Comparison of 8086 and 8088.
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Evolution of Microprocessor:
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•
•
a.
-
Microprocessor is identified with word size.
The evolution of microprocessor are based on speed.
Intel Microprocessors are
4 bit processors:
INTEL 4004,INTEL 4040
ALU perform 4 bit of data at a time
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b. 8 bit processors:
- 8008, 8080, 8085, MOTOROLA 6800
- ALU take 8 bit of data at a time
c. 16 bit processors:
- 8086,8088,zilog2800,80/86,80286
- ALU perform 16 bit of data at a time
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d. 32 bit processors:
- INTEL 80386, 80387,80486
- INTEL PENTIUM,
INTEL PENTIUM PRO,
INTEL
PENTIUM2 , INTEL PENTIUM 3, INTEL PENTIUM 4
- ALU perform 32 bit operation at a time.
e. 64 bit processors
- speed is very fast
- INTEL CORE2, INTEL CORE I7, INTEL CORE I5, INTEL COREI3
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8086 - Register set
• 8086 has a powerful set of registers known as general
purpose and special purpose registers.
• The general purpose registers can be used as either 8-bit or
16- bit registers.
• They may be either used for holding data, variables and
intermediate results temporarily or for other purposes like
counter.
• The special purpose registers are used as segment registers ,
pointers, index registers or as offset storage registers for
particular addressing modes.
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Fig 1.1 Registers organization of 8086
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General Purpose Register
• The registers AX,BX,CX and DX are the general purpose 16- bit
registers.
• AX is used as 16- bit accumulator, with lower 8- bits of AX
designated as AL and higher 8- bits as AH.
• Usually the letter L and H specify lower and higher bytes of a
particular register.
• The CX register is also used as a default counter in case of
string and loop instructions.
•
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• The CH means the higher 8- bits of the CX register and CL
means the lower 8- bits of the CX register.
• The letter X is used to specify the complete 16- bit
registers.
• The register BX is used as an offset storage for forming
physical addresses in case of certain addressing modes.
• The DX register is a general purpose register which may
be used as an implicit operand or destination in case of
few instructions.
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Special Purpose Register
 Segment Registers
• The complete 1 megabyte memory, which the addresses, is
divided into 16 logical segments.
• Each segment thus contains 64Kbytes of memory.
• The four segment registers are Code Segment Register (CS),
Data Segment Register (DS), Extra Segment Register (ES) and
Stack Segment Register (SS).
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• Code segment register (CS): is used for addressing memory
location in the code segment of the memory, where the
executable program is stored.
• Data segment register (DS): points to the data segment of the
memory where the data is stored.
• Extra Segment Register (ES): also refers to a segment in the
memory which is another data segment in the memory.
• Stack Segment Register (SS): is used for addressing stack
segment of the memory.
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• The stack grows down, ie, the data is pushed onto the stack in
the memory locations with decreasing addresses.
• When this information will be required by the CPU, they will
be popped off from the stack.
• The physical address calculated from two parts, the first is
segment address and the second is offset.
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• The segment registers contains 16- bit segment base
addresses related to different segments.
• Any of the pointers and index registers or BX may contain the
offset of the location to be addressed.
• These segment registers are the logical segments.
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 Pointers and Index Registers
• The index registers are used as general purpose registers as
well as for offset storage in case of indexed, based indexed
and relative based indexed addressing modes.
• SI - store the offset of source data in the data segment
• DI - store the offset of destination in data or extra segment.
• The index registers are used for string manipulations.
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• The pointers contain offset within the particular segments.
• The pointers IP, BP, and SP usually contain offsets within the
code (IP), and stack (BP & SP) segments.
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
•
•
a.
b.
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Flag Registers
It indicate the results of computations in the ALU.
8086 has a 16- bit flag registers which is divided into two parts
Condition code or status flags
Machine control flags
The condition code flag register is the lower byte of the 16- bit
flag register along with the overflow flag.
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• The control flag register is higher byte of the flag register of
8086.
• It contains
- Direction flag (D)
- Interrupt flag (I)
- Trap flag (T)
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Fig 1.2: Flag register of 8086
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Condition Flag
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Control Flag
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8086 - Architecture
•
•
•
•
It is 16 bit microprocessor.
It support 16 bit ALU.
The 8086 architecture divided into two parts:
Bus Interface Unit (BIU)
Execution Unit (EU)
Fig 1.3 : 8086 a/c
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• Bus Interface Unit
- Contains the physical address calculations and a predecoding
instruction byte queue.
- This unit is responsible for establishing communications with
external devices, peripherals including memory via the bus.
- The physical address is a summation of segment address and
offset address.
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- The content of segment register is also called segment
address is shifted left bit wise four times and to this result.
- Content of offset register called offset address.
- Add segment address and offset address produce 20 bit
physical address.
- Each segment have accommodate 64K locations.
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- eg:
Segment address -> 1005H
Offset address -> 5555H
Segment address -> 0001 0000 0000 0101
Shifted by 4 bit positions ->0001 0000 0000 0101 0000 +
Offset address
->
0101 0101 0101 0101
Physical address
->0001 0101 0101 1010 0101
1
5
5
A 5
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

Segment address – code, stack, data and extra segment.
Offset address - IP,BX,SI,DI,SP,BP
Precoded instruction byte queue.
The fetched instruction is executed internally,
The external bus is used to fetch the machine code of the next
instruction and arrange it in a queue.
 It is 6 byte long
 FIFO structure
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• Execution Unit
- Contains the register set of 8086 except segment registers and
IP.
- It has 16 bit ALU, which performs arithmetic and logical
operations.
- The 16 bit flag register reflects the results of execution by the
ALU.
- The decoding unit decodes the opcode bytes issued from
instruction byte queue.
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- The timing and control unit derives the necessary control
signals to execute instruction opcode received from the
queue, depending upon the information made available by
the decoding circuit.
- The execution unit may pass result to the bus interface unit
for storing them in memory.
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Memory Segmentation
• Each segment is 64K bytes in sizes and addressed by one of
the segment registers.
• The 16 bit contents of the segment register actually point to
the starting location of a particular segment.
• The offset address is also 16 bit long so that maximum offset
value can be FFFFH, and the maximum size of any segment is
thus 64K locations.
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• The CPU 8086 is able to address 1Mbytes of physical memory.
• The complete 1Mbytes memory can be divided into 16
segments, each of 64Kbytes size.
• The addresses of the segment may be assigned as 0000H to
F000H respectively.
• The offset address values are from 0000H to FFFFH so that the
physical addresses range from 00000H to FFFFFH.
• A segment starts at a particular address and its maximum size
can be 64Kbytes.
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• Non-Overlapped Segment – A segment starts at a particular
address and its maximum size can go up to 64kilobytes.
• But if another segment starts before this 64kilobytes location
of the first segment, then the two segments are said to be
Non-Overlapped Segment.
• But, if another segment starts before this 64K bytes locations
of the first segment, the two segments are said to be
overlapping segments.
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• The area of the memory from the start of the second segment
to the possible end of the first segment is called an
overlapped segment area.
• In the overlapped area location physical address = CS1+IP1=
CS2+IP2 where ‘+’ indicates the procedure of physical address
formation.
• Fig 1.2 (a) shows non overlapping segments and Fig 1.2(b)
shows overlapping segments.
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(a)
(b)
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Signal Description
• The 8086 signals can be categorized in three groups.
– Signals having common functions in minimum as well as
maximum mode
– Signals which are special functions for minimum mode
– Signals having special functions for maximum mode
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Fig 1.3: signal description
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1. GND
- Ground the internal circuit.
2. Address/Data bus
- AD0-AD15
- These are 16 bit address/data bus
- AD0-AD7 carries low order byte data and AD8-AD15 carries
higher order byte data.
- During the first clock cycle , it carries 16 bit address and after
that it carries 16 bit data.
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3. NMI
- Non Maskable Interrupt
- Available at pin17
- Edge triggered input, which causes an interrupt request to the
microprocessor.
4. INTR
- It is available at pin18
- It is an interrupt request signal , which is sampled during the
last clock cycle of each instruction to determine if the
processor considered this as an interrupt or not.
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5. CLK
- It is available at pin 19.
- It provides timing to the processor for operations.
- Its frequency is different for different versions, ie, 5MHz,
8MHz and 10MHz
6. RESET
- It is available at pin 21
- Used to restart the execution
- It causes the processor to immediate terminate its
present activity.
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7. READY
- It is available at pin 22
- It is an acknowledgement signal from I/O devices or memory
that data is transferred.
- It is an active high signal.
- When it is high, device is ready to transfer data.
- When it is low, it indicate wait state.
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8.TEST
- This signal is like wait state
- Available at pin 23
- When this signal is high, then the processor has to wait for
IDLE state, else, the execution continuous.
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9.QS1 and QS0
- Queue status
- It available at pin 24 and 25
- Status of instruction queue
- While the execution unit is busy in executing an instruction,
after it is completely decoded,
o the bus interface unit may be fetching the bytes of the next
instruction from memory,
o depending upon the queue status.
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10. S0,S1,S2
- Status signal
- It provide status operation.
- Generate memory and I/O control signal
- Available at pin 26,27,28
11. LOCK
- Available at 29
- This signal active at the processors not to ask the CPU to leave
the system bus.
- When the CPU is executing a critical instruction which
requires the system bus, the LOCK prefix instruction ensures
that other processors connected in this system will not gain
the control of the bus.
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12.RQ/GT1 and RQ/GT0
- These are Request/Grant signal.
- It used by the other processors requesting the CPU to release
the system bus.
- When the signal is received by the CPU, then it sends
acknowledgement.
- RQ/GT0 has a higher priority than RQ/GT1.
13.RD
- Read operation
- Available at pin 32
- Used to read signal for read operation.
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14.MN/MX
- Stands for minimum/maximum
- Available at pin 33
- It indicate what mode the processor is to operate in.
- When it is high, it works in the minimum mode operation.
- When it is low, it works in maximum mode operation.
15.S7/BHE
- BHE- Bus High Enable
- It is available at pin 34
- It is used to indicate the transfer of data using data bus D8D15.
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16.Address/Status bus
- A16-A19/S3-S6
- These are the 4 address/status buses.
- During the first clock cycles, it carries 4-bit address and later it
carries status signals.
17.VCC
- +5V power supply for the operation of the internal circuit.
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18. INTA
- It stands for Interrupt Acknowledgement.
- When micro[processor receives this signal, it acknowledges
the interrupt.
- Available at pin 24.
19. ALE
- Address Latch Enable
- Available at pin 25.
- +ve pulse is generated each time the processor begins any
operation.
- The signal indicates the availability of a valid address on the
address/data line.
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20. DEN
- Data Enable
- Available at pin 26
- Used to enable transciever
- Transciever is a device used to separate data from the
address/data bus.
21. DT/R
- Data Transmit/Recieve signal
- Available at pin 27
- It decides the direction of data flow through the transciever.
- When it is high, data is transmitted.
- When it is low, data is recieved
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21. M/IO
- Used to distinguish between memory and I/O.
- When it is high, I/O operation.
- When it is low, memory operation.
- It is available at pin 28
22. WR
- Write signal.
- Available at pin 29
- Write the data into the memory or the output device.
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23. HLDA
- It stands for Hold Acknowledgement
- Available at pin 30
- Acknowledges the HOLD signal
24. HOLD
- It is available at pin 31
- This signal indicates to the processor that external devices are
requesting to access the address/data buses.
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Minimum Mode 8086 system and
timing
• The microprocessor 8086 is operated in minimum mode by
strapping its MN/MX pin to logic 1.
• There is a single microprocessor in the minimum mode
system.
• The remaining components in the system are latches,
transreceivers , clock generator, memory and I/O devices.
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Fig 1.4: minimum mode 8086
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• Latches
- It is generally buffered output D-type flip-flops like 74LS373 or
8282.
- They are used for separating the valid address from the
multiplexed address/data signals.
- It is controlled by the ALE signal generated by 8086.
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•
-
Transreceivers
It is bidirectional buffers
Some times they are called as data amplifiers.
They are required to separate the valid data from the time
multiplexed address/data signals.
- They are controlled by two signals namely, DEN and DT/R.
- The DEN signal indicates the direction of data, i.e. from or to
the processor.
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•
•
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Memory and I/O devices
EPROM - monitor storage
RAM - user’s program storage
A system may contain I/O devices.
Clock generator
IC 8284
Generates the clock from crystal oscillator and then shapes it
to make it more precise so that it can be used as an accurate
timing reference for the system.
- It also synchronize some external signal with system clock.
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Timing diagram
• The opcode fetch and read cycles are similar.
• Hence the timing diagram can be categorized in two parts, the
first is the timing diagram for read cycle and the second is the
timing diagram for write cycle.
• The read cycle begins in T1 with the assertion of address latch
enable (ALE) signal and also M / IO signal.
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• During the negative going edge of this signal, the valid address
is latched on the local bus.
• The BHE and A0 signals address low, high or both bytes.
• From T1 to T4 , the M/IO signal indicates a memory or I/O
operation.
• At T2, the address is removed from the local bus and is sent to
the output.
• The bus is then tristated.
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• The read (RD) control signal is also activated in T2.
• The read (RD) signal causes the address device to enable its
data bus drivers.
• After RD goes low, the valid data is available on the data bus.
• The addressed device will drive the READY line high.
• When the processor returns the read signal to high level, the
addressed device will again tristate its bus drivers.
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• A write cycle also begins with the assertion of ALE and the
emission of the address.
• The M/IO signal is again asserted to indicate a memory or I/O
operation.
• In T2, after sending the address in T1, the processor sends the
data to be written to the addressed location.
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• The data remains on the bus until middle of T4 state.
• The WR becomes active at the beginning of T2.
• The BHE and A0 signals are used to select the proper byte or
bytes of memory or I/O word to be read or write.
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Maximum Mode 8086 system
• In the maximum mode, the 8086 is operated by strapping the
MN/MX pin to ground.
• In this mode, the processor derives the status signal S2, S1,
S0.
• Another chip called bus controller derives the control signal
using this status information.
• In the maximum mode, there may be more than one
microprocessor in the system configuration.
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Fig 1.4 : Maximum mode configuration
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• The basic function of the bus controller chip IC8288, is to
derive control signals like RD and WR ( for memory and I/O
devices), DEN, DT/R, ALE etc. using the information by the
processor on the status lines.
• The bus controller chip has input lines S2, S1, S0 and CLK.
These inputs to 8288 are driven by CPU.
• It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC,
IORC, IOWC and AIOWC. IORC, IOWC are I/O read command
and I/O write command signals respectively .
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• These signals enable an IO interface to read or write the data
from or to the address port.
• The MRDC, MWTC are memory read command and memory
write command signals respectively and may be used as
memory read or write signals.
• All these command signals instructs the memory to accept or
send data from or to the bus.
•
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Comparison b/w 8086 & 8088
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