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Overvoltage and Ringing in a State-of-the-art SiC MOSFET Power Module for
Traction Inverters
Conference Paper · November 2020
DOI: 10.23919/AEITAUTOMOTIVE50086.2020.9307430
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2020 AEIT International Conference of Electrical and Electronic Technologies for Automotive
Overvoltage and ringing in a state-of-the-art SiC MOSFET Power Module for
traction inverters
Antonio Riccardo Fallico
Santi Agatino Rizzo
Angelo Raciti
Fabio Mandrile
Salvatore Musumeci
Luigi Abbatelli
Elena Venuti
Document Version:
Accepted author manuscript, peer reviewed version
Citation for published version:
A.R. Fallico, S.A. Rizzo, A. Raciti, F. Mandrile, S. Musumeci, L. Abbatelli, E. Venuti, “Overvoltage and
ringing in a state-of-the-art SiC MOSFET Power Module for traction inverters”, AEIT International
Conference of Electrical and Electronic Technologies for Automotive, online, Nov 18-20, 2020.
DOI: 10.23919/AEITAUTOMOTIVE50086.2020.9307430
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works.
Overvoltage and Ringing in a State-of-the-art SiC
MOSFET Power Module for Traction Inverters
Antonio R. Fallico
Santi A. Rizzo,
University of Catania
Catania, Italy
a.riccardo.fallico@gmail.com
santi.rizzo@dieei.unict.it
Angelo Raciti
IMM - Consiglio Nazionale delle
Ricerche (CNR)
Catania, Italy
angelo.raciti@dieei.unict.it
Abstract—Research teams from industry and academia have
highlighted the advantages obtained from the introduction of
Silicon Carbide (SiC) traction inverter power modules.
Similarly, commercial solutions already benefit from SiC
traction inverter in terms of performance as well as in terms of
economical investment. Notwithstanding, the good features
there are some issues due to the fast switching ability of SiC
MOSFET. In such a contest, is the fine-tuning of a proper
simulation tool is the first for an optimal design of the
conversion systems, especially, the snubbers necessary to
mitigate turn-off overvoltage and ringing of SiC MOSFET
devices. In this perspective, this paper combines Ansys Q3D
analysis and Spice simulations to foresee the SiC MOSFET
Power Module waveforms. The experimental results have
highlighted a good accuracy of the tool at predicting the
performance of the module and the boundary operating
conditions.
Keywords—automotive, overvoltage, parasitic inductance,
ringing, SiC MOSFET, Spice
I. INTRODUCTION
The growing global energy consumption and the concerns
about a sustainable future have pushed towards more efficient
power conversion systems. Moreover, the reduction of the size
and the increment of the switching frequency are also a longestablished trend in static power converters.
SiC MOSFETs feature low on-resistance, high switching
speed. high voltage-blocking capability and high working
temperature [1]. Moreover, the low body-diode reverserecovery current, the low parasitic capacitances, and the
absence of the tail recovery current make SiC MOSFETs an
increasingly more interesting technology in several high
frequency converter applications [2]. As a matter of the fact,
conduction losses reduction is one of the main advantages in
traction inverter.
The fast switching ability of SiC MOSFET involves lower
switching losses at cost of some concerns due to the increased
overvoltages and oscillations. More specifically, the parasitic
inductances in the layout combined with the faster switching
speed worsens the phenomenon of overvoltage and related
ringing issues [3]. Analysis of these quantities is a critical
factor in assessing the limiting conditions and the maximum
rating for the converter in terms of rated voltage, switching
frequency, EMI, and so on. Moreover, any optimal design of
the conversion system, especially, the snubbers necessary to
mitigate turn-off overvoltage and ringing of the SiC MOSFET
devices, asks for simulation tools able at foreseeing the
waveform of different power module designs.
In this paper, firstly, Ansys Q3D has been used for the
evaluation parasitic inductances of the interconnections. Then,
978-8-8872-3749-8 ©2020 AEIT
Fabio Mandrile
Salvatore Musumeci,
Politecnico di Torino
Torino, Italy
salvatore.musumeci@polito.it
fabio.mandrile@polito.it
Luigi Abbatelli,
Elena Venuti
STMicroelectronics
Catania, Italy
luigi.abbatelli@st.com
elena.venuti@st.com
these quantities are used with the SiC MOSFET SPICE model
to estimate the turn-off overvoltage and ringing into the
switching devices. The effectiveness of using the 3D Finite
Element Method (FEM) in conjunction with the SPICE
simulation has been confirmed by the experimental results.
More specifically, the case study of concerns a solid-state
power module for automotive traction inverter application.
The module has three legs, each switch contains 8 die of SiC
MOSFET connected in parallel, thus there are 48 die in the
traction inverter module.
The paper is organized as follows. Section II firstly reports
an overview of the advantages of Silicon Carbide MOSFET
and the performance boost it brings, then Section II presents a
comparison between SiC MOSFET and traditional silicon
semiconductor devices in different converter applications,
with emphasis on the case study of the power module. In
section III the stray inductance extraction method with Ansys
Q3D using FEM analysis as well as the behavioral model of
the SiC MOSFET are discussed. Section IV deals with the
simulation of a double pulse test performed on the inverter leg
and the comparison with the experimental results obtained in
the laboratory test-rig.
II. COMPARISON BETWEEN SIC MOSFET AND SI IGBT
SiC MOSFETs are a good choice in all applications where
high power densities, high efficiency and high reliability are
required [2]-[4]. In this Section a brief overview of the
interesting features of SiC and the advantages it brings when
used as a substrate for MOSFETs (part A) are done. A
comparison with IGBT (part B) is given, with a focus (section
C) on module implementation of multiple devices in parallel.
A. SiC Material Advantage
SiC allows realization of power devices with improved
characteristics compared to Silicon devices having the same
blocking-voltage rating. SiC material has three times higher
energy gap, breakdown electric field and doubled carrier
mobility compared to Si [1], [4], [5]. These properties enable
to obtain drift regions with block high-voltages and low
forward voltage-drop [5]. The drift-region resistance is the
main component that contributes to the overall specific onresistance of MOSFETs designed for medium to high-power
applications [6]. SiC devices allow for a theoretical reduction
of such a component by a factor up to 100 compared to the
one of the Si MOSFETs [2], [7], [8]. Even using a super
junction (SJ) structure, SiC MOSFET’s specific on resistance
remains lower when compared to the state-of-the-art Si
devices in the 600 to 900 V voltage ratings [9]. Higher energy
gap and lower doping concentration required for a fixed
breakdown voltage lower the intrinsic carrier concentration in
the devices, making SiC MOSFET quantities, like the on-state
resistance and the reverse recovery current, less sensitive to
temperature variations.
operations at four-times higher switching-frequency, bringing
passives size reduction and lower cooling requirements.
SiC allows to realize devices with higher power rating and
reliability due to the higher thermal conductivity and melting
point [10], [11]. Lower intrinsic carrier concentration also
determines lower leakage currents during the blocking state,
and lower diode reverse-recovery currents at turn-off.
Advantages brought to the system by SiC power devices are
higher power density, increased efficiency, and high
switching speed, resulting in cost savings and size reduction
due to the low cooling needs and the low filtering
requirements [8].
C. Power Module with SiC MOSFETs
Many system advantages of using SiC MOSFETs in
power modules make it a valid competitor to traditional
devices in automotive and industrial applications [28]. The
absence of the tail current together with almost negligible
reverse-recovery current-peak of the body-diode bring
significant switching loss reduction in SiC based power
modules [36]. Lower conduction and switching losses, higher
SiC thermal conductivity and operating temperature together
with modules low thermal resistance significantly improve the
efficiency and leave room for a substantial increase in
switching frequencies and power density [37], [38].
In [9] a comparison between bridge configurations of SJ
and SiC MOSFETs shows how the better diode recovery
characteristic of the latter produces ten times decrease in the
overall switching losses. High electron saturation velocity
contributes to the lower drift region resistance and to the
higher switching frequency of devices fabricated with SiC
substrate, giving better dynamic response [10], [12]. Factors
that have been damping SiC adoption during the last 10 years
were small wafer diameters available (3 inches), higher raw
material cost and poor epitaxial layer quality, with many
defects lowering the breakdown voltage [13], [14]. Currently
[10], [15] 6 inches wafer are available with improved substrate
quality with low density of defects [16]. Focusing on the
MOSFET structure, the major reasons for concern were oxide
interface traps and bulk defects as well as the high electric
field stress on the gate oxide [14], [17]. Moreover, early
manufactured devices presented threshold voltage shifts and
low channel inversion region mobility [14], [18], [19], now
solved by using improved shielding of the p regions and the
oxide nitridation processes looking to increase the mobility
[12], [20], [21].
B. SiC MOSFET and Si IGBT comparison
SiC MOSFETs adoption in power converters yields
consistent savings in system costs or in long term costs as well
as improved efficiency and power density [22], [23]. Thus SiC
MOSFETs are now used in hard switching applications such
as telecom [24] and high-end server power supplies [25], solar
inverters [26], automotive applications like inverter motor
drives and on board chargers (OBC) [10], [27], [28], being an
increasingly more valid alternative to IGBT.
Lower specific on-state resistance results in smaller dies
with overall smaller gate charge and parasitic capacitances [4],
[29]. The consequent shorter transients allow for a consistent
reduction in the switching losses. Moreover, being majority
carrier devices, MOSFETs do not exhibit any tail current
during the turn-off transient compared to IGBTs, which
further lowers the turn-off energy loss. SiC MOSFETs have a
rugged body-diode with almost no reverse recovery current
and forward characteristics practically independent [30] from
temperature variations, that is very suitable for four-quadrant
operations in bridge configurations [10], so allowing for
significant reductions in the turn-on losses and the total die
area [31]. In particular, the use in FET/FET bridge
configurations and DC-DC converter application yields major
savings in the dissipated power [32]-[34].
In converter applications [35] SiC MOSFETs enable
higher efficiency and switching frequency, giving a threetimes lower turn on energy Eon and four-times lower turn off
energy Eoff, even at high temperatures thus enabling
Together with the above advantages, SiC MOSFETs bring
also new issues that need to be addressed. Higher di/dt
together with the stray inductances cause voltage peaks at
turn-off across the device terminals. During turn-on in half
bridge configurations, the parasitic inductance and the body
diode reverse-recovery current peak causes voltage spikes
across the terminals of the complementary device in the same
leg. These parameters require both a careful analysis and
design of the converter layout to reduce EMI, crosstalk and
excessive stresses during commutation [39]. As the body
diode shows less reverse-recovery current, the focus shifts on
the voltage spikes induced by the high di/dt during the device
turn-off as major cause of reliability issues and even failure
[40]. This problem is even more important in automotive
applications, where sudden high power is required frequently
[41]. The use of modules, which connect multiple devices in
parallel at close distance, is the best way to address these
problems in high-power and high-voltage applications, thus
reducing the parasitic inductance associated with the
conductive path between dies [21] as well as increasing the
reliability and the power density. Dynamic performance of
SiC MOSFET demands efforts of R&D to focus on modelling
accurately and reducing the parasitic inductance between dies
while guaranteeing the reliability [42]. Using multiple dies in
parallel in practical applications introduces issues of current
imbalance both in static and dynamic operations. The
parameters spread of the devices like parasitic capacitance and
threshold voltage, parasitic mismatches on the power layout
contribute to the latter problems, calling for a careful module’s
layout design [43]-[45]. Gate loop has a minor effect on
switching waveforms but it generates ringing in the gate
terminal when resonating with the input capacitance,
especially in modules unless the path from the driver to the
gate and source pins is optimized [46].
Another important issue to address in power modules is
the coupling between the output node voltage in half bridge
configurations and gate terminals through parasitic
capacitances. Exceeding the maximum negative rating of the
gate voltage worsens both the reliability and ruggedness,
while a positive glitch causes an increase on losses. Efficient
ways to reduce these effects is the adoption of active Miller
clamps and higher turn off resistance in the drive [47], [48].
Gate glitches bring together with oxide degradation the risk of
spurious turn-on of the complementary device, posing
unwanted short circuit operation of the bridge leg.
III. CIRCUIT MODEL
In this work the effect of the parasitic inductances is
studied on an experimental three-phase automotive traction
inverter module. The focus is on the turn-off overvoltage spike
of a single leg of the inverter. The module fits 16
main switching loop, the gate drive loop, and both the loops.
These main parasitic components are depicted in Fig. 2.
Fig. 1. Module leg's layout and schematic diagram.
Fig. 3. Main lumped inductive parasitic component of the half bridge leg.
The voltage overshoot and 𝐸
increase with 𝐿 , while
the drain current spike and 𝐸 decrease with the 𝐿 . 𝐿
inductance lowers the overall stresses on the device with its
feedback effect but increases both the turn on and turn off
energies [39], [45].
Fig. 2. Main inductive and capacitive parasitic parameters.
1200 V, 30 𝑚Ω SiC MOSFETs per leg, 8 dies in the upper
switch and 8 dies in the lower switch, with 48 total devices. In
Fig. 1 is shown the layout of the single leg inside the module.
Analysis and simulation of the turn-off overvoltage requires
the knowledge of several items: the parasitic inductance of the
interconnections between the dies and the Kelvin terminals
extracted using Ansys Q3D through a FEM analysis (Sec. A)
and the behavioral model of the SiC devices (Sec. B). Results
of both sections are used in a simulation of a double pulse test
using LTSpice (Sec. C) to analyse the turn-off voltage spike
and the ringing transient.
A. FEM
In hard switching conditions, the layout parasitic inductances
together with MOSFETs’ internal parasitic capacitances cause
a voltage overshoot and parasitic oscillations during the turnoff transient, that are caused by high di/dt. If not damped, the
overvoltage spike during the turn-off may bring the device in
avalanche breakdown and then to the failure. To prevent the
ringing caused by the interaction between the stray inductance
and the internal parasitic capacitance from coupling through
the 𝐶 capacitance to the gate terminal causing unwanted
turn-on, Miller clamping techniques are adopted in the gate
drive configurations together with a hard turn-off gate voltage
of -5 V [33], [48]. In [3], [39] the cumulative effect of the
package, the board, and the die inductance are studied by
experiments, by considering their effects with three main
inductances associated with the drain 𝐿 , gate 𝐿 and source
𝐿 terminal. These are associated correspondingly with the
Packaging multiple devices in a power module reduces the
parasitic phenomenon due to the bonding wires, leads and
PCB traces, leaving only the components associated with the
copper plate and the sintering interconnections between the
dies, the sensing terminals and the input/output terminals.
The CAD model containing the geometry of the module
together with information of the materials are imported in the
software Ansys Q3D to perform a FEM analysis, which gives
the values of the parasitic components in terms of a matrix of
inductances and resistances. To lighten the computational
burden on the Spice simulator, the inductances associated with
the main switching loop of the half-bridge are lumped in the
components shown in Fig. 3. The values are given in Table I.
Q3D extractor has been used to determine these contributes
for each main terminal of the module, that is: the busbars P,
N, and Out; high and low side Kelvin Drain and Kelvin
Source; solder points of the dies and bonding wires to the
module.
B. MOSFET Behavioral Model
In the SPICE simulation, a behavioral model of the SiC
MOSFET is used (Fig. 2). The model is based on the static and
dynamic characterization of the device. In other terms, the
model emulates the main aspects of the device: the output
characteristics 𝑖 − 𝑣 ; the transfer characteristics; the gate
charge as function of the gate-source voltage; input 𝐶 ,
output 𝐶 , and 𝐶 reverse parasitic capacitances as a
function of 𝑣 , the breakdown voltage, the switching energy
on resistive and inductive load, the temperature and bodydiode characteristics.
Curves obtained from interpolating the experimental
results [49] are then fed to the behavioral current sources,
giving a light burden for the computational and physical
description of the device.
TABLE I.
LUMPED PARASITIC INDUCTANCES
Inductance
Resistance
Name
Value
Unit
Value
Unit
LA
LB
LC
LD
LE
LF
LG
LH
LI
LJ
LK
LL
LM
4.45
27.00
2.69
33.00
295.00
965.00
9.06
2.52
27.00
14.00
33.00
2.57
1.20
𝑛𝐻
𝑓𝐻
𝑛𝐻
𝑝𝐻
𝑝𝐻
𝑝𝐻
𝑛𝐻
𝑛𝐻
𝑓𝐻
𝑛𝐻
𝑝𝐻
𝑛𝐻
𝑛𝐻
0.1818
0.0001
0.0700
0.0325
0.0260
0.0300
0.0300
0.1688
0.0001
4.1900
0.0325
0.0584
0.0420
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
𝑚Ω
Fig. 5. Double pulse test schematic.
As freewheeling diode of the configuration, the internal
body-drain junction of the eight higher side MOSFETs is
used.
The gate driver controls the low side devices deploying
two nMOS in a push-pull configuration, which have a driving
capability of 5 A, tailored to drive the total gate charge 𝑄 ≃
600 𝑛𝐶 of the eight paralleled devices in a rise time below 120
𝑛𝑠. Driving voltage values of 18V and -5 V, typical of SiC
and the
MOSFET devices, are used to minimize the 𝑅
switching losses and circumvent the threshold shifting as well
as to reduce the occurrence of the Miller turn-on phenomenon
[33], [47], [48]. Similar reasons led to use a 5.6 Ω as turn off
resistor and a 3.3 Ω as turn on resistor.
The test procedure is the following:
1. (𝑡 ÷ 𝑡 = 1 𝜇𝑠) the test starts with the DUT in off state,
the DC-Link capacitor charged up to 700 V and with no
current in the load inductor;
Fig. 4 Schematic of the MOSFET behavioral model. Credit by [49].
IV. SIMULATIONS
In this Section a brief description of the simulation setup
in LTSpice and the results found in terms of turn-off
overvoltage and ringing transient with relative voltage and
current waveforms are given. The simulated results are then
compared with the experimental data extracted by some tests
performed on the module. In part A, the double pulse test and
the measurement conditions are described while, in part B,
these results are compared with the bench experimental
results.
A. Double Pulse Test
To perform the dynamic analysis of the device
performance on the module, a double pulse test is used, which
reproduces hard switching on a clamped inductive load, a
common occurrence in many converter applications [50]. The
LTSpice schematic of the virtual test bench is shown in Fig 5.
In the test, the following quantities are used. A DC link
capacitor of 300 𝜇𝐹 with 855 V rated voltage, a 15 𝑛𝐻
equivalent series inductance (ESL), a 0.8 𝑚Ω equivalent
series resistance (ESR) are connected to a 700 V DC bus
voltage generator. Eight parallel SiC MOSFETs compose a
switch of the leg, each with 1.2 kV breakdown voltage 𝐵𝑉 ,
30 𝑚Ω on-resistance Rdson and 75 A drain current 𝐼 . An air
core inductor is used as load, modelized with an inductance
value of 6 𝜇𝐻 inductance, a 5 𝑚Ω ESR and parasitic
capacitance of 300 𝑝𝐹.
2. (𝑡 ÷ 𝑡 = 4.14 𝜇𝑠) at time 𝑡 the switch is turned on by
the gate drive and the freewheeling body diode blocks the
bus voltage so that the current through the inductor and
through the switch reaches the test current of 500 A, the
process takes 4.14 𝜇𝑠 with an inductance of 6 𝜇𝐻;
3. (𝑡 ÷ 𝑡 = 3.86 μs) at 𝑡 the DUT is turned off and the
diode turns on, clamping the drain of the DUT to the bus
voltage. During this process, the DUT turns off and the
voltage 𝑣 and the current 𝑖 waveforms are acquired;
4. (𝑡 ÷ 𝑡 = 3 𝜇𝑠) at 𝑡 the DUT is turned on again and the
diode turns off, releasing the reverse recovery current,
𝐼 , together with the load current back to the DUT.
During this time interval the turn-on waveforms are
acquired.
B. Simulation Results
Fig. 6 shows the turn-off transient and the gate source
voltage 𝑣 , drain current 𝑖 , and drain source voltage 𝑣
waveforms of the low side MOSFETs. Focusing on step 3 of
the previous part, as the inductive load is switched, the voltage
across the DUT increases until it reaches the bus voltage and
only after this phase the current starts flowing in the freewheel
body-diode on the high side. This is a typical commutation
behaviour, with the load that experience the current increase,
similar to the current in inductive loads. During this phase, the
output capacitance of the DUT forms an RLC network with
the parasitic inductance and with the on-state resistance of the
MOSFETs. Though the diode provides clamping when
switching the highly inductive load, it does not clamp the stray
inductance mentioned above. This inductance reduces the 𝐸
due to voltage drop across the inductor during turn-on and
Fig. 1. Simulation waveforms during a switching cycle: vgs, id, and vds of
devices.
limits the reverse-recovery current of the upper body diode.
At turn-off, the negative di/dt causes high overvoltage in the
devices, as there is no other path left for the current in the
inductor to return the energy. Together with the output
capacitance of the MOSFETs, the inductance also creates a
ringing transient overlapped to the turn-off voltage and current
waveforms with a frequency that is depending on the values
of 𝐶 and 𝐿.
Fig. 7. Experimental waveforms during a switching cycle.
As can be seen, during the turn-off transient of the low side
devices a voltage peak of 985 V appears across the devices,
which is followed by an oscillation at a frequency equal to
28.6 MHz. These results are compatible with the preliminary
analytic evaluation made using [51] as reference, obtained by
using the following relation to determine the overvoltage 𝑉 :
𝑉
𝑡 =
𝐼 𝐿
𝐸𝑆𝐿
.
1−
𝑇
𝑒
sin 𝜔
1−𝜁
1−𝜁
Φ
(1)
where 𝑇
is the turn off time, 𝐼 the drain current, 𝜁
damping factor, 𝜔 resonance frequency and Φ phase shift
given by the relation (2), (3) and (4)
𝑅 𝐶
𝜁=
2 𝐿
(2)
1
𝜔 =
(3)
√𝐿𝐶
Φ = arccos ζ
(4)
in which:
- 𝑅 is a resistance whose value averages the effect of the gate
of the devices 𝑅 ≃ 0.31 Ω;
drive resistor and the 𝑅
- 𝐿 is the sum of the inductance of the main switching loop
and the parasitic inductance 𝐸𝑆𝐿 of the DC-link
𝐿
capacitor 𝐸𝑆𝐿 , :
- 𝐿
=𝐿
𝐿
𝐿
𝐿
𝐸𝑆𝐿
𝐿=𝐿
𝐿
𝐿
𝐿
𝐿 ≃ 10 𝑛𝐻
= 15 𝑛𝐻
,
𝐸𝑆𝐿
,
= 25 𝑛𝐻
(5)
(6)
(7)
- 𝐶 is the sum of the output parasitic capacitance 𝐶 of each
of the devices with 700 V across drain and source:
𝐶
= 151 𝑝𝐹
𝐶 =8∙𝐶
≃ 1.2 𝑛𝐹
(8)
(9)
The magnitude of the overvoltage computed, using a 𝑇
of 85 ns from the spice simulation, is 279 V with an oscillation
frequency of 28.5 MHz, both close to the simulation results.
The overvoltage peak in the first oscillation, as can be seen
from the relation (1), depends heavily on the drain current of
the devices, the switching speed, and intrinsic parasitic
parameters of the power module.
Fig. 8. Comparison of the simulation and experimental results.
As can be seen from Table I, the most prominent ones are
those associated with the P and N terminal busbar, i.e. 𝐿 and
𝐿 , and the one from the DC link capacitor 𝐸𝑆𝐿 , .
In order to evaluate those two effects, double pulse tests
on the power module were carried out in the laboratories, the
results of which are shown in Fig. 7. Simulation and
experimental results are in good agreement, as can be seen
from Fig. 8.
V. CONCLUSIONS
In this paper, a methodology to evaluate the turn-off
overvoltage and the ringing is carried out. The parasitic
inductances are extracted by using the Ansys Q3D tool, and
the behavioral model of the SiC MOSFETs is used for
simulation purpose. The case study is a power module
realizing a three-phase traction inverter. The simulated results
obtained with LTSpice package are compared with the
experimental results- A peak voltage having an overvoltage of
279 V, and a ringing frequency of 28.5 MHz are the outcome
of the simulation, while a peak voltage of 281 V, and 28.1
MHz as a ringing frequency are the experimental results. The
close correlation of the results confirms the validity and
correctness of the proposed approach.
VI. ACKNOWLEDGMENT
The work has been partially supported by the projects:
“Research and Development in Electric Vehicle
Technologies” funded by the DIEEI, University of Catania;
“Advanced power-trains and systems for full electric
aircrafts” funded by the “Ministero dell'Istruzione
dell'Università e della Ricerca” under the call PRIN 2017;
“WInSiC4AP- Wide band-gap Innovative SiC for Advanced
Power”, funded by the European Union; DFM.AD001.098,
“Nuovi Dispositivi di Silicio oltre il CMOS Scaling”.
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