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William Stallings
Computer Organization
and Architecture
9th Edition
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Chapter 5
Internal Memory
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Semiconductor Main Memory
organization

All semiconductor memory cells share certain properties



Exhibits two stable states, used to represent binary 1 and 0
Capable of being written into (at least once)
Capable of being read to sense the state
Memory cell operation

Fig. 5.1 depicts the operation of memory cell,
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The cell has three functional terminals :

Select terminal a cell for a read or write

Control terminal indicate read or write
Third to provide read or write signal
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Memory Cell Operation
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DRAM and SRAM
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Table 5.1 list the major types of semiconductor memory

RAM (random-access memory) is the most common

In fact all semiconductor memories are random access

RAM is a read / write memory

Two forms of RAM are used in computers.
DRAM and SRAM
Semiconductor Memory Types
Table 5.1 Semiconductor Memory Types
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Dynamic RAM (DRAM)

RAM technology is divided into two technologies:


Dynamic RAM (DRAM)
Static RAM (SRAM)
DRAM

Made with cells that store data as charge on capacitors

Presence or absence of charge in a capacitor is interpreted
as a binary 1 or 0

Requires periodic charge refreshing to maintain data
storage

The term dynamic refers to tendency of the stored charge
to leak away, even with power continuously applied
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Dynamic
RAM
Structure
Figure 5.2a
Typical Memory Cell Structures
(not required)
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Static RAM
(SRAM)

Digital device that uses the
same logic elements used
in the processor

Binary values are stored
using traditional flip-flop
logic gate configurations

Will hold its data as long as
power is supplied to it
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Static
RAM
Structure
Figure 5.2b
Typical Memory Cell Structures
(not required)
SRAM versusDRAM

Both volatile
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
Power must be continuously supplied to the memory
to preserve the bit values
Dynamic cell




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Simpler to build, smaller
More dense (smaller cells = more cells per unit area)
Less expensive
Requires the supporting refresh circuitry
Tend to be favored for large memory requirements
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
SRAM
Compensate for the fixed cost of the refresh circuit
Used for main memory
Static
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
Faster
Used for cache memory (both on and off chip)
DRAM
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Read Only Memory (ROM)

Contains a permanent pattern of data that cannot be
changed or added to
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No power source is required to maintain the bit values in
memory
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Data or program is permanently in main memory and never
needs to be loaded from a secondary storage device

Data is actually wired into the chip as part of the fabrication
process
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Disadvantages of this:
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No room for error, if one bit is wrong the whole batch of ROMs
must be thrown out
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Data insertion step includes a relatively large fixed cost
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Programmable ROM (PROM)
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Less expensive alternative
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Nonvolatile and may be written into only once
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Writing process is performed electrically and may be
performed by supplier or customer at a time later than the
original chip fabrication
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Special equipment is required for the writing process
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Provides flexibility and convenience

Attractive for high volume production runs
Read-Mostly Memory
EPROM
EEPROM
Erasable programmable
read-only memory
Electrically erasable
programmable read-only
memory
Can be written into at any
time without erasing prior
contents
Erasure process can be
performed repeatedly
More expensive than
PROM but it has the
advantage of the multiple
update capability
Combines the advantage of
non-volatility with the
flexibility of being
updatable in place
More expensive than
EPROM
Flash
Memory
Intermediate between
EPROM and EEPROM in
both cost and functionality
Uses an electrical erasing
technology, does not
provide byte-level erasure
Microchip is organized so
that a section of memory
cells are erased in a single
action or “flash”
Typical 16 Mb DRAM (4M x 4)
Chip Packaging
Figure 5.5
256-KByte
Memory
Organization
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1MByte Module Organization
Interleaved Memory
Main Main Composed of a
collection of DRAM chips
Grouped together to form a
memory bank
Each bank is independently
able to service a memory read
or write request
K banks can service K requests
simultaneously, increasing
memory read or write rates by
a factor of K
If consecutive words of
memory are stored in different
banks, the transfer of a block of
memory is speeded up
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Error Correction

Hard Failure
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Permanent physical defect
Memory cell or cells affected cannot reliably store data but
become stuck at 0 or 1 or switch erratically between 0 and 1
Can be caused by:
 Harsh environmental abuse
 Manufacturing defects
Soft Error



Random, non-destructive event that alters the contents of one or
more memory cells
No permanent damage to memory
Can be caused by:
 Power supply problems
 Alpha particles
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
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Error Correction (continue)
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Both hard and soft errors are undesirable. Modern memory
systems include logic for detecting and correcting errors
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Fig 5.7 illustrates in general how the process is carried out
 A calculation, as function of f, is performed on the data to
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
produce a code ( say of length K bit
Both the data (length M )and the produced code are stored
 The actual size of the stored word is M + K bits
When a previously stored word is read out, the code is used
to detect and possibly correct errors

A new K code bit is generated from M data (read out), compared
with the fetched K code. The comparison yield one of 3 results
 No error detected.
 An error is detected, and it is possible to correct
 An error is detected, and it is not possible to correct
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Error Signal
Data Out
M
Corrector
M
Data In
K
M
Memory
f
K
f
Figure 5.7 Error-Correcting Code Function
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
K
Compare
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Hamming Code
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Hamming code is simple error-correcting code
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Fig 5.8 uses Venn diagram to illustrate the use of this code on
4-bit words (M = 4).
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With 3 intersecting circles, there are 7 compartments
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Assign the 4 data bits to the inner compartment (Fig 5.8a). The
remaining compartments are filled with parity bits (Fig 5.8b)
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Each parity bit is chosen so total # of 1s in its circle is even
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If an error changes one of the data bits (Fig 5.8c), it is easily
found. By checking the parity bits, differences are found in
circle A and B but not in B
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Only one of the seven compartments is in A and C but not B
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The error can therefore be corrected by changing that bit
To clarify the concept, we will develop a code that can detect
and correct single-bit in 8-bit word
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
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Hamming
Error
Correcting
Code
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Hamming Code:- developing a code to
detect and correct single-bit errors
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The code length is given by the following inequality:2k – 1 ≥ M + K ( K = code length, M= word length)
Syndrome word
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Refer to Fig. 5.7, The comparison logic receives as input two
K-bit values (one before write to memory, and one after read
from memory).
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A bit-by-bit comparison is done by taking the exclusive-OR of
the two inputs . The result is called the Syndrome word . Its value
(in decimal) determine the position where the error occurs
Example ( code length, K, for a word of 8 data bits, M = 8 )
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Use 2k – 1 ≥ M + K , take K = 3, then 23 – 1 < 8 + 3 (no), take
K=4, the n 24 – 1 > 8 + 4 (ok)
Table 5.2 (first 3 columns) lists the number of check (parity)
bits required for various data words
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Single-Error Correction
Data Bits
Check Bits
% Increase
Single-Error Correction/
Double-Error Detection
Check Bits
% Increase
8
4
50
5
62.5
16
5
31.25
6
37.5
32
6
18.75
7
21.875
64
7
10.94
8
12.5
128
8
6.25
9
7.03
256
9
3.52
10
3.91
Table 5.2
Increase in Word Length with Error Correction
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ Hamming Code:- Generation a 4-bit
syndrome for an 8-bit data
Important characteristics
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If the syndrome contains all 0s, no error has been detected
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If it contain one and only one bit set to 1, then an error has
occurred in one of the 4 check bits. No correction is needed
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If it contain more than one bit set to 1, the numerical value of
the syndrome indicates the position of the data bit in error.
This data bit is inverted for correction
To achieve these characteristics, the data and check bits are
arranged into 12-bit word as shown in Fig 5.9
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The bit positions are numbed from 1 to 12.
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Those bit positions whose position numbers are powers of 2 are
designated as check bits
the check bits are calculated (shown in class)
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
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Layout of Data Bits and Check Bits
Check Bit Calculation
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Hamming SEC-DED Code (not req)
Advanced DRAM Organization

One of the most critical system bottlenecks
when using high-performance processors is
the interface to main internal memory
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The traditional DRAM chip is constrained by
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SDRAM
DDR-DRAM
Its Internal architecture
Its Interface to the processor’s memory bus
Anumber of enhancements to the basic
DRAM architecture have been explored:
RDRAM
Table 5.3 provide performance comparison
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Table 5.3 Performance Comparison of Some DRAM Alternatives
+ Synchronous DRAM (SDRAM)
 One

of the most widely used forms of DRAM,
unlike traditional DRAM, which is asynchronous
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SDRAM Exchanges data with the processor synchronized to
an external clock signal and running at the full speed of the
processor/memory bus without imposing wait states
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With synchronous access the DRAM moves data in and out
under control of the system clock
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The processor or other master issues the instruction and address
information which is latched by the DRAM
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The DRAM then responds after a set number of clock cycles
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Meanwhile the master can safely do other tasks while
SDRAM employs a bust mode to eliminate the address set up
and row and column line precharge time after the first access
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+ SDRAM Read Timing
- Fig. 5.13 shows an example of SDRAM operation. Here the
burst length is 4 and latency is 2.The read command is initiated.
- The address determine the starting column for the bust
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Rambus DRAM (RDRAM)
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Developed by Rambus. Adopted by Intel for its Pentium and
Itanium processors
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Has become the main competitor to SDRAM
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Chips are vertical packages with all pins on one side
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Exchanges data with the processor over 28 wires no more than 12
centimeters long
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Bus can address up to 320 RDRAM chips and is rated at 1.6 GBps
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Special Bus delivers address and control information using an
asynchronous block-oriented protocol
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Gets a memory request over the high-speed bus
 Request contains the desired address, the type of operation, and
the number of bytes in the operation
Fig 5.14 illustrate the RDRAM layout. Consists of;
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Controller, # of RDRAM, connected via a common bus.
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RDRAM Structure
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Double Data Rate SDRAM
(DDR SDRAM)
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SDRAM can only send data once per bus clock cycle
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Double-data-rate SDRAM can send data twice per clock
cycle, once on the rising edge and once on the falling edge
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Widely used in desktop computers and servers
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Fig. 5.15 shows the basic timing for a DDR read
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Data transfer is synchronized to both rising and falling edge of
the clock
There have many generations of improvement to DDR
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DDR (clock rate 200 to 600 MHz), DDR2 ( rate 400 to 1066 MHz),
DDR3 ( rate 800 to 1600 MHz), DDR4, DDR5 (released 2021)
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Voltage :- DDR (2.5V), DDR2(1.8V), DDR3 (1.5V), DDR4(1.2V)
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DDR SDRAM
Read
Timing
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Cache DRAM (CDRAM)
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Developed by Mitsubishi
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Integrates a small SRAM cache onto a generic DRAM chip
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SRAM on the CDRAM can be used in two ways:
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It can be used as a true cache consisting of a number of 64-bit
lines
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Cache mode of the CDRAM is effective for ordinary random
access to memory
Can also be used as a buffer to support the serial access of a
block of data
Summary
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Internal
Memory
Chapter 5
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
Semiconductor main memory
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Hamming code
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Advanced DRAM organization
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Organization
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DRAM and SRAM
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Types of ROM
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Synchronous DRAM
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Chip logic
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Rambus DRAM
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Chip packaging
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DDR SDRAM
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Module organization
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Cache DRAM
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Interleaved memory
Error correction
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Hard failure
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Soft error