Microprocessors@BITS
Microprocessors@BITS
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Arithmetic
Instructions
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AAA
Clock
AAD
7:46 PM
AAM
AAS
Jun 27, 51155 (Mon)
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
Copyright
The Instruction Set Dictionary is subject to copyright protection and may be used
only for private study by persons who are enrolled in this course. Any other use of
these materials must be with the express, written permission of any of the course
instructors from Goa campus
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/[3/9/2019 8:39:50 PM]
Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
https://sites.google.com/site/microprocessorsbits/[3/9/2019 8:39:50 PM]
Microprocessors@BITS
Program
Execution
Transfer
Instructions
CALL
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
…
https://sites.google.com/site/microprocessorsbits/[3/9/2019 8:39:50 PM]
Microprocessors@BITS
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Arithmetic Instructions - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
AAD
AAM
Arithmetic Instructions
This page gives info about the various arithmetic instructions available in the Intel
x86 ISA.
AAS
Subpage Listing
ADC
AAA
ADD
AAD
CMP
AAM
DAA
AAS
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
ADC
ADD
CMP
DAA
DAS
DEC
DIV
SBB
IDIV
SUB
IMUL
XADD
INC
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
Search this site
MUL
NEG
SBB
SUB
XADD
Subpages (19): AAA AAD AAM AAS ADC ADD CMP DAA DAS DEC DIV
IDIV IMUL INC MUL NEG SBB SUB XADD
Comments
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions[3/9/2019 8:40:20 PM]
Arithmetic Instructions - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions[3/9/2019 8:40:20 PM]
Arithmetic Instructions - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions[3/9/2019 8:40:20 PM]
Arithmetic Instructions - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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AAA - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
AAA
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Search this site
ASCII adjust after addition. Addition of two one digit ASCII
coded number will not be ASCII. To convert the result to
ASCII, we use AAA after ADD instruction. The result in AX,
when added to 3030H, gives us ASCII coded sum.
USAGE: AAA
FLAGS: AF CF (OF,PF,SF,ZF undefined)
CLOCKS AND SIZE:
Operands
none
Clock Cycles
Size in bytes
8086
80286
80386
80486
8
3
4
3
EXAMPLE:
MOV AL,31H;mov ASCII 1 in AL
ADD AL,39H;The ASCII result should be 10 but we get 6AH in AL
AAA;Adjusts the result and AX now contains 0100H
ADD AX,3030H;AX now contains ASCII result 10
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aaa[3/9/2019 8:40:48 PM]
1
AAA - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aaa[3/9/2019 8:40:48 PM]
AAA - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aaa[3/9/2019 8:40:48 PM]
AAA - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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AAD - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
AAD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
Search this site
AAD stands for ASCII Adjust before Division (or BCD-to-Binary Convert before
Division). AAD converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL. This adjustment must be made before dividing the two unpacked BCD digits
in AX by an unpacked BCD byte. After the division, AL will contain the unpacked BCD
quotient and AH will contain the unpacked BCD remainder.
Usage AAD
Flags PF, SF, ZF
Clocks and Size
Operands
Clocks
none
Size in Bytes
8086
286
386
486
60
14
19
14
2
NEG
SBB
SUB
Example
Divide 67 by 9
XADD
Bit Manipulation
Instructions
MOV AX, 0607H
MOV CH, 09H
BSWAP
Logical AND
AAD ;AX = 0043 = 43H = 67
Logical OR
DIV CH ;Divide AX by unpacked BCD in CH, result: AL = 07 unpacked BCD, AH
Logical XOR
= 04 unpacked BCD
Logical NOT
RCL
RCR
ROL
Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aad[3/9/2019 8:41:24 PM]
AAD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aad[3/9/2019 8:41:24 PM]
AAD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aad[3/9/2019 8:41:24 PM]
AAD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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AAM - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
AAM
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
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The AAM mnemonic stands for
ASCII adjust for Multiplication or BCD Adjust after
Multiply. This instruction is used in the process of multiplying two ASCII digits. The
process begins with masking the upper 4 bits of each digit, leaving an unpacked BCD in
each byte. These unpacked BCD digits are then multiplied and the AAM instruction is
subsequently used to adjust the product to two unpacked BCD digits in AX.
AAM works only after the multiplication of two unpacked BCD bytes, and it works only on
an operand in AL.
Usage AAM
Flags PF,SF,ZF
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
83
16
17
15
XADD
Bit Manipulation
Instructions
Example
Multiply 9 and 5
BSWAP
Logical AND
MOV AL, 00000101
Logical NOT
MOV BH, 00001001
Logical OR
MUL BH Logical XOR
RCL
AAM ;AX = 00000100 00000101 = 0405H = 45 in unpacked BCD
;If ASCII values are required an OR operation with 3030H can follow this step.
RCR
;Result stored in AX
;AX = 00000000 00101101 = 2DH = 45 in decimals
ROL
ROR
SAR
Comments
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aam[3/9/2019 8:41:50 PM]
2
AAM - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aam[3/9/2019 8:41:50 PM]
AAM - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aam[3/9/2019 8:41:50 PM]
AAM - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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AAS - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
AAS
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
Search this site
ASCII ADJUST FOR SUBTRACTION:
DESCRIPTION:Corrects result of a previous unpacked ASCII
subtraction in AX.
USAGE: AAS
FLAGS:AF CF (OF,PF,SF,ZF undefined)
CLOCKS AND SIZES:
Operands
none
Clock Cycles
Size in bytes
8086
80286
80386
80486
8
3
4
3
EXAMPLE:
MOV AX,39H
; Load ASCII 9
AAS
; Adjust difference
SUB AL,31H
ADD AX,3030H
; Subtract ASCII 1
; Answer in ASCII
BSWAP
Logical AND
Logical NOT
Comments
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aas[3/9/2019 8:42:19 PM]
1
AAS - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aas[3/9/2019 8:42:19 PM]
AAS - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aas[3/9/2019 8:42:19 PM]
AAS - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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ADC - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
ADC
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
Search this site
It carries out the addition of source and destination, storing
the result in the destination.
If CF is set, a 1 is added to the destination.
USAGE: ADC dest,src
dest-mem/reg
src
-mem/reg/imm
Note: The only types of addition not allowed are memory to memory and segment
register.
IDIV
IMUL
INC
FLAGS: AF CF OF PF SF ZF
MUL
NEG
SBB
SUB
XADD
CLOCKS AND SIZE:
Operands
Clock Cycles
Size in bytes
8086
80286
80386
80486
3
2
2
1
2
mem,reg
16+EA
7
6
3
2-4
BSWAP
reg,mem
9+EA
7
7
2
2-4
Logical AND
mem,immed
17+EA
7
7
3
3-4
reg,immed
4
3
2
1
3-6
accum,immed
4
3
2
1
2-3
Bit Manipulation
Instructions
Logical NOT
Logical OR
reg,reg
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
EXAMPLES:
ADC AL,BL; AL=AL+BL+carry
ADC CL,44h;CL=CL+44h+carry
ADC [BX],AL;AL adds byte contents of the data segment memory
location addressed by BX
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/adc[3/9/2019 8:42:48 PM]
ADC - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
with the sum stored in the same memory location.
Carry is also added to destination if CF is set.
ADC BX,[SI+2];The word contents of the data segment memory
location addressed by SI+2
add to BX with the sum stored in BX.Carry is also
added to destination if CF is set.
ADC BX,TEMP[DI];The word contents of the data segment memory
location addressed by TEMP+DI
add to BX with the sum stored in BX. Carry is also
added to destination if CF is set.
MOVZX
SAHF
Comments
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/adc[3/9/2019 8:42:48 PM]
ADC - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/adc[3/9/2019 8:42:48 PM]
ADC - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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ADD - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
ADD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
Search this site
It carries out the addition of source and destination, storing
the result in the destination.
USAGE: ADD dest,src
dest-mem/reg
src
-mem/reg/imm
Note: The only types of addition not allowed are memory to memory and segment
register.
DIV
IDIV
IMUL
FLAGS: AF CF OF PF SF ZF
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
CLOCKS AND SIZE:
Operands
Clock Cycles
8086
80286
80386
80486
3
2
2
1
2
16+EA
7
6
3
2-4
reg,reg
mem,reg
reg,mem
Size in bytes
9+EA
7
7
2
2-4
17+EA
7
7
3
3-4
reg,immed
4
3
2
1
3-6
accum,immed
4
3
2
1
2-3
mem,immed
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
EXAMPLES:
ADD AL,BL; AL=AL+BL
ADD CL,44h;CL=CL+44h
ADD [BX],AL;AL adds byte contents of the data segment memory
location addressed by BX
with the sum stored in the same memory location
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/add[3/9/2019 8:43:18 PM]
ADD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
ADD BX,[SI+2];The word contents of the data segment memory
location addressed by SI+2
add to BX with the sum stored in BX
ADD BX,TEMP[DI];The word contents of the data segment memory
location addressed by TEMP+DI
add to BX with the sum stored in BX
ADD BYTEPTR[DI],3;A 3 adds to the byte contents of the data
segment memory location addressed
by DI with the sum stored in the same location
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
Comments
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/add[3/9/2019 8:43:18 PM]
ADD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/add[3/9/2019 8:43:18 PM]
ADD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CMP - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
CMP
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
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COMPARE
DESCRIPTION:Subtracts source from destination and updates the fl
not save result. Flags can subsequently be checked for conditio
USAGE: CMP dest,src
dest-mem/reg/immed
src-mem/reg/immed
FLAGS:AF CF OF PF SF ZF
CLOCKS AND SIZES:
Operands
Clock Cycles
reg,reg
Size in bytes
8086
80286
80386
80486
3
2
2
1
mem,reg
9+EA
7
5
2 2-4
reg,mem
9+EA
6
6
2 2-4
mem,immed
10+EA
6
5
2 3-6
SBB
reg,immed
4
3
2
1 3-4
SUB
accum,immed
4
3
2
1 2-3
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
EXAMPLES:
CMP CL,BL : CL-BL and flags updated
CMP AX,2000H: AX-2000H and flags updated
CMP [DI],CH: CH is subtracted from the byte contents of the
data segment addressed by DI and flags updated.
CMP AH,[1234H] : The byte contents of data memory location
1234h is subtracted from AH and flags updated.
RCR
ROL
ROR
SAR
Comments
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/cmp[3/9/2019 8:43:56 PM]
2
CMP - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/cmp[3/9/2019 8:43:56 PM]
CMP - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/cmp[3/9/2019 8:43:56 PM]
CMP - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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DAA - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
DAA
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Decimal adjust after addition. This instruction follows ADD or
ADC to adjust the result into BCD result.
This instruction works only with the AL registers and so must
occur 8 bits at a time.
USAGE: DAA
FLAGS: AF CF (OF,PF,SF,ZF undefined)
EXAMPLE
MOV DX,1234H ; load 1234H BCD
MOV BX,3099H ;load 3099H BCD
MOV AL,BL ;only AL register can be used for DAA
ADD AL,DL ;
DAA ;result is BCD adjusted
MOV CL,AL
MOV AL,BH
;mov result into CL
;
ADC AL,DH ;
DAA ;result is BCD adjusted
mov CH,AL ;now CX contains the sum in BCD format as 4333
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
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Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/daa[3/9/2019 8:44:24 PM]
DAA - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/daa[3/9/2019 8:44:24 PM]
DAA - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/daa[3/9/2019 8:44:24 PM]
DAA - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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DAS - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
DAS
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DECIMAL ADJUST AFTER SUBTRACTION
DESCRIPTION:This instruction follows the SUB or SBB
instruction to adjust the difference to a BCD result.DAS works
only with AL register, hence subtraction must occur 8 bits at
a time.
DAS
DEC
USAGE:DAS
DIV
FLAGS: AF CF (OF,PF,SF,ZF undefined)
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
EXAMPLE:
MOV DX, 1234H
; load 1234 BCD
MOV BX, 3099H
; load 3099 BCD
MOV AL,BL
SUB AL,DL
; subtract DL from BL
DAS
MOV CL,AL
MOV AL,BH
SBB AL,DH
DAS
MOV CH,AL
; decimal adjust
; answer in CL
; subtract CH with borrow
; decimal adjust
; answer in CH
Logical XOR
RCL
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Comments
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/das[3/9/2019 8:44:53 PM]
DAS - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/das[3/9/2019 8:44:53 PM]
DAS - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/das[3/9/2019 8:44:53 PM]
DAS - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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DEC - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
DEC
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
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DESCRIPTION: Decrement subtracts 1 from a register or a memory
location. DEC instruction subtracts 1 from any register or
memory location, except segment register.
USAGE: DEC dest
dest-mem/reg
FLAGS: AF OF PF SF ZF
CLOCKS AND SIZES:
EXAMPLES:
DEC BL; BL=BL-1
DEC BYTEPTR[BX];Subtracts 1 from the byte contents of data
segment memory location addressed by BX
Comments
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/dec[3/9/2019 8:45:22 PM]
DEC - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/dec[3/9/2019 8:45:22 PM]
DEC - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/dec[3/9/2019 8:45:22 PM]
DEC - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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DIV - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
DIV
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
The DIV instruction is used to divide an
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unsigned word (doubleword) by a byte (word).
For word-byte division, the word must be in the AX register; the divisor can be in a reg or a
mem location. After the division, AL contains the quotient and AH contains the remainder.
Division by zero or a quotient larger than can fit into AL (FFH) raises a Type 0 Interrupt.
For a doubleword-word division, the most significant word must be in the DX register and the
least significant word in the AX register. Post-division, AX contains the quotient and DX the
remainder.
Division of a byte by a byte is done by putting the dividend byte in AL and filling AH with
zeros. A similar analogy can be applied to word-word division.
If the divisor does not divide the dividend exactly, the quotient is
truncated, not round
Usage DIV Source
Flags None
Clocks and Size
Operands
Clocks
8086
Size in Bytes
286
386
486
Logical NOT
reg8
80-90
14
14
16
2
Logical OR
reg16
144-162
22
22
24
2
Logical XOR
reg32
-
38
40
2
mem8
86-96 (+EA)
17
17
16 2 - 4
mem16
150-168 (+EA)
25
25
24 2 - 4
mem32
-
41
40 2 - 4
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
-
-
Example
DIV BL ;Divide a word in AX with a byte in BL. Quotient in AL, remainder in AH
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/div[3/9/2019 8:45:50 PM]
DIV - Microprocessors@BITS
SHRD/SHLD
Data Transfer
Comments
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/div[3/9/2019 8:45:50 PM]
DIV - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/div[3/9/2019 8:45:50 PM]
DIV - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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IDIV - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
IDIV
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
This instruction is used to
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divide a signed word (doubleword) by a signed byte (word).
The locations of quotients, remainders, dividends and divisors are the same as in the DIV
instruction; the sign of the remainder is the same as that of the dividend.
Division by zero and quotient values > 128 or <-127 result in a Type 0 Interrupt. (The range
for 186+ is -128 to +127).
For byte-byte (word-word) divisions, AH (DX) must be sign extended with the same sign as
the AL (AX) byte (word).
Usage IDIV Source
Flags Undefined
Clocks and Size
Operands
Clocks
8086
286
Size in Bytes
386
486
reg8
101-112
17
19
19
2
reg16
165-184
25
27
27
2
reg32
-
43
43
2
mem8
107-118 (+EA)
20
22
20 2 - 4
mem16
171-190 (+EA)
38
30
28 2 - 4
mem32
-
46
44 2 - 4
-
-
Example
IDIV BP ;Signed doubleword in DX and AX divided by signed word in BP
Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/idiv[3/9/2019 8:46:16 PM]
IDIV - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/idiv[3/9/2019 8:46:16 PM]
IDIV - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/idiv[3/9/2019 8:46:16 PM]
IDIV - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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IMUL - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
IMUL
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
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This insruction multilplies a signed byte (word) from a source with a signed byte (word) in
AL (AX).
All details of IMUL are exactly the same as that of MUL, except that if all bits of the
destination are not used by the result, the result is sign extended. The OF and the CF are
both set to 1 if the upper byte (word) of a 16-bit (32-bit) prodct contains part of the product.
Usage IMUL Source
Flags OF, CF
Clocks and Size
Operands
Clocks
8086
286
Size in Bytes
386
486
NEG
reg8
80-98
13 9 - 14
13-18
2
SBB
reg16
128-154
21 9 - 22
13-26
2
reg32
-
9-38
12-42
2
mem8
86-104
16 12 - 17
13-18
2-4
mem16
134-160
24 12 - 25
13-26
2-4
mem32
-
12 - 41
13-42
2-4
reg16,reg16
-
-
9 - 22
13-26
3-5
BSWAP
reg32,reg32
-
-
9-38
13-42
3-5
Logical AND
reg16,mem16
-
-
12 - 25
13-26
3-5
reg16,immed
-
21 9 - 22
13-26
reg32,immed
-
21 9-38
13-42
3-6
reg16,reg16,immed
-
13-26
3-6
reg32,reg32,immed
-
21 9-38
13-42
3-6
SUB
XADD
Bit Manipulation
Instructions
Logical NOT
Logical OR
Logical XOR
-
2 9 - 22
3
RCL
reg16,mem16,immed -
24 12 - 25
13-26
3-6
RCR
reg32,mem32,immed -
24 12-41
13-42
3-6
ROL
ROR
SAR
SHL/SAL
Example
IMUL AX ;AX times AX, result in DX and AX
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/imul[3/9/2019 8:46:45 PM]
IMUL - Microprocessors@BITS
SHRD/SHLD
Data Transfer
Comments
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/imul[3/9/2019 8:46:45 PM]
IMUL - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/imul[3/9/2019 8:46:45 PM]
IMUL - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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INC - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
INC
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
Search this site
Increment addition adds 1 to a register or a memory location.
INC instruction adds 1 to any register or memory location,
except segment register.
USAGE: INC dest
dest-mem/reg
FLAGS: AF OF PF SF ZF
DIV
IDIV
IMUL
CLOCKS AND SIZE:
INC
MUL
Operands
8086
80286
80386
80486
NEG
reg8
3
2
2
1
2
SBB
reg16
3
2
2
1
1
reg32
3
2
2
1
1
mem
15+EA
7
6
3
2-4
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Clock Cycles
Size in bytes
EXAMPLES:
INC BL; BL=BL+1
INC BYTEPTR[BX];Adds 1 to the byte contents of data segment
memory location addressed by BX
Logical OR
Logical XOR
RCL
Comments
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/inc[3/9/2019 8:47:14 PM]
INC - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/inc[3/9/2019 8:47:14 PM]
INC - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/inc[3/9/2019 8:47:14 PM]
INC - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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MUL - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
MUL
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
Search this site
This instruction multiplies an unsigned byte (word) from some source with an unsigned
byte (word) in the AL (AX) register.
The source can be a register or a memory location addressed by any of the 24 standard
modes of addressing.
When doing byte-multiplication, the result is stored in a 16-bit location AX since the result
can be as large as 16 bits. Word-multiplication results in the most significant word being
placed in the DX register and the least significant word placed in the AX register.
If the most significant byte (word) of a 16-bit (32-bit) result is zero, both CF and OF will be
zero.
Usage MUL Source
Flags OF,CF
Clocks and Size
Operands
Clocks
8086
286
Size in Bytes
386
486
reg8
70-77
13 9 - 14
13-18
2
BSWAP
reg16
118-133
21 9 - 14
13-26
2
Logical AND
reg32
-
mem8
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
-
9-38
13-42
2-4
76-83 (+ EA)
16 12 - 17
13-18
2-4
mem16
124-139 (+EA)
24 13-26
12 - 25
2-4
mem32
-
13-42
2-4
-
12 - 21
Example
MUL CX ; AX times CX, result high word in DX and low word in AX
Comments
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/mul[3/9/2019 8:47:43 PM]
MUL - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/mul[3/9/2019 8:47:43 PM]
MUL - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/mul[3/9/2019 8:47:43 PM]
MUL - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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NEG - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
NEG
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
TWO COMPLEMENTS' NEGATION
DESCRIPTION:Subtracts the destination from 0 and saves the 2s co
"dest" back into "dest".
USAGE:NEG
FLAGS:AF CF OF PF SF ZF
CLOCKS AND SIZES:
Operands
reg
INC
mem
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
dest
dest-mem/reg
IMUL
MUL
Search this site
Clock Cycles
16+EA
Size in bytes
8086
80286
80386
80486
3
2
2
1
7
6
3 2-4
EXAMPLES:
NEG AX
: AX is two's complemented
NEG BYTE PTR[BX] : The byte contents of the data segment
memory location addressed by BX are two's complemented.
BSWAP
Logical AND
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/neg[3/9/2019 8:48:09 PM]
2
NEG - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/neg[3/9/2019 8:48:09 PM]
NEG - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/neg[3/9/2019 8:48:09 PM]
NEG - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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SBB - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
SBB
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
Search this site
SUBTRACT WITH BORROW/CARRY
DESCRIPTION:Subtracts the source from the destination, and subtr
the Carry Flag is set.Results are returned in "dest".
USAGE: SBB
dest,src
dest-mem/reg/immed
src-mem/reg/immed
FLAGS:AF CF OF PF SF ZF
CLOCKS AND SIZE:
Operands
Clock Cycles
reg,reg
Size in bytes
8086
80286
80386
80486
3
2
2
1
mem
16+EA
7
6
3 2-4
reg,mem
9+EA
7
7
2 2-4
NEG
mem,immed
17+EA
7
7
3 3-6
SBB
SUB
reg,immed
4
3
2
1 3-4
accum,immed
4
3
2
1 2-3
MUL
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
EXAMPLES:
SBB AX,BX : AX=AX-BX-carry
SBB CL,2
: CL=CL-2-carry
SBB [DI],AL: Both AL and carry subtract from the data segment
memory location addressed by DI
SBB BYTE PTR[DI],3: Both 3 and carry are subtracted from the
memory byte data addressed by DI.
Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/sbb[3/9/2019 8:48:35 PM]
2
SBB - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/sbb[3/9/2019 8:48:35 PM]
SBB - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/sbb[3/9/2019 8:48:35 PM]
SBB - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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SUB - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
SUB
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
Search this site
This instruction subtracts the source from the destination and
stores the result back into the destination
USAGE: SUB dest,src
dest-mem/reg
src mem/reg/imm
Note: The only types of subtraction not allowed are memory to memory and
segment register.
FLAGS:AF CF OF PF SF ZF
CLOCKS AND SIZE:
Operands
Clock Cycles
Size in bytes
8086
80286
80386
80486
3
2
2
1
IMUL
reg,reg
INC
mem
16+EA
7
6
3 2-4
reg,mem
9+EA
7
7
2 2-4
mem,immed
17+EA
7
7
3 3-6
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
reg,immed
4
3
2
1 3-4
accum,immed
4
3
2
1 2-3
EXAMPLES:
SUB AL,BL; AL=AL-BL
SUB CL,44h;CL=CL-44h
SUB [BX],AL;Subtracts AL from byte contents of the data
segment memory location addressed by BX
with the differnce stored in the same memory
location
SUB BX,[SI+2];The word contents of the data segment memory
location addressed by SI+2
in BX
are subtracted from BX with the difference stored
ADD BX,TEMP[DI];The word contents of the data segment memory
location addressed by TEMP+DI
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/sub[3/9/2019 8:49:05 PM]
2
SUB - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
in BX
are subtracted from BX with the difference stored
Comments
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/sub[3/9/2019 8:49:05 PM]
SUB - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/sub[3/9/2019 8:49:05 PM]
SUB - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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XADD - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic Instructions ‎ > ‎
Arithmetic
Instructions
XADD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
Search this site
EXCHANGE AND ADD (486+ )
DESCRIPTION: The XADD instruction adds the source to the
destination and stores the sum in the destination, as with any
addition. The difference is that after the addition takes
place, the original value of the destination is copied into
source operand.
USAGE: XADD dest, src
FLAGS: AF CF OF PF SF ZF
CLOCKS AND SIZES:
Operands
Clock Cycles
8086
80286
Size in bytes
80386
80486
SBB
reg,reg
3
2
SUB
mem,reg
4
2-4
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
EXAMPLE:
If BL=12H and DL=02H,
XADD BL,DL
Now BL= 14H and DL= 12H
RCL
RCR
ROL
ROR
Comments
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/xadd[3/9/2019 8:49:33 PM]
XADD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/xadd[3/9/2019 8:49:33 PM]
XADD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/xadd[3/9/2019 8:49:33 PM]
XADD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Bit Manipulation Instructions - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
AAD
AAM
Bit Manipulation Instructions
This page gives information about various logical instructions which manipulate data
at binary bit level.
AAS
Subpage Listing
ADC
BSWAP
ADD
Logical AND
CMP
Logical NOT
DAA
Logical OR
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
Search this site
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SBB
SHR
SUB
SHRD/SHLD
XADD
Bit Manipulation
Instructions
BSWAP
Subpages (13): BSWAP Logical AND Logical NOT Logical OR Logical XOR
RCL RCR ROL ROR SAR SHL/SAL SHR SHRD/SHLD
Logical AND
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions[3/9/2019 8:50:02 PM]
Bit Manipulation Instructions - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions[3/9/2019 8:50:02 PM]
Bit Manipulation Instructions - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions[3/9/2019 8:50:02 PM]
Bit Manipulation Instructions - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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BSWAP - Microprocessors@BITS
Microprocessors@BITS
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
BSWAP
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Search this site
BYTE SWAP(486+)
DESCRIPTION:
Changes the byte order of a 32 bit register from big endian to
little endian or vice versa. Result left in destination regist
is undefined if the operand is a 16 bit register.
USAGE: BSWAP reg32
reg32- 32 bit register
FLAGS:NONE
CLOCKS AND SIZES:
Operands
Clock Cycles
Size in bytes
8086
reg32
-
80286
-
80386
80486
-
EXAMPLES:
If EAX is 12345678H
BSWAP EAX results in EAX being 78563412H.
Comments
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/bswap[3/9/2019 8:50:30 PM]
1
2
BSWAP - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/bswap[3/9/2019 8:50:30 PM]
BSWAP - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/bswap[3/9/2019 8:50:30 PM]
BSWAP - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Logical AND - Microprocessors@BITS
Microprocessors@BITS
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
Logical AND
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
Search this site
DESCRIPTION:
Performs a logical AND of the two operands replacing the destina
with the result.
USAGE: AND dest,src
dest-mem/reg
src-imm/reg/mem
DAS
Note: AND instruction uses any addressing mode except memory to memory and
DEC
segment register addressing.
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
FLAGS: CF OF PF SF ZF (AF undefined)
CLOCKS AND SIZE:
Operands
Clock Cycles
reg,reg
Size in bytes
8086
80286
80386
80486
3
2
2
1 2
mem,reg
16+EA
7
7
3 2-4
reg,mem
9+EA
7
6
1 2-4
mem,immed
17+EA
7
7
3 3-6
reg,immed
4
3
2
1 3-4
accum,immed
4
3
2
1 2-3
EXAMPLE:
AND AX,BX; AX = AX and BX
AND DI,3333H; DI=DI and 3333H
AND AX,[DI]; The word contents of the memory location
addressed by DI are ANDed with AX
AND ARRAY[SI],AL; The byte contents of memory location
addressed by ARRAY plus SI are ANDed with AL
AND [EAX],CL; CL is ANDed with the byte contents of the memory
location addressed by EAX
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-and[3/9/2019 8:50:56 PM]
Logical AND - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
Comments
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-and[3/9/2019 8:50:56 PM]
Logical AND - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-and[3/9/2019 8:50:56 PM]
Logical AND - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Logical NOT - Microprocessors@BITS
Microprocessors@BITS
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
Logical NOT
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
Search this site
DESCRIPTION: Inverts the bits of the operand by taking it's
one's complement.
USAGE: NOT dest
dest-mem/reg
FLAGS: none
CLOCKS AND SIZE:
Operands
Clock Cycles
reg
mem
16+EA
Size in bytes
8086
80286
80386
80486
3
2
2
1
7
6
3 2-4
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
EXAMPLE:
NOT AX
;AX is one's complemented
NOT TEMP ;Contents of memory location TEMP is one's
complemented
NOT BYTE PTR[Var];Byte contents of memory location addressed
by variable are one's complemented
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
Comments
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-not[3/9/2019 8:51:24 PM]
2
Logical NOT - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-not[3/9/2019 8:51:24 PM]
Logical NOT - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-not[3/9/2019 8:51:24 PM]
Logical NOT - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Logical OR - Microprocessors@BITS
Microprocessors@BITS
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
Logical OR
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
DESCRIPTION: Performs a logical OR
of the two operands replacing the destination
with the result. Any bit set in either operand will be set in
the destination.
USAGE: OR dest,src
dest-mem/reg
src-imm/reg/mem
Note: OR instruction uses any addressing mode except memory to memory and
segment register addressing.
FLAGS: CF OF PF SF ZF (AF undefined)
CLOCKS AND SIZE:
Operands
Clock Cycles
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
Search this site
Size in bytes
8086
80286
80386
3
2
2
1 2
reg,reg
80486
mem,reg
16+EA
7
7
3 2-4
reg,mem
9+EA
7
6
2 2-4
mem8,immed8
17+EA
7
7
3 3-6
mem16,immed16
25+EA
7
7
3 3-6
reg,immed
4
3
2
1 3-4
accum,immed
4
3
2
1 2-3
EXAMPLE:
OR AX,BX; AX=AX or BX
OR DI,3333H; DI=DI or 3333H
OR AX,[DI]; The word contents of the memory location addressed
by DI are ORed with AX
OR ARRAY[SI],AL; The byte contents of memory location
addressed by ARRAY plus SI are ORed with AL
OR [EAX],CL; CL is ORed with the byte contents of the memory
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-or[3/9/2019 8:51:53 PM]
Logical OR - Microprocessors@BITS
SHRD/SHLD
location addressed by EAX
Data Transfer
CMPXCHG
LAHF
Comments
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-or[3/9/2019 8:51:53 PM]
Logical OR - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-or[3/9/2019 8:51:53 PM]
Logical OR - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Logical XOR - Microprocessors@BITS
Microprocessors@BITS
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
Logical XOR
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
DESCRIPTION: Performs bitwise exclusive-OR
of the two operands replacing the destination
with the result.
USAGE: XOR dest,src
dest-mem/reg
src-imm/reg/mem
Note: XOR instruction uses any addressing mode except memory to memory and
segment register addressing.
FLAGS: CF OF PF SF ZF (AF undefined)
CLOCKS AND SIZE:
Operands
Clock Cycles
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Search this site
reg,reg
Size in bytes
8086
80286
80386
80486
3
2
2
1 2
mem,reg
16+EA
7
6
3 2-4
reg,mem
9+EA
7
6
2 2-4
mem,immed
17+EA
7
7
3 3-6
reg,immed
4
3
2
1 3-4
accum,immed
4
3
2
1 2-3
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
EXAMPLE:
XOR AX,BX; AX=AX xor BX
XOR DI,3333H; DI=DI xor 3333H
XOR AX,[DI]; The word contents of the memory location
addressed by DI are Exclusive-ORed with AX
XOR ARRAY[SI],AL; The byte contents of memory location
addressed by ARRAY plus SI are Exclusive-ORed
with AL
XOR [EAX],CL; CL is Exclusive-ORed with the byte contents of
the memory location addressed by EAX
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-xor[3/9/2019 8:52:23 PM]
Logical XOR - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
Comments
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-xor[3/9/2019 8:52:23 PM]
Logical XOR - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-xor[3/9/2019 8:52:23 PM]
Logical XOR - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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RCL - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
RCL
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
ROTATE THROUGH CARRY LEFT
DESCRIPTION:
.-. .---------------.
.--|C|<----|7 <---------- 0|<-.
| '-' '---------------' |
'-----------------------------'
Rotates the bits in the destination to the left "count" times wi
all data pushed out the left side reentering on the right. The
Carry Flag holds the last bit rotated out.
USAGE:RCL
dest,count
dest-mem/reg
FLAGS:CF OF
CLOCKS AND SIZE:
Operands
Clock Cycles
reg,1
Size in bytes
8086
80286
80386
80486
2
2
9
3
7
10
mem,1
15+EA
reg,CL
8+4n
5+n
9 8 - 30
mem,CL
20+EA+4n
8+n
10 9 - 31
BSWAP
reg,immed8
-
5+n
9 8 - 30
Logical AND
mem,immed8
-
8+n
10 9 - 31
Bit Manipulation
Instructions
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
2
4 2-4
2
2-4
3
3-5
EXAMPLES:
RCL,BX,6 : BX rotates left through carry 6 places
RCL AH,CL : AH rotates left through carry by the number
specified in CL
RCL BYTE PTR[BX],10 :Byte contents of memory location
addressed by BX is rotated left through carry by 10 places
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rcl[3/9/2019 8:52:53 PM]
RCL - Microprocessors@BITS
SHRD/SHLD
Data Transfer
Comments
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rcl[3/9/2019 8:52:53 PM]
RCL - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rcl[3/9/2019 8:52:53 PM]
RCL - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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RCR - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
RCR
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
ROTATE THROUGH CARRY RIGHT
DESCRIPTION:
.---------------. .-.
.->|7 ----------> 0|---->|C|--.
| '---------------' '-' |
'-----------------------------'
Rotates the bits in the destination to the right "count" times w
all data pushed out the right side reentering on the left. The
Carry Flag holds the last bit rotated out.
USAGE: RCR
dest,count
dest-mem/reg
FLAGS: CF OF
CLOCKS AND SIZE:
Operands
Clock Cycles
reg,1
Size in bytes
8086
80286
80386
80486
2
2
9
3
7
10
mem,1
15+EA
reg,CL
8+4n
5+n
9 8 - 30
BSWAP
mem,CL
20+EA+4n
8+n
10 9 - 31
Logical AND
reg,immed8
-
5+n
9 8 - 30
mem,immed8
-
8+n
10 9 - 31
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
2
4 2-4
2
2-4
3
3-5
EXAMPLES:
RCR,BX,6 : BX rotates right through carry 6 places
RCR AH,CL : AH rotates right through carry by the number
specified in CL
RCR BYTE PTR[BX],10 :Byte contents of memory location
addressed by BX is rotated right through carry by 10 places
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rcr[3/9/2019 8:53:18 PM]
RCR - Microprocessors@BITS
SHRD/SHLD
Data Transfer
Comments
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rcr[3/9/2019 8:53:18 PM]
RCR - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rcr[3/9/2019 8:53:18 PM]
RCR - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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ROL - Microprocessors@BITS
Microprocessors@BITS
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Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
ROL
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
ROTATE LEFT
DESCRIPTION:
.-. .---------------.
|C|<-.--|7 <---------- 0|<-.
'-' | '---------------' |
'---------------------'
Rotates the bits in the destination to the left "count" times wi
all data pushed out the left side reentering on the right. The
Carry Flag will contain the value of the last bit rotated out.
USAGE:ROL
dest,count
dest-mem/reg
FLAGS:CF OF
CLOCKS AND SIZE:
Operands
Clock Cycles
reg,1
Size in bytes
8086
80286
80386
80486
2
2
3
3
7
7
4 2-4
mem,1
15+EA
reg,CL
8+4n
5+n
3
3
mem,CL
20+EA+4n
8+n
7
4 2-4
reg,immed8
-
5+n
3
2
mem,immed8
-
8+n
7
4 3-5
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
EXAMPLES:
ROL SI,10 : SI is rotated left by 10 places
ROL WORD PTR[BX],2 : The word contents of the data segment
addressed by BX is rotated left by 2 places
SAR
SHL/SAL
Comments
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rol[3/9/2019 8:53:49 PM]
2
2
3
ROL - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rol[3/9/2019 8:53:49 PM]
ROL - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rol[3/9/2019 8:53:49 PM]
ROL - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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ROR - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
ROR
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
ROTATE RIGHT
DESCRIPTION:
.---------------. .-.
.->|7 ----------> 0|--.->|C| | '---------------' | '-' '---------------------' Rotates the bits in the destination to the right "count" times w
all data pushed out the right side reentering on the left. The
Carry Flag will contain the value of the last bit rotated out.
USAGE:ROR
dest,count
dest-mem/reg
FLAGS:CF OF
CLOCKS AND SIZE:
Operands
Clock Cycles
8086
80286
80386
80486
2
2
3
3
7
7
4 2-4
5+n
3
3
20+EA+4n
8+n
7
4 2-4
reg,immed8
-
5+n
3
2
mem,immed8
-
8+n
7
4 3-5
SUB
reg,1
XADD
mem,1
15+EA
reg,CL
8+4n
mem,CL
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
Size in bytes
EXAMPLES:
ROR SI,10 : SI is rotated left by 10 places
ROR BYTE PTR[BX],2 : The byte contents of the data segment
addressed by BX is rotated left by 2 places
ROR
SAR
SHL/SAL
Comments
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/ror[3/9/2019 8:54:15 PM]
2
2
3
ROR - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/ror[3/9/2019 8:54:15 PM]
ROR - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/ror[3/9/2019 8:54:15 PM]
ROR - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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SAR - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
SAR
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHIFT ARITHMETIC RIGHT
DESCRIPTION:
.---------------. .-.
.--|7 ----------> 0|---->|C|
| '---------------' '-'
'---^
Shifts the destination right by "count" bits with the current si
bit replicated in the leftmost bit. The Carry Flag contains the
last bit shifted out.
USAGE:SAR
dest,count
dest-mem/reg
FLAGS:CF OF PF SF ZF (AF undefined)
CLOCKS AND SIZE:
Operands
Clock Cycles
reg,1
Size in bytes
8086
80286
80386
80486
2
2
3
3
7
7
4 2-4
mem,1
15+EA
reg,CL
8+4n
5+n
3
3
mem,CL
20+EA+4n
8+n
7
4 2-4
reg,immed8
-
5+n
3
2
mem,immed8
-
8+n
7
4 3-5
2
2
3
EXAMPLES:
SAR SI,2 : SI is arithmetically shifted 2 places to the right
SAR DATA1,CL : The contents of data segment addressed by DATA1
is right shifted arithmetically by the number specified by CL.
SAR BYTE PTR[BX],10 :The byte contents addressed by BX is
arithmetically right shifted by 10.
Comments
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/sar[3/9/2019 8:54:45 PM]
SAR - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/sar[3/9/2019 8:54:45 PM]
SAR - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/sar[3/9/2019 8:54:45 PM]
SAR - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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SHL/SAL - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
SHL/SAL
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
SHIFT LOGICAL LEFT/ SHIFT ARITHMETIC LEFT
DESCRIPTION:
.-. .---------------. .-.
|C|<----|7 <---------- 0|<----|0|
'-' '---------------' '-'
Shifts the destination left
by "count" bits with zeroes shifted in on the right.
The Carry Flag contains the last bit shifted out.
DAS
USAGE: SHL/SAL
DEC
dest-mem/reg
DIV
IDIV
IMUL
INC
dest,count
FLAGS: CF OF PF SF ZF (AF undefined)
CLOCKS AND SIZE:
Operands
Clock Cycles
Size in bytes
8086
80286
80386
80486
MUL
reg,1
2
2
3
3
2
NEG
mem,1
15+EA
7
7
4
2-4
SBB
reg,CL
8+4n
5+n
3
3
2
mem,CL
20+EA+4n
8+n
7
4
2-4
reg,immed8
-
5+n
3
2
3
mem,immed8
-
8+n
7
4
3--5
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
EXAMPLES:
SHL/SAL ECX,10
SHL/SAL ECX,CL
: ECX is logically shifted left 10 places
: ECX is logically shifted left by the number
of spaces specified by CL
SHL/SAL BYTE PTR[BX],10 : The byte contents of data segment
addressed by BX is logically left shifted by
10
ROR
SAR
Comments
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shl-sal[3/9/2019 8:55:14 PM]
SHL/SAL - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shl-sal[3/9/2019 8:55:14 PM]
SHL/SAL - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shl-sal[3/9/2019 8:55:14 PM]
SHL/SAL - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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SHR - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
SHR
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
SHIFT LOGICAL RIGHT
DESCRIPTION:
.-. .---------------. .-.
|0|---->|7 ----------> 0|---->|C|
'-' '---------------' '-'
Shifts the destination right by "count" bits with zeroes shifted The Carry Flag contains the last bit shifted out.
USAGE: SHR
dest,count
dest-mem/reg
FLAGS: CF OF PF SF ZF (AF undefined)
CLOCKS AND SIZE:
Operands
Clock Cycles
reg,1
Size in bytes
8086
80286
80386
2
2
3
7
7
mem,1
15+EA
SBB
reg,CL
8+4n
5+n
3
mem,CL
20+EA+4n
8+n
7
SUB
reg,immed8
-
5+n
3
XADD
mem,immed8
-
8+n
7
NEG
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
80486
SAR
2-4
2
2-4
3
3--5
EXAMPLES:
SHR ECX,10
SHR ECX,CL
: ECX is logically shifted right 10 places
: ECX is logically shifted right by the number of
spaces specified by CL.
SHR BYTE PTR[BX],10 : The byte contents of data segment
addressed by BX is logically right shifted by
10.
ROL
ROR
2
Comments
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shr[3/9/2019 8:55:41 PM]
SHR - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shr[3/9/2019 8:55:41 PM]
SHR - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shr[3/9/2019 8:55:41 PM]
SHR - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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SHRD/SHLD - Microprocessors@BITS
Microprocessors@BITS
Home
Bit Manipulation Instructions ‎ > ‎
Arithmetic
Instructions
SHRD/SHLD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Search this site
DOUBLE PRECISION SHIFT (386+)
DESCRIPTION:
SHLD shifts "dest" to the left "count" times and the bit positio
opened are filled with the most significant bits of "src". SHRD
shifts "dest" to the right "count" times and the bit positions
opened are filled with the least significant bits of the second
operand. Only the 5 lower bits of "count" are used.
USAGE:
SHLD dest,src,count
SHRD dest,src,count
FLAGS: CF PF SF ZF (OF,AF undefined)
CLOCKS AND SIZES:
Operands
Clock Cycles
8086
80286
Size in bytes
80386
80486
reg,reg,imm 3
2
4
mem,reg,imm
7
3
6
reg,reg,CL
3
3
3
mem,reg,CL
7
3
5
Logical AND
Logical NOT
Logical OR
Logical XOR
Comments
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shrd-shld[3/9/2019 8:56:11 PM]
SHRD/SHLD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shrd-shld[3/9/2019 8:56:11 PM]
SHRD/SHLD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shrd-shld[3/9/2019 8:56:11 PM]
SHRD/SHLD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Data Transfer - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
AAD
AAM
Data Transfer
This category enlists and describes all functions used for transfer of data between
registers, between registers and memory, or between two locations in memory.
AAS
Instructions
ADC
CMPXCHG
ADD
LAHF
CMP
LAR
DAA
LDS/LES
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
Search this site
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
SUB
XADD
Bit Manipulation
Instructions
Subpages (12): CMPXCHG LAHF LAR LDS/LES LEA MOV MOVS MOVSX
[386+] MOVZX SAHF XCHG XLAT(B)
BSWAP
Logical AND
Comments
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer[3/9/2019 8:56:41 PM]
Data Transfer - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer[3/9/2019 8:56:41 PM]
Data Transfer - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer[3/9/2019 8:56:41 PM]
Data Transfer - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CMPXCHG - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
CMPXCHG
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
This instruction compares the accumulator (AL/AX/EAX) (8-32 bits) with the operand
"dest". If equal the "dest" is loaded with the operand "src", otherwise the accumulator is
loaded with "dest".
Usage CMPXCHG dest,src
Flags AF PF OF CF ZF SF
Clocks and Size
Operands
Clocks
Size Bytes
486
reg,reg
6
2
reg,mem
7
2
Example
;Assume AX = 0010H, CX = 0010H, DX = 0012H
CMPXCHG CX, DX
; CX = AX so CX = 0012H
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/cmpxchg[3/9/2019 8:57:08 PM]
CMPXCHG - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/cmpxchg[3/9/2019 8:57:08 PM]
CMPXCHG - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/cmpxchg[3/9/2019 8:57:08 PM]
CMPXCHG - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Google Sites
LAHF - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
LAHF
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
This instruction copies the
Search this site
low byte of the flag register to AH. Only
the remaining bits are undefined. After copying, AH looks like this:
AH = SF ZF xx AF xx PF xx CF
Usage LAHF
Flags None
Clocks and Size
Operands
Clock Cycles
8086
none
4 Size in bytes
80286
80386
80486
2
2
3
INC
MUL
NEG
SBB
five flags are copied
Comments
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/lahf[3/9/2019 8:57:39 PM]
1
LAHF - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/lahf[3/9/2019 8:57:39 PM]
LAHF - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/lahf[3/9/2019 8:57:39 PM]
LAHF - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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LAR - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
LAR
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
LOAD ACCESS RIGHT (286+ protected)
DESCRIPTION:
The high byte of the of the destination register is overwritten
the value of the access rights byte and the low order byte is ze
depending on the selection in the source operand. The Zero Flag
set if the load operation is successful.
USAGE:
LAR dest,src
FLAGS: ZF
CLOCKS AND SIZES:
Operands
Clock Cycles
8086
SBB
reg16, reg16
SUB
reg32, reg32
XADD
reg16, mem16
Bit Manipulation
Instructions
Search this site
reg32, mem32
80286
14
16
Size in bytes
80386
15
11
3
15
11
3
16
11
3-7
16
11
3-7
BSWAP
Logical AND
Logical NOT
Logical OR
80486
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/lar[3/9/2019 8:58:05 PM]
LAR - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/lar[3/9/2019 8:58:05 PM]
LAR - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/lar[3/9/2019 8:58:05 PM]
LAR - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Google Sites
LDS/LES - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
LDS/LES
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Search this site
This instruction copies a word from two memory locations into the register specified in the
instruction. It then copies a word from the next two memory locations into the DS(ES)
register. It is useful for pointing to SI(DI) and DS(ES) at the start of a string before using a
string instruction.
Usage LDS dest, src
Operands
src
Memory address of first word
dest
Register
Flags None.
Clocks and Size
Operands
Clocks
8086
reg16,mem32
16+EA
reg,mem (PM)
-
-
Size in bytes
286
386
7
7
6 2-4
22
12 5 - 7
Example
LDS BX, [4326] ;Copy contents of memory at displacement 4326H in DS to BL,
contents of 4327H to BH. The contents at a displacement of 4328H and 4329H
are copied to the DS register.
Logical OR
Logical XOR
RCL
486
Comments
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/lds-les[3/9/2019 8:58:34 PM]
LDS/LES - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/lds-les[3/9/2019 8:58:34 PM]
LDS/LES - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/lds-les[3/9/2019 8:58:34 PM]
LDS/LES - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Google Sites
LEA - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
LEA
AAA
AAD
AAM
Search this site
Transfers offset address of "src" to the destination register. LEA is very similar to MOV, except
that math can be done on the original value before it is used.
AAS
ADC
ADD
CMP
DAA
DAS
DEC
Usage LEA dest, src
dest must be a register.
Flags None.
Clocks and Size
Operands
Clocks
DIV
IDIV
IMUL
INC
MUL
NEG
8086
reg,mem
2+EA
386
3
2
Example
lea
lea
eax, [eax+eax] ; Double the value of eax -- eax = eax * 2
edi, [esi+0Bh] ; Add 11 to esi and store the result in edi
SBB
SUB
Size in bytes
286
Comments
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/lea[3/9/2019 8:59:00 PM]
486
1 2-4
LEA - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/lea[3/9/2019 8:59:00 PM]
LEA - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/lea[3/9/2019 8:59:00 PM]
LEA - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Google Sites
MOV - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
MOV
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
Search this site
Description
The MOV instruction copies a word or byte of data from a specified source to a
specified destination. The source and destination in an instrcution cannot both be
memory locations. For the MOV instruction, the src and dest addresses must both be
of type byte or both of type word.
Usage MOV dest, src
dest - Reg/Mem
src - Reg/Mem/Imm
Flags
None.
Clocks and Size
Clock Cycles
Instruction
reg,reg
8086
80286
80386
80486 Size in bytes
2
2
2
1
2
mem,reg
9+EA
3
2
1 2-4
reg,mem
8+EA
5
4
1 2-4
mem,immed
10+EA
3
2
1 3-6
4
2
2
1 2-4
mem,accum
10
3
2
1
3.000
accum,mem
10
5
4
1
3.000
Logical XOR
segreg,reg16
2
2
2
3
2.000
RCL
segreg,mem16
5
5
9 2-4
2
2
3
3
2
3 2-4
BSWAP
Logical AND
Logical NOT
Logical OR
RCR
ROL
reg,immed
8+EA
reg16,segreg
mem16,segreg
2
9+EA
6
4
CR0,reg32
10
16
SAR
CR2,reg32
4
4
3
SHL/SAL
CR3,reg32
5
4
3
22
10
3
ROR
SHR
reg32,CR0/CR2/CR3
2.000
reg32,DR0/DR1/DR2/DR3
https://sites.google.com/site/microprocessorsbits/data-transfer/move[3/9/2019 8:59:36 PM]
MOV - Microprocessors@BITS
reg32,DR6/DR7
22
10
3
Data Transfer
DR0/DR1/DR2/DR3,reg32
22
11
3
DR6/DR7,reg32
16
11
3
CMPXCHG
reg32,TR6/TR7
12
4
3
LAHF
TR6/TR7,reg32
12
4
3
SHRD/SHLD
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
reg32,TR3
3
TR3,reg32
6
Examples
mov eax, ebx — copy the value in ebx into eax
mov byte ptr [var], 5 — store the value 5 into the byte at location var
SAHF
XCHG
XLAT(B)
Comments
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/move[3/9/2019 8:59:36 PM]
MOV - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/move[3/9/2019 8:59:36 PM]
MOV - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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MOVS - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
MOVS
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Search this site
Copies data from addressed by DS:SI (even if operands are given) to the location ES:DI
destination and updates SI and DI based on the size of the operand or instruction used. SI and
DI are incremented when the Direction Flag is cleared and decremented when the Direction
Flag is Set. Use with REP prefixes.
Usage MOVS( /B/W/D) dest, src
dest ES:DI
src DS:SI
Flags
None.
Clocks and Size
Operands
Clocks
Size in bytes
8086
286
386
486
18
5
7
7
dest,src
Example
; copy mystr into mystr2
mov esi, mystr
mov edi, mystr2
cld
mov ecx,4
rep movsw
Logical AND
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/movs[3/9/2019 9:00:03 PM]
1
MOVS - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/movs[3/9/2019 9:00:03 PM]
MOVS - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/movs[3/9/2019 9:00:03 PM]
MOVS - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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MOVSX [386+] - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
MOVSX [386+]
AAA
AAD
AAM
Copies the value of the source operand to the destination register with the sign extended.
AAS
Usage MOVSX dest,src
ADC
Flags None
ADD
CMP
DAA
DAS
Search this site
Operands
Clocks
Size Bytes
386
486
reg,reg
3
3
reg,mem
6
3 3-7
3
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
Example
MOVSX r32,r/m16 Move word to double word, sign-extension
0x1000 becomes 0x00001000, since it was positive
0x7FFF becomes 0x00007FFF, since it was positive
0xFFFF becomes 0xFFFFFFFF, since it was negative (note that 0xFFFF is -1 in 16bit signed, and 0xFFFFFFFF is -1 in 32-bit signed)
0x8000 becomes 0xFFFF8000, since it was negative (note that 0x8000 is -32768 in 16bit signed, and 0xFFFF8000 is -32768 in 32-bit signed)
SUB
XADD
Bit Manipulation
Instructions
Comments
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/movsx[3/9/2019 9:00:29 PM]
MOVSX [386+] - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/movsx[3/9/2019 9:00:29 PM]
MOVSX [386+] - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/movsx[3/9/2019 9:00:29 PM]
MOVSX [386+] - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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MOVZX - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
MOVZX
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
Search this site
This instruction copies the value of the source operand to the destination operand with the
zeros extended. This instruction is only available 386 onwards.
Usage MOVZX dest, src
Flags None
Clocks and Size
Operands
Clocks
Size in bytes
8086
286
386
486
IDIV
reg,reg
-
-
3
3
3
IMUL
reg,mem
-
-
6
3
3- 7
INC
MUL
NEG
SBB
SUB
Comments
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/movzx[3/9/2019 9:00:54 PM]
MOVZX - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/movzx[3/9/2019 9:00:54 PM]
MOVZX - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/movzx[3/9/2019 9:00:54 PM]
MOVZX - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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SAHF - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
SAHF
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
Search this site
SAHF- Store AH Register into Flags
DESCRIPTION: Transfers bits of AH register into the Flag
Register. This includes AF, CF, PF, SF and ZF.
USAGE: SAHF
FLAGS: AF CF PF SF ZF
CLOCKS AND SIZES:
Operands
Clock Cycles
8086
none
4 Size in bytes
80286
80386
80486
2
3
2
INC
MUL
NEG
Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/sahf[3/9/2019 9:01:20 PM]
1
SAHF - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/sahf[3/9/2019 9:01:20 PM]
SAHF - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/sahf[3/9/2019 9:01:20 PM]
SAHF - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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XCHG - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
XCHG
AAA
AAD
AAM
AAS
ADC
ADD
The xchg (exchange) instruction swaps the src operand with the dest operand. It's like doing three
move operations: from dest to a temporary (another register), then from src to dest, then from the
temporary to src, except that no register needs to be reserved for temporary storage.
Only one operands can be in memory: at least one has to be a register.
CMP
Usage XCHG dest, src
DAA
Flags None.
DAS
DEC
DIV
IDIV
Search this site
Clocks and Size
Operands
Clocks
reg,reg
Size Bytes
8086
286
386
486
4
3
3
3
2
IMUL
mem,reg
17+EA
5
5
5 2-4
INC
reg,mem
17+EA
5
5
3 2-4
MUL
accum,reg
3
3
3
3
1
reg,accum
3
3
3
3
1
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Example
XCHG AX, r16 Exchange r16 with AX
XCHG r/m32,r32 Exchange r32 with doubleword from r/m32
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/xchg[3/9/2019 9:01:46 PM]
XCHG - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/xchg[3/9/2019 9:01:46 PM]
XCHG - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/xchg[3/9/2019 9:01:46 PM]
XCHG - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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XLAT(B) - Microprocessors@BITS
Microprocessors@BITS
Home
Data Transfer ‎ > ‎
Arithmetic
Instructions
XLAT(B)
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
Search this site
Replaces the byte in AL with byte from a user table addressed by BX. Before the XLAT
instruction can be executed, the lookup table containing the values for the new code must be
put in memory, and the offset of the starting address of the lookup table must be loaded in
BX. The best way to describe this is MOV AL,[BX+AL].
Usage XLATB
Flags None.
Clocks and Size
Operands
table offset
Clocks
Size in bytes
8086
286
386
486
11
5
5
4
Example
XLATB Set AL to memory byte DS:[(E)BX + unsigned AL]
Comments
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/xlat[3/9/2019 9:02:13 PM]
1
XLAT(B) - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/data-transfer/xlat[3/9/2019 9:02:13 PM]
XLAT(B) - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/data-transfer/xlat[3/9/2019 9:02:13 PM]
XLAT(B) - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Miscellaneous - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
AAD
AAM
Miscellaneous
This page includes instructions that don't quite fall under any of the other major
categories.
AAS
Subpage Listing
ADC
BT
ADD
CBW
CMP
CDQ
DAA
CWD
DAS
DEC
CWDE
DIV
IDIV
IMUL
INC
MUL
Search this site
Subpages (5): BT CBW CDQ CWD CWDE
Comments
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous[3/9/2019 9:02:44 PM]
Miscellaneous - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/miscellaneous[3/9/2019 9:02:44 PM]
Miscellaneous - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/miscellaneous[3/9/2019 9:02:44 PM]
Miscellaneous - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Google Sites
BT - Microprocessors@BITS
Microprocessors@BITS
Home
Miscellaneous ‎ > ‎
Arithmetic
Instructions
BT
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
Search this site
The Bit Test instruction copies to the CF the bit at index 'src' in the 'dest' operand. This
instruction is available 386 onwards.
Usage BT dest, src
Flags CF
Clocks and Size
Operands
Clocks
8086
286
Size in Bytes
386
486
IDIV
reg16,immed8
-
-
3
3
4-8
IMUL
mem16,immed8
-
-
6
6
4-8
reg16,reg16
-
-
3
3
3-7
mem16,reg16
-
-
12
12
3-7
INC
MUL
NEG
SBB
SUB
XADD
Example
BT AX, 4 ;Copy the fifth least-significant bit from AX to CF
Bit Manipulation
Instructions
BSWAP
Logical AND
Comments
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/bt[3/9/2019 9:03:12 PM]
BT - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/miscellaneous/bt[3/9/2019 9:03:12 PM]
BT - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/miscellaneous/bt[3/9/2019 9:03:12 PM]
BT - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Google Sites
CBW - Microprocessors@BITS
Microprocessors@BITS
Home
Miscellaneous ‎ > ‎
Arithmetic
Instructions
CBW
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
Search this site
This instruction (Convert signed Byte to signed Word) fills AH with the sign of the byte in
AL. AH is then the sign extension of AL.
CBW is usually done before the signed byte in AL can be divided by another signed byte
with the IDIV instruction.
Usage CBW
Flags None
Clocks and Size
Operands
Clocks
none
Size in Bytes
8086
286
386
486
2
2
3
3
NEG
SBB
Example
SUB
XADD
CBW ;AX = 11111111 10011011 = -155 in Decimal (Signed)
Bit Manipulation
Instructions
BSWAP
; AL = 10011011 = -155 in Decimal (Signed)
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/cbw[3/9/2019 9:03:40 PM]
1
CBW - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/miscellaneous/cbw[3/9/2019 9:03:40 PM]
CBW - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/miscellaneous/cbw[3/9/2019 9:03:40 PM]
CBW - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CDQ - Microprocessors@BITS
Microprocessors@BITS
Home
Miscellaneous ‎ > ‎
Arithmetic
Instructions
CDQ
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
Search this site
CONVERT DOUBLE TO QUAD
DESCRIPTION:Converts signed DWORD in EAX to a signed quad word i extending the high order bit of EAX throughout EDX.
USAGE:CDQ
FLAGS:NONE
CLOCKS AND SIZES:
Operands
Clock Cycles
Size in bytes
8086
none
-
80286
80386
80486
2
3
-
1
EXAMPLE:
If EAX is 011111110011101110011101110010111110
CDQ will result in
EDX:EAX =
00000000000000000000000000000000:0111111100111011100111011100101
Comments
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/cdq[3/9/2019 9:04:09 PM]
CDQ - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/miscellaneous/cdq[3/9/2019 9:04:09 PM]
CDQ - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/miscellaneous/cdq[3/9/2019 9:04:09 PM]
CDQ - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CWD - Microprocessors@BITS
Microprocessors@BITS
Home
Miscellaneous ‎ > ‎
Arithmetic
Instructions
CWD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
Search this site
This instruction (Convert signed Word to signed Doubleword) copies the sign bit of a word in
AX to all the bits of DX. DX is then the sign extension of AX.
This instruction must be done before a signed word in AX can be divided by another signed
word with the IDIV instruction.
Usage CWD
Flags None
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
5
2
2
3
NEG
SBB
Example
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
;AX = 11110000 11000111 = -3897 decimal
CWD ;Result: DX = 11111111 11111111, AX = 11110000 11000111
Comments
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/cwd[3/9/2019 9:04:34 PM]
1
CWD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/miscellaneous/cwd[3/9/2019 9:04:34 PM]
CWD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/miscellaneous/cwd[3/9/2019 9:04:34 PM]
CWD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Google Sites
CWDE - Microprocessors@BITS
Microprocessors@BITS
Home
Miscellaneous ‎ > ‎
Arithmetic
Instructions
CWDE
AAA
AAD
AAM
AAS
ADC
This instruction converts a signed word in AX to a signed doubleword in EAX by extending
the sign bit of AX throughout EAX (unlike CWD which uses DX:AX).
Usage CWDE
ADD
Flags None
CMP
Clocks and Size
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
Search this site
Operands
none
Clocks
Size in Bytes
8086
286
386
486
-
-
3
3
Example
;AX = 11110000 11000111 = -3897 decimal
CWD ;Result: EAX = 11111111 11111111 11110000 11000111, AX = 11110000
11000111
NEG
SBB
Comments
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/cwde[3/9/2019 9:05:00 PM]
1
CWDE - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/miscellaneous/cwde[3/9/2019 9:05:00 PM]
CWDE - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/miscellaneous/cwde[3/9/2019 9:05:00 PM]
CWDE - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Processor Control Instructions - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
Processor Control Instructions
AAD
Subpage Listing
AAM
CLC
AAS
CLD
ADC
CLI
ADD
CMC
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
Search this site
ESC
LOCK
NOP
STC
STD
STI
WAIT
MUL
NEG
SBB
SUB
XADD
Subpages (11): CLC CLD CLI CMC ESC LOCK NOP STC STD STI WAIT
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions[3/9/2019 9:05:28 PM]
Processor Control Instructions - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions[3/9/2019 9:05:28 PM]
Processor Control Instructions - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions[3/9/2019 9:05:28 PM]
Processor Control Instructions - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CLC - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
CLC
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
Search this site
‎>‎
This instruction clears the Carry Flag (CF).
Usage CLC
Flags CF
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
2
2
2
2
IDIV
IMUL
INC
Comments
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/clc[3/9/2019 9:05:55 PM]
1
CLC - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/clc[3/9/2019 9:05:55 PM]
CLC - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/clc[3/9/2019 9:05:55 PM]
CLC - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CLD - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
CLD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
Search this site
‎>‎
This instruction resets the Direction Flag to
0. SI and DI are automatically
when one of the string instructions is executed.
Usage CLD
Flags CF
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
2
2
2
2
IMUL
INC
MUL
incremented
Comments
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cld[3/9/2019 9:06:23 PM]
1
CLD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cld[3/9/2019 9:06:23 PM]
CLD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cld[3/9/2019 9:06:23 PM]
CLD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CLI - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
CLI
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
Search this site
‎>‎
This instruction resets the interrupt flag to
0. If the interrupt flag is reset, the 8086
respond to an interrupt signal on its INTR input.
The CLI instruction has no effect on the non-maskable interrupt (NMI).
Usage CLI
Flags IF
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
2
2
3
5
MUL
NEG
SBB
SUB
will n
Comments
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cli[3/9/2019 9:06:51 PM]
1
CLI - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cli[3/9/2019 9:06:51 PM]
CLI - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cli[3/9/2019 9:06:51 PM]
CLI - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CMC - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
CMC
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
Search this site
‎>‎
COMPLEMENT CARRY
DESCRIPTION:Toggles (inverts) the Carry Flag.
USAGE: CMC
FLAGS: CF
CLOCKS AND SIZES:
Operands
none
Clock Cycles
Size in bytes
8086
80286
80386
80486
2
2
2
2
IDIV
IMUL
INC
MUL
NEG
Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cmc[3/9/2019 9:07:17 PM]
1
CMC - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cmc[3/9/2019 9:07:17 PM]
CMC - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cmc[3/9/2019 9:07:17 PM]
CMC - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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ESC - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
ESC
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
Search this site
‎>‎
ESCAPE
DESCRIPTION: The ESC instruction passes instructions to
floating point coprocessor from the microprocessor. Whenever
an ESC instruction executes, the microprocessor provides the
memory address, if required, but otherwise performs a NOP.
USAGE: ESC immed,src
FLAGS: NONE
CLOCKS AND SIZES:
Operands
Clock Cycles
Size in bytes
8086
80286
80386
80486
immed, reg 2
9-20
2
immed, mem
2
9-20
2-4
Comments
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/esc[3/9/2019 9:07:46 PM]
ESC - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/esc[3/9/2019 9:07:46 PM]
ESC - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/esc[3/9/2019 9:07:46 PM]
ESC - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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LOCK - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
LOCK
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
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‎>‎
DESCRIPTION: The LOCK prefix appends to an instruction and
causes the x86 LOCK Pin to be asserted(become logic 0) and
thereby causing external bus masters and other peripherals to
be disabled.
The LOCK instruction causes the LOCK pin to be activated for
only the duration of the locked instruction.
USAGE : LOCK : [Instruction]
FLAGS : NONE
CLOCKS AND SIZES:
Operands
Clock Cycles
Size in bytes
8086
80286
80386
80486
2
0
0
1
none
EXAMPLES:
LOCK: MOV AL,BL
;
Causes the LOCK Pin to be activated for
the particular mov instruction
Logical NOT
Logical OR
Logical XOR
Comments
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/lock[3/9/2019 9:08:14 PM]
1
LOCK - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/lock[3/9/2019 9:08:14 PM]
LOCK - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/lock[3/9/2019 9:08:14 PM]
LOCK - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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NOP - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
NOP
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
‎>‎
NO OPERATION
DESCRIPTION:This is a do nothing instruction. It results in occ
space and time and is most useful for patching code segments.
USAGE: NOP
FLAGS: NONE
CLOCKS AND SIZES:
Operands
none
Clock Cycles
Size in bytes
8086
80286
80386
80486
3
3
3
1
INC
EXAMPLE:
MUL
;To do nothing 2 times:
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
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DELAY:
NOP
NOP
; does nothing
; does nothing
RET
; returns to point of function call
Comments
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/nop[3/9/2019 9:08:40 PM]
1
NOP - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/nop[3/9/2019 9:08:40 PM]
NOP - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/nop[3/9/2019 9:08:40 PM]
NOP - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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STC - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
STC
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
This instruction sets the
Search this site
‎>‎
carry flag (CF) to 1.
Usage STC
Flags CF
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
2
2
2
2
IDIV
IMUL
INC
Comments
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/stc[3/9/2019 9:09:09 PM]
1
STC - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/stc[3/9/2019 9:09:09 PM]
STC - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/stc[3/9/2019 9:09:09 PM]
STC - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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STD - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
STD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
Search this site
‎>‎
This instruction is used to set the
Direction Flag to 1 so that SI/DI will automatically
decrement when one of the string instructions executes.
Usage STD
Flags DF
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
2
2
2
2
IMUL
INC
MUL
Comments
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/std[3/9/2019 9:09:37 PM]
1
STD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/std[3/9/2019 9:09:37 PM]
STD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/std[3/9/2019 9:09:37 PM]
STD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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STI - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
STI
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
Search this site
‎>‎
Setting the interrupt flag
enables the INTR interrupt input of the 8086. The instruction
will not take effect until after the next instruction after STI.
When the INTR input is enabled, an interrupt signal on this input will then cause the 8086 to
interrupt program execution, push the return address and flags on the stack, and execute an
interrupt service procedure. An IRET instruction after the interrupt service procedure restores
flags and returns execution to the interrupted program.
Usage STI
Flags IF
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
2
2
2
5
SUB
XADD
Bit Manipulation
Instructions
Comments
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/sti[3/9/2019 9:10:03 PM]
1
STI - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/sti[3/9/2019 9:10:03 PM]
STI - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/sti[3/9/2019 9:10:03 PM]
STI - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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WAIT - Microprocessors@BITS
Microprocessors@BITS
Home
Processor Control Instructions
Arithmetic
Instructions
WAIT
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
Search this site
‎>‎
DESCRIPTION: The WAIT instruction monitors the hardware BUSY
pin on 80286 and 80386, and the TEST pin on the 8086/8088. If
WAIT instruction executes while the pin=1, nothing happens and
the next instruction executes normally. If pin=0, when the
WAIT instruction executes, the microprocessor waits for the
pin to return to logic 1. This instruction is used to prevent
the CPU fromaccessing memory that may be
temporarily in use by the coprocessor.
USAGE: WAIT
IMUL
INC
MUL
NEG
SBB
SUB
XADD
FLAGS: NONE
CLOCKS AND SIZES:
Operands
none
Clock Cycles
Size in bytes
8086
80286
80386
80486
4
3
6+
1-3
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/wait[3/9/2019 9:10:29 PM]
1
WAIT - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/wait[3/9/2019 9:10:29 PM]
WAIT - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/wait[3/9/2019 9:10:29 PM]
WAIT - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Program Execution Transfer Instructions - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
Program Execution Transfer
Instructions
Instructions here transfer control of the program from the current address to some
other address below or above. This is necessary if sequential execution of
instructions is not desired like in cases of conditional/ unconditional branch, loop, etc.
The conditional transfer instructions like jump if carry, compare values in order to
decide whether or not a jump is taken to the given address. The
terms above and below refer to unsigned binary numbers where above means
greater in magnitude and below means lesser in magnitude in such instructions. In
signed number comparisons the terms greater than and less than are used.
INC
Subpage Listing
MUL
CALL
NEG
ENTER
SBB
INT
SUB
INTO
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
Logical OR
JC
Logical XOR
JCXZ
RCL
JE/JZ
RCR
JG/JNLE
ROL
JGE/JNL
ROR
JL/JNGE
SAR
SHL/SAL
SHR
Search this site
JLE/JNG
JMP
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions[3/9/2019 9:10:58 PM]
Program Execution Transfer Instructions - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
JNE/JNZ
JNO
JNP/JPO
JNS
JO
LDS/LES
JP/JPE
LEA
JS
MOV
LEAVE
MOVS
LOOP
MOVSX [386+]
LOOPE/LOOPZ
MOVZX
LOOPNE/LOOPNZ
SAHF
XCHG
TEST
XLAT(B)
Miscellaneous
BT
CBW
CDQ
Subpages (29): View All
Comments
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution Transfer
Instructions
CALL
ENTER
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions[3/9/2019 9:10:58 PM]
Program Execution Transfer Instructions - Microprocessors@BITS
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
CMPS/CMP…
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions[3/9/2019 9:10:58 PM]
Program Execution Transfer Instructions - Microprocessors@BITS
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CALL - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
CALL
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
‎>‎
DESCRIPTION:Pushes Instruction Pointer (and Code Segment for far stack and loads Instruction Pointer with the address of procedur
name.
Code continues with execution at CS:IP.
USAGE: CALL destination
destination-label/reg/mem
FLAGS: None
CLOCK CYCLES:
Operands
Clock Cycles
8086
80286
80386
80486
label(near)
19
7
7
3
label(far)
28
13
17
18
reg(near)
16
7
7
5
11
10
5
7
7
5
mem(near)
mem(far)
21+EA
16
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
EXAMPLES:
CALL BX ; The program flow jumps to the offset address
specified in BX register(within the current code segment).
CALL FUNCTION1 ; Program flow switches to location with label
'FUNCTION1'.
Comments
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/call[3/9/2019 9:11:27 PM]
CALL - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/call[3/9/2019 9:11:27 PM]
CALL - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/call[3/9/2019 9:11:27 PM]
CALL - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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ENTER - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
ENTER
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
‎>‎
Description: Modifies stack for entry into procedures for high level languages. Paired with
the LEAVE instruction, this is an efficient method of entry and exit to procedures. This
instruction is available from 80188 onward.
Usage: ENTER storage, level
[storage: amount of storage to be allocated on the stack, a 16 bit immediate value]
[level: nesting level of the routine, an 8 bit immediate value]
Flags: the instruction has no effect on any flags.
Clocks and size:
Operands
Clocks
8086
none
-
Size in Bytes
286
5
386
4
486
5
1
Example:
ENTER 16, 0; creates a stack frame for a procedure
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/enter[3/9/2019 9:11:55 PM]
ENTER - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/enter[3/9/2019 9:11:55 PM]
ENTER - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/enter[3/9/2019 9:11:55 PM]
ENTER - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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INT - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
INT
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
The INT instruction initiates a
3. Decrement the stack pointer by 3 and push the offset of the next instruction after the INT
number instruction on the stack.
4. Get a new value for UP from an absolute memory address of 4 times the type specified in
the instruction. For an INT 8 instruction, for example, the new IP will be read from address
00020H.
5. Get a new value for CS from an absolute memory address of 4 times the type specified in
the instruction plus 2. For the same example, CS = 00022H.
6. Reset both IF and TF.
Usage INT <Type>
Type is between 0 and 255
Flags IF, TF
Clocks and Size
Operands
3 (prot. mode,
486
33
26
2
-
40+m
59
44
2
-
78+m
99
71
2
-
-
119
82
2
task gate)
-
167+m
immed8
52/72
23+m
37
30
1
-
40+m
59
44
1
same priv.)
3 (prot. mode,
more priv.)
RCR
PL 0)
ROL
3 (prot. mode via
SHR
386
23+m
3 (from VM86 to
SHL/SAL
286
Size in Bytes
51/71
RCL
SAR
Clocks
8086
Logical NOT
ROR
software interrupt by doing the following:
2. Decrement the stack pointer by 2 and push the contents of CS onto the stack.
3 (constant)
Logical XOR
‎>‎
1. Decremenet the stack pointer by 2 and push the flags onto the stack.
Logical AND
Logical OR
Search this site
TS
37+TS
2
immed8 (prot.
mode, same
priv.)
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/int[3/9/2019 9:12:24 PM]
INT - Microprocessors@BITS
SHRD/SHLD
Data Transfer
immed8 (prot.
mode, more
priv.)
CMPXCHG
immed8 (from
LAHF
VM86 to PL 0)
LAR
immed8 (prot.
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
-
78+m
-
-
-
167+m
99
71
1
119
86
1
mode, via task
gate)
TS
37+TS
1
Example
INT 35 ;New IP from 0008CH, new CS from 0008EH
INT 3 ;Special form which is used as a breakpoint instruction on many systems. New
IP: 0000CH, CS: 0000EH. Has a single-byte
;code CCH.
Comments
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/int[3/9/2019 9:12:24 PM]
INT - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/int[3/9/2019 9:12:24 PM]
INT - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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INTO - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
INTO
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
overflow condition (INT 4). IP is read from 00010H and CS from 00012H.
The foll. steps are executed by the 8086 before doing the call:
1. Decrement the stack pointer by 2 and push the flags onto the stack
2. Decrement SP by 2, push CS onto the stack.
3. Decrement SP by 2, push the offset of the next instruction after INTO onto the stack
4. Reset TF and IF.
Usage INTO
Flags IF, TF
Clocks and Size
Operands
none: jump
286
24+m
4
3
Size in Bytes
386
486
35
28
1
3
3
1
none: (prot.
mode, same
priv.)
mode, more
Logical XOR
priv.)
ROR
53/73
none: no jump
Logical OR
ROL
Clocks
8086
none: (prot.
RCR
‎>‎
INTO stands for the Interrupt on Overflow instruction. If the Overflow Flag (OF) = 1, this
instruction causes the 8086 to do an indirect far call to a procedure you write to handle the
Logical NOT
RCL
Search this site
-
-
59
46
1
-
-
99
73
1
-
-
84
119
1
-
-
none: (from
VM86 to PL 0)
none: (prot.
mode, via task
gate)
TS
39+TS
SAR
SHL/SAL
SHR
Comments
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/into[3/9/2019 9:12:59 PM]
1
INTO - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/into[3/9/2019 9:12:59 PM]
INTO - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/into[3/9/2019 9:12:59 PM]
INTO - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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IRET - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
IRET
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
Search this site
‎>‎
The IRET instruction is used at the end of an interrupt service procedure to return execution
to the interrupted program. To do this return, the 8086 copies the saved value of IP from the
stack to IP, the stored value of CS from the stack to CS, and the stored value of the flags back
to the flag register.
Flag values from the procedure will be lost unless they are specifically saved in some way.
Usage IRET
IRETD (386+)
Flags AF, CF, DF, IF, ZF, SF, TF, PF
Clocks and Size
Operands
Clocks
8086
286
Size in Bytes
386
486
SBB
(iret)none
32/44
17+m
22
15
1
SUB
(prot. mode)
-
31+m
38
15
1
-
55+m
82
36
1
NT=1)
-
169+m
TS
BSWAP
(iretd)
-
-
22/38
Logical AND
(to less
-
-
(to VM86 mode) -
-
XADD
Bit Manipulation
Instructions
Logical NOT
Logical OR
Logical XOR
(to less
privilege)
(different task,
privilege)
TS+32
1
15
1
82
36
1
60
15
1
iretd (different
task, NT=1)
-
-
TS
TS+32
RCL
RCR
ROL
ROR
Comments
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/iret[3/9/2019 9:13:35 PM]
1
IRET - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/iret[3/9/2019 9:13:35 PM]
IRET - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/iret[3/9/2019 9:13:35 PM]
IRET - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JA/JNBE - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JA/JNBE
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if above/ Jump if not below or equal
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes both CF and ZF to have value equal to 0, else
no action is taken.
Usage: JA dest, JNBE dest
[dest: addressin the range of -128 bytes to +127 bytes from the address of instruction after
JA/JNBE]
Flags: the instruction has no effect on any flags.
Example:
CMP AX, 0030H; compares by subtracting 0030H from the value in AX regsiter
JA LABEL1; jumps to the address specified by LABEL1 if value in register AX is above
the value 0030H
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/ja-jnbe-1[3/9/2019 9:14:09 PM]
JA/JNBE - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/ja-jnbe-1[3/9/2019 9:14:09 PM]
JA/JNBE - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/ja-jnbe-1[3/9/2019 9:14:09 PM]
JA/JNBE - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JAE/JNB - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JAE/JNB
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if above or equal/ Jump if not below
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes CF to have value equal to 0, else no action is
taken.
Usage: JAE dest, JNB dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JAE/JNB]
Flags: the instruction has no effect on any flags.
Example:
CMP AX, 0030H; compares by subtracting 0030H from the value in AX regsiter
JAE LABEL1; jumps to the address specified by LABEL1 if value in register AX is above
or equal to the value 0030H
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jae-jnb[3/9/2019 9:14:40 PM]
JAE/JNB - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jae-jnb[3/9/2019 9:14:40 PM]
JAE/JNB - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jae-jnb[3/9/2019 9:14:40 PM]
JAE/JNB - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JB/JNAE/JC - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JB/JNAE/JC
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if below/ Jump if not above or equal
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes CF to have value equal to 1, else no action is
taken.
Usage: JB dest, JNAE dest, JC dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JB/JNAE/JC]
Flags: the instruction has no effect on any flags.
Example:
CMP AX, 0030H; compares by subtracting 0030H from the value in AX regsiter
JB LABEL1; jumps to the address specified by LABEL1 if value in register AX is below
the value 0030H
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jb-jnae[3/9/2019 9:15:15 PM]
JB/JNAE/JC - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jb-jnae[3/9/2019 9:15:15 PM]
JB/JNAE/JC - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jb-jnae[3/9/2019 9:15:15 PM]
JB/JNAE/JC - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JBE/JNA - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JBE/JNA
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if below or equal/ Jump if not above
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes either the CF or ZF to have value equal to 1,
else no action is taken.
Usage: JBE dest, JNA dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JBE/JNA]
Flags: the instruction has no effect on any flags.
Example:
CMP AX, 0030H; compares by subtracting 0030H from the value in AX regsiter
JBE LABEL1; jumps to the address specified by LABEL1 if value in register AX is below
or equal to the value 0030H
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jbe-jna[3/9/2019 9:15:46 PM]
JBE/JNA - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jbe-jna[3/9/2019 9:15:46 PM]
JBE/JNA - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jbe-jna[3/9/2019 9:15:46 PM]
JBE/JNA - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JC - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JC
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
Search this site
‎>‎
Jump if carry
Description: Jumps to the destination label mentioned in the instruction if the value of CF is
1, else no action is taken.
Usage: JC dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JC]
Flags: the instruction has no effect on any flags.
Example: JC LABEL1; jumps to the address specified by LABEL1 if CF is set
Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jc[3/9/2019 9:16:16 PM]
JC - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jc[3/9/2019 9:16:16 PM]
JC - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jc[3/9/2019 9:16:16 PM]
JC - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JCXZ - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JCXZ
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
Search this site
‎>‎
The Jump if CX is Zero causes a jump to a label given in the instruction if CX contains all
zeros; unsigned comparison is used.
JCXZ does not look at ZF when deciding to jump. Destination label must be in the range
of -128 to 127 bytes from the address of the instruction after the JCXZ instruction.
Usage JCXZ Label
JECXZ Label (386+)
Flags None
Clocks and Size
Operands
label: jump
no jump
Clocks
Size in bytes
8086
286
386
486
18
8+m
9+m
8
2
6
4
5
5
2
SUB
XADD
Bit Manipulation
Instructions
Comments
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jcxz[3/9/2019 9:16:42 PM]
JCXZ - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jcxz[3/9/2019 9:16:42 PM]
JCXZ - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jcxz[3/9/2019 9:16:42 PM]
JCXZ - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JE/JZ - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JE/JZ
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
Search this site
‎>‎
Jump if equal/ Jump if zero
Description: Jumps to the destination label mentioned in the instruction if the ZF is set, else
no action is taken.
Usage: JE dest, JZ dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JE/JZ]
Flags: the instruction has no effect on any flags.
Example: JZ LABEL1; jumps to the address specified by LABEL1 if ZF=1
Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/je-jz[3/9/2019 9:17:12 PM]
JE/JZ - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/je-jz[3/9/2019 9:17:12 PM]
JE/JZ - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/je-jz[3/9/2019 9:17:12 PM]
JE/JZ - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JG/JNLE - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JG/JNLE
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if greater/ Jump if not less than or equal
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes ZF to have value equal to 0 and CF and OF
to have same values, else no action is taken.
Usage: JG dest, JNLE dest
[dest: addressin the range of -128 bytes to +127 bytes from the address of instruction after
JG/JNLE]
Flags: the instruction has no effect on any flags.
Example:
CMP AX, 0030H; compares by subtracting 0030H from the value in AX regsiter
JG LABEL1; jumps to the address specified by LABEL1 if value in register AX is more
positive than the value 0030H
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jg-jnle[3/9/2019 9:17:41 PM]
JG/JNLE - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jg-jnle[3/9/2019 9:17:41 PM]
JG/JNLE - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jg-jnle[3/9/2019 9:17:41 PM]
JG/JNLE - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JGE/JNL - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JGE/JNL
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if greater than or equal/ Jump if not less than
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes CF to have value equal to OF, else no action
is taken.
Usage: JGE dest, JNL dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JGE/JNL]
Flags: the instruction has no effect on any flags.
Example:
CMP AX, 0030H; compares by subtracting 0030H from the value in AX regsiter
JGE LABEL1; jumps to the address specified by LABEL1 if value in register AX is more
positive or equal to the value 0030H
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jge-jnl[3/9/2019 9:18:08 PM]
JGE/JNL - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jge-jnl[3/9/2019 9:18:08 PM]
JGE/JNL - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jge-jnl[3/9/2019 9:18:08 PM]
JGE/JNL - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JL/JNGE - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JL/JNGE
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if less than/ Jump if not greater than or equal
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes CF to have value not equal to OF, else no
action is taken.
Usage: JL dest, JNGE dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JL/JNGE]
Flags: the instruction has no effect on any flags.
Example:
CMP AX, 0030H; compares by subtracting 0030H from the value in AX regsiter
JL LABEL1; jumps to the address specified by LABEL1 if value in register AX is more
negative than the value 0030H
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jl-jnge[3/9/2019 9:18:37 PM]
JL/JNGE - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jl-jnge[3/9/2019 9:18:37 PM]
JL/JNGE - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jl-jnge[3/9/2019 9:18:37 PM]
JL/JNGE - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap
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JLE/JNG - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JLE/JNG
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if less than or equal/ Jump if not greater than
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes either the ZF to have value equal to 1 or OF
to have value unequal to SF, else no action is taken.
Usage: JLE dest, JNG dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JLE/JNG]
Flags: the instruction has no effect on any flags.
Example:
CMP AX, 0030H; compares by subtracting 0030H from the value in AX regsiter
JLE LABEL1; jumps to the address specified by LABEL1 if value in register AX is more
negative than or equal to the value 0030H
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jle-jng[3/9/2019 9:19:04 PM]
JLE/JNG - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jle-jng[3/9/2019 9:19:04 PM]
JLE/JNG - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jle-jng[3/9/2019 9:19:04 PM]
JLE/JNG - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JMP - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JMP
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
Search this site
‎>‎
Jump
Description: Jumps to the destination label mentioned in the instruction. NEAR and SHORT
jumps cause the IP to be updated whereas the FAR jumps cause CS and IP to be updated.
Usage: JMP dest
[dest: address in the range of -32768 bytes to +32767 bytes from the address of instruction
after JMP]
Flags: the instruction has no effect on any flags.
Clocks and Size:
Operands
Clocks
8086
286
386
486
MUL
rel8 (relative)
15
7+m
7+m
3
NEG
rel16 (relative)
15
7+m
7+m
3
rel8 (relative)
-
-
7+m
3
11
7+m
7+m
5
-
-
7+m
5
18+EA
11+m
10+m
5
24+EA
15+m
10+m
5
-
-
12+m
17
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
reg16 (near,
register indirect)
reg32 (near,
register indirect)
mem16 (near,
register indirect)
mem32 (near,
register indirect)
ptr16:16 (far,
dword immed)
Logical XOR
RCL
RCR
Example:
ROL
JMP LABEL1; jumps to the address specified by LABEL1
ROR
SAR
SHL/SAL
Comments
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jmp[3/9/2019 9:19:31 PM]
JMP - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jmp[3/9/2019 9:19:31 PM]
JMP - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jmp[3/9/2019 9:19:31 PM]
JMP - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JNE/JNZ - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JNE/JNZ
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
Search this site
‎>‎
Jump if not equal/ Jump if not zero
Description: Jumps to the destination label mentioned in the instruction if the ZF is 0, else no
action is taken.
Usage: JNZ dest, JNE dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JNZ/JNE]
Flags: the instruction has no effect on any flags.
Example: JNZ LABEL1; jumps to the address specified by LABEL1 if ZF=0
Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jne-jnz[3/9/2019 9:20:05 PM]
JNE/JNZ - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jne-jnz[3/9/2019 9:20:05 PM]
JNE/JNZ - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jne-jnz[3/9/2019 9:20:05 PM]
JNE/JNZ - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JNO - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JNO
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if no overflow
Description: Jumps to the destination label mentioned in the instruction if the OF is 0, else
no action is taken. The overflow flag is set when a signed arithmetic operation produces a
result too large for the destination register or memory location to store.
Usage: JNO dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JNO]
Flags: the instruction has no effect on any flags.
Example: ADD AL,BL; add signed bytes in AL and BL
JNZ LABEL1; jumps to the address specified by LABEL1 if OF=0 after to the add
instruction above
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jno[3/9/2019 9:20:31 PM]
JNO - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jno[3/9/2019 9:20:31 PM]
JNO - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jno[3/9/2019 9:20:31 PM]
JNO - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JNP/JPO - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JNP/JPO
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if no parity/ Jump if parity odd
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes PF to have value equal to 0, else no action is
taken.
Usage: JNP dest, JPO dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JNP/JPO]
Flags: the instruction has no effect on any flags.
Example:
OR AX, AX;
Set flags
JNP LABEL1; even parity is expected, jumps to the address specified by LABEL1 if parity
is found to be odd
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jnp-jpo[3/9/2019 9:20:58 PM]
JNP/JPO - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jnp-jpo[3/9/2019 9:20:58 PM]
JNP/JPO - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jnp-jpo[3/9/2019 9:20:58 PM]
JNP/JPO - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JNS - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JNS
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if not signed (Jump if positive)
Description: Jumps to the destination label mentioned in the instruction if the SF is set, else
no action is taken. If the sign flag is 0 it indicates a positive signed number. Hence the
instruction causes a jump if the result of previous instruction is positive.
Usage: JNS dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JNS]
Flags: the instruction has no effect on any flags.
Example: ADD AL,BL; add signed bytes in AL and BL
JNS LABEL1; jumps to the address specified by LABEL1 if SF=0 due to the add
instruction above
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jns[3/9/2019 9:21:35 PM]
JNS - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jns[3/9/2019 9:21:35 PM]
JNS - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jns[3/9/2019 9:21:35 PM]
JNS - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JO - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JO
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if overflow
Description: Jumps to the destination label mentioned in the instruction if the OF is set, else
no action is taken. The overflow flag is set when a signed arithmetic operation produces a
result too large for the destination register or memory location to store.
Usage: JO dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JO]
Flags: the instruction has no effect on any flags.
Example: ADD AL,BL;
add signed bytes in AL and BL
JZ LABEL1; jumps to the address specified by LABEL1 if OF=1 due to the add instruction
above
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jo[3/9/2019 9:22:04 PM]
JO - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jo[3/9/2019 9:22:04 PM]
JO - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jo[3/9/2019 9:22:04 PM]
JO - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JP/JPE - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JP/JPE
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if parity/ Jump if parity even
Description: Jumps to the destination label mentioned in the instruction if the result of
previous instruction (generally compare) causes PF to have value equal to 1, else no action is
taken.
Usage: JP dest, JPE dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JP/JPE]
Flags: the instruction has no effect on any flags.
Example:
OR AX, AX; Set flags
JNP LABEL1;
odd parity is expected, jumps to the address specified by LABEL1 if parity
is found to be even
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jp-jpe[3/9/2019 9:22:34 PM]
JP/JPE - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jp-jpe[3/9/2019 9:22:34 PM]
JP/JPE - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jp-jpe[3/9/2019 9:22:34 PM]
JP/JPE - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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JS - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
JS
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Search this site
‎>‎
Jump if signed (Jump if negative)
Description: Jumps to the destination label mentioned in the instruction if the SF is 0, else no
action is taken. If the sign flag is 0 it indicates a positive signed number. Hence the
instruction causes a jump if the result of previous instruction is negative.
Usage: JS dest
[dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
JS]
Flags: the instruction has no effect on any flags.
Example: ADD AL,BL; add signed bytes in AL and BL
JS LABEL1; jumps to the address specified by LABEL1 if SF=1 due to the add instruction
above
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/js[3/9/2019 9:23:01 PM]
JS - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/js[3/9/2019 9:23:01 PM]
JS - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/js[3/9/2019 9:23:01 PM]
JS - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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LEAVE - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
LEAVE
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
‎>‎
Description: Releases the local variables created by the previous ENTER instruction by
restoring SP and BP to their condition before the procedure stack frame was initialized.
This instruction is available from 80188 onward.
Usage: LEAVE
Flags: the instruction has no effect on any flags.
Clocks and size:
Operands
Clocks
8086
none
MUL
Example:
NEG
LEAVE;
-
Size in Bytes
286
5
386
4
486
5
1
set SP/ESP to BP/EBP and then pop BP/EBP
SBB
SUB
XADD
Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/leave[3/9/2019 9:23:28 PM]
LEAVE - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/leave[3/9/2019 9:23:28 PM]
LEAVE - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/leave[3/9/2019 9:23:28 PM]
LEAVE - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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LOOP - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
LOOP
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
Description: Contents of CX register are decremented by 1 and if the new value in CX
register is non-zero, a jump is taken to the destination label mentioned in the instruction, else
no action is taken.
Usage: LOOP dest
[dest: addressin the range of -128 bytes to +127 bytes from the address of instruction after
LOOP]
Flags: the instruction has no effect on any flags.
Clocks and Size:
Operands
INC
jump is taken
MUL
jump is not
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
‎>‎
taken
Clocks
Size in Bytes
8086
286
386
486
18
8+m
11+m
6
2
5
4
?
2
2
Example:
LOOP LABEL1; jumps to the address specified by LABEL1 if value in register CX is nonzero after it has been decremented
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loop[3/9/2019 9:23:57 PM]
LOOP - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loop[3/9/2019 9:23:57 PM]
LOOP - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loop[3/9/2019 9:23:57 PM]
LOOP - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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LOOPE/LOOPZ - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
LOOPE/LOOPZ
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
Description: Contents of CX register are decremented by 1 and if the new value in CX
register is non-zero and the ZF is set, a jump is taken to the destination label mentioned in the
instruction, else no action is taken.
Usage: LOOPE dest, LOOPZ dest
[dest: addressin the range of -128 bytes to +127 bytes from the address of instruction after
LOOPE/LOOPZ]
Flags: the instruction has no effect on any flags.
Clocks and Size:
Operands
INC
jump is taken
MUL
jump is not
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
‎>‎
taken
Clocks
Size in Bytes
8086
286
386
486
18
8+m
11+m
9
2
5
4
?
6
2
Example:
LOOPE LABEL1; jumps to the address specified by LABEL1 if value in register CX is
non-zero after it has been decremented and ZF is set due to previous instruction
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loope-loopz[3/9/2019 9:24:29 PM]
LOOPE/LOOPZ - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loope-loopz[3/9/2019 9:24:29 PM]
LOOPE/LOOPZ - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loope-loopz[3/9/2019 9:24:29 PM]
LOOPE/LOOPZ - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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LOOPNE/LOOPNZ - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
LOOPNE/LOOPNZ
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
Description: Contents of CX register are decremented by 1 and if the new value in CX
register is non-zero and the ZF is 0, a jump is taken to the destination label mentioned in the
instruction, else no action is taken.
Usage: LOOPNE dest, LOOPNZ dest
[dest: addressin the range of -128 bytes to +127 bytes from the address of instruction after
LOOPNE/LOOPNZ]
Flags: the instruction has no effect on any flags.
Clocks and Size:
Operands
INC
jump is taken
MUL
jump is not
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
‎>‎
taken
Clocks
Size in Bytes
8086
286
386
486
19
8+m
11+m
9
2
5
4
?
6
2
Example:
LOOPNE LABEL1; jumps to the address specified by LABEL1 if value in register CX is
non-zero after it has been decremented and ZF is 0 due to previous instruction
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loopne-loopnz[3/9/2019 9:25:01 PM]
LOOPNE/LOOPNZ - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loopne-loopnz[3/9/2019 9:25:01 PM]
LOOPNE/LOOPNZ - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loopne-loopnz[3/9/2019 9:25:01 PM]
LOOPNE/LOOPNZ - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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TEST - Microprocessors@BITS
Microprocessors@BITS
Home
Program Execution Transfer Instructions
Arithmetic
Instructions
TEST
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
Search this site
‎>‎
DESCRIPTION:
Performs a logical AND of the two operands updating the flags
register without saving the result.
USAGE: TEST dest,src
FLAGS: CF OF PF SF ZF (AF undefined)
CLOCKS AND SIZES:
Operands
Clock Cycles
Size in bytes
8086
80286
80386
80486
5
2
2
1
IMUL
reg,reg
INC
mem,reg
9+EA
6
5
2 2-4
MUL
reg,mem
9+EA
6
5
2 2-4
mem,immed
11+EA
6
5
2 3-6
NEG
SBB
SUB
reg,immed
4
3
2
1 3-4
accum,mem
4
3
2
1 2-3
XADD
Bit Manipulation
Instructions
BSWAP
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/test[3/9/2019 9:25:39 PM]
2
TEST - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/test[3/9/2019 9:25:39 PM]
TEST - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/test[3/9/2019 9:25:39 PM]
TEST - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Stack Instructions - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
AAD
Stack Instructions
This section contains all instructions that are involved in manipulating stacks.
AAM
Subpage Listing
AAS
POP
ADC
POPA/POPAD
ADD
POPF/POPFD
CMP
PUSH
DAA
DAS
DEC
DIV
Search this site
PUSHA/PUSHAD
PUSHF/PUSHFD
RET
IDIV
IMUL
INC
MUL
NEG
SBB
Subpages (7): POP POPA/POPAD POPF/POPFD PUSH PUSHA/PUSHAD
PUSHF/PUSHFD RET
Comments
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions[3/9/2019 9:26:13 PM]
Stack Instructions - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/stack-instructions[3/9/2019 9:26:13 PM]
Stack Instructions - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/stack-instructions[3/9/2019 9:26:13 PM]
Stack Instructions - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Google Sites
POP - Microprocessors@BITS
Microprocessors@BITS
Home
Stack Instructions ‎ > ‎
Arithmetic
Instructions
POP
AAA
AAD
AAM
AAS
ADC
This instruction transfers the word at the current stack top (SS:SP) to the destination, and then
increments SP by two to point to the new stack top.
The POP CS instruction is illegal.
ADD
Usage POP Destination
CMP
Flags None
DAA
DAS
DEC
Search this site
Clocks and Size
Operands
Clocks
Size in Bytes
8086
286
386
486
reg16
8
5
4
4
1
IDIV
reg32
4
4
1
IMUL
segreg
8
1
DIV
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
mem16
17+EA
mem32
immed
5
7
3
5
5
6 2-4
5
-
6 2-4
-
3
2
Example
POP DS ; Copy a word from the top of the stack to DS and increment SP by 2.
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/pop[3/9/2019 9:26:44 PM]
1
POP - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/stack-instructions/pop[3/9/2019 9:26:44 PM]
POP - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/stack-instructions/pop[3/9/2019 9:26:44 PM]
POP - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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POPA/POPAD - Microprocessors@BITS
Microprocessors@BITS
Home
Stack Instructions ‎ > ‎
Arithmetic
Instructions
POPA/POPAD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
This instruction pops the top 8 words off the stack into the 8 general purpose 16/32 bit
registers. Registers are popped in the following order: (E)DI, (E)SI, (E)BP, (E)SP, (E)DX,
(E)CX and (E)AX.
The (E)SP value popped from the stack is actually discarded.
Usage POPA
POPAD (386+)
DAS
Flags None
DEC
Clocks and Size
DIV
IDIV
IMUL
Search this site
Operands
none
Clocks
Size in Bytes
8086
286
386
486
-
19
24
9
INC
MUL
NEG
SBB
Comments
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/popa[3/9/2019 9:27:19 PM]
1
POPA/POPAD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/stack-instructions/popa[3/9/2019 9:27:19 PM]
POPA/POPAD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/stack-instructions/popa[3/9/2019 9:27:19 PM]
POPA/POPAD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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POPF/POPFD - Microprocessors@BITS
Microprocessors@BITS
Home
Stack Instructions ‎ > ‎
Arithmetic
Instructions
POPF/POPFD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
Search this site
The POPF (POPFD) instruction pops a word (doubleword) from the stack into the Flags
Register and then increments SP by 2 (4).
Usage POPF
POPFD
Flags None
Clocks and Size
Operands
none/ (dest/src)
Clocks
Size in Bytes
8086
286
386
486
8/12
5
5
9
Comments
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/popf-popfd[3/9/2019 9:27:50 PM]
1
POPF/POPFD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/stack-instructions/popf-popfd[3/9/2019 9:27:50 PM]
POPF/POPFD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/stack-instructions/popf-popfd[3/9/2019 9:27:50 PM]
POPF/POPFD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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PUSH - Microprocessors@BITS
Microprocessors@BITS
Home
Stack Instructions ‎ > ‎
Arithmetic
Instructions
PUSH
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
Search this site
This instruction decrements SP by the size of the operand (two or four, byte values are sign
extended) and transfers one word from source to the stack top (SS:SP).
The source can be a general purpose register, a segment register, or memory. SS & SP must
be initialized before this instruction can be used.
Bytes cannot be pushed using this instruction, only words or doublewords.
Usage PUSH Source
Flags None
Clocks and Size
Operands
Clocks
8086
Size in Bytes
286
386
486
3
2
1
1
2
1
1
5
4 2-4
5
4 2-4
INC
reg16
11 - 15
reg32
-
MUL
mem16
16 + EA
NEG
mem32
-
segreg
10 - 14
3
2
3
immed
-
3
2
1 2-3
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
5
-
Example
PUSH BX ; Decrement SP by 2, copy BX to stack
Logical AND
Logical NOT
Comments
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/push[3/9/2019 9:28:24 PM]
1
PUSH - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/stack-instructions/push[3/9/2019 9:28:24 PM]
PUSH - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/stack-instructions/push[3/9/2019 9:28:24 PM]
PUSH - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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PUSHA/PUSHAD - Microprocessors@BITS
Microprocessors@BITS
Home
Stack Instructions ‎ > ‎
Arithmetic
Instructions
PUSHA/PUSHAD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
Pushes all general purpose registers onto the stack in the following order: (E)AX, (E)CX,
(E)DX, (E)BX, (E)SP, (E)BP, (E)SI, (E)DI. (The EAX etc. values are pushed when the
PUSHAD instruction is used.)
The value of SP pushed into the stack is its value before the actual push of SP.
Usage PUSHA
PUSHAD (386+)
DAS
Flags None
DEC
Clocks and Size
DIV
IDIV
IMUL
Search this site
Operands
none
Clocks
Size in Bytes
8086
286
386
486
-
19
24
11
INC
MUL
Comments
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/pusha[3/9/2019 9:28:58 PM]
1
PUSHA/PUSHAD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/stack-instructions/pusha[3/9/2019 9:28:58 PM]
PUSHA/PUSHAD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/stack-instructions/pusha[3/9/2019 9:28:58 PM]
PUSHA/PUSHAD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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PUSHF/PUSHFD - Microprocessors@BITS
Microprocessors@BITS
Home
Stack Instructions ‎ > ‎
Arithmetic
Instructions
PUSHF/PUSHFD
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
Search this site
This instruction transfers the Flags Register onto the stack. PUSHF saves a 16 bit value
while PUSHFD saves a 32 bit value.
The stack pointer is decremented by 2.
Usage PUSHF
PUSHFD
Flags None
Clocks and Size
Operands
none/ (dest/src)
Clocks
Size in Bytes
8086
286
386
486
10-14
3
4
4
IMUL
INC
MUL
Comments
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/pushf[3/9/2019 9:29:29 PM]
1
PUSHF/PUSHFD - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/stack-instructions/pushf[3/9/2019 9:29:29 PM]
PUSHF/PUSHFD - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/stack-instructions/pushf[3/9/2019 9:29:29 PM]
PUSHF/PUSHFD - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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RET - Microprocessors@BITS
Microprocessors@BITS
Home
Stack Instructions ‎ > ‎
Arithmetic
Instructions
RET
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
Search this site
DESCRIPTION:
Transfers control from a procedure back to the instruction addre
saved on the stack. "n bytes" is an optional number of bytes to
release. Far returns pop the IP followed by the CS, while near
returns pop only the IP register.
USAGE:
RET nBytes
RETF nBytes
RETN nBytes
FLAGS:NONE
CLOCKS AND SIZES:
Operands
Clock Cycles
8086
80286
Size in bytes
80386
80486
SBB
retn
16/20
11+m
10+m
5
1
retn immed
20/24
11+m
10+m
5
3
SUB
retf
26/34
15+m
18+m
13
1
XADD
retf immed
25/33
15+m
18+m
14
3
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/ret[3/9/2019 9:30:00 PM]
RET - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/stack-instructions/ret[3/9/2019 9:30:00 PM]
RET - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/stack-instructions/ret[3/9/2019 9:30:00 PM]
RET - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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String Instructions - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
AAD
AAM
String Instructions
This section describes the various string-related operations that are supported by the
Intel x86 family.
AAS
Subpage Listing
ADC
CMPS/CMPSB/CMPSW
ADD
INS/INSB/INSW
CMP
LODS/LODSB/LODSW
DAA
MOVS/MOVSB/MOVSW
DAS
DEC
DIV
IDIV
IMUL
INC
Search this site
OUTS/OUTSB/OUTSW
REP
REPE/REPNE/REPZ/REPNZ
SCAS/SCASB/SCASW
STOS/STOSB/STOSW
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
Subpages (9): CMPS/CMPSB/CMPSW INS/INSB/INSW LODS/LODSB/LODSW
MOVS/MOVSB/MOVSW OUTS/OUTSB/OUTSW REP
REPE/REPNE/REPZ/REPNZ SCAS/SCASB/SCASW STOS/STOSB/STOSW
Comments
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions[3/9/2019 9:30:35 PM]
String Instructions - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions[3/9/2019 9:30:35 PM]
String Instructions - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions[3/9/2019 9:30:35 PM]
String Instructions - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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CMPS/CMPSB/CMPSW - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
String Instructions ‎ > ‎
Arithmetic
Instructions
CMPS/CMPSB/CMPSW
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
The CMPSB(W) instruction can be used to compare a byte(word) in one string (DS:offset in
SI) with a byte (word) in another string (ES:offset in DI). The comparison is executed by
subtracting the byte (word) in DI from the byte (word) in SI.
The Direction Flag (DF) value determines whether SI and DI are to be incremented (DF =
0) or decremented (DF = 1) after each move. Increments/decrements happen by 1 for byte
strings and by 2 for word strings.
The CMPSB(W) instruction is almost always used
with a REP(E/Z) prefix to compare
multiple words/bytes.
The result of the comparison can be gleaned from flag updates.
Usage CMPS src, dest
CMPSB
CMPSW
Flags AF,CF,OF,PF,SF,ZF
Clocks and Size
Operands
Clocks
Size in Bytes
8086
286
386
486
22
8
10
8
none/ (dest/src)
1
Logical OR
Logical XOR
Example
RCL
RCR
Compare, till a difference is found, two data items of 100 bytes each
at STR1 and STR2
ROL
ROR
MOV SI, STR1
SAR
MOV DI, STR2
SHL/SAL
MOV CX, 100
SHR
CLD; Clear the direction flag
https://sites.google.com/site/microprocessorsbits/string-instructions/cmps-cmpsb-cmpsw[3/9/2019 9:31:07 PM]
CMPS/CMPSB/CMPSW - Microprocessors@BITS
SHRD/SHLD
Data Transfer
REPE CMPSB
CMPXCHG
LAHF
LAR
LDS/LES
Comments
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions/cmps-cmpsb-cmpsw[3/9/2019 9:31:07 PM]
CMPS/CMPSB/CMPSW - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions/cmps-cmpsb-cmpsw[3/9/2019 9:31:07 PM]
CMPS/CMPSB/CMPSW - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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INS/INSB/INSW - Microprocessors@BITS
Microprocessors@BITS
Home
String Instructions ‎ > ‎
Arithmetic
Instructions
INS/INSB/INSW
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
Search this site
Loads data from a port to the destination [ES:DI]. DI is incremented or decremented
depending on the value of DF.
Usage INS dest, port
INSB
INSW
Flags None
Clocks and Size
Operands
dest,port
Clocks
Size in Bytes
8086
286
386
486
Not Implemented
5
15
17
MUL
NEG
SBB
Example
Move a word from <port address> to STR
SUB
XADD
Bit Manipulation
Instructions
BSWAP
MOV DX, <port address>
MOV DI, offset STR
INSW
Logical AND
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/ins-insb-insw[3/9/2019 9:31:39 PM]
1
INS/INSB/INSW - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions/ins-insb-insw[3/9/2019 9:31:39 PM]
INS/INSB/INSW - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions/ins-insb-insw[3/9/2019 9:31:39 PM]
INS/INSB/INSW - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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LODS/LODSB/LODSW - Microprocessors@BITS
Microprocessors@BITS
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Home
String Instructions ‎ > ‎
Arithmetic
Instructions
LODS/LODSB/LODSW
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
This instruction copies a byte (word) of string from the location pointed to by SI. The SI
value is automatically incremented (depending on the DF value) after each movement by 1
byte (2 bytes) for a byte string (word string).
This instruction is preferred over MOV for string manipulation due to its treatment of the
SI pointer and the ability to use it with REP prefixes.
Usage LODS <String>
LODSB
LODSW
Flags None
Clocks and Size
Operands
none/ (dest/src)
Clocks
Size in Bytes
8086
286
386
486
12/16
5
5
5
XADD
Bit Manipulation
Instructions
Example
CLD
BSWAP
MOV SI, Offset STR
Logical AND
LODSB
Logical NOT
Logical OR
Logical XOR
Comments
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/lods-lodsb-lodsw[3/9/2019 9:32:13 PM]
1
LODS/LODSB/LODSW - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions/lods-lodsb-lodsw[3/9/2019 9:32:13 PM]
LODS/LODSB/LODSW - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions/lods-lodsb-lodsw[3/9/2019 9:32:13 PM]
LODS/LODSB/LODSW - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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MOVS/MOVSB/MOVSW - Microprocessors@BITS
Microprocessors@BITS
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Home
String Instructions ‎ > ‎
Arithmetic
Instructions
MOVS/MOVSB/MOVSW
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
This instruction copies a byte or a word from a location in the data segment
location in the extra segment [ES:DI]. The offset in the data segment for the source is to be
stored in the SI register and the offset for the destination in the extra segment is to be stored
in the DI register.
For multiple byte/word movement, the value stored in the CX register by the user functions as
a counter. After each move, SI and DI are automatically adjusted to point to the next source
and destination respectively.
The Direction Flag (DF) value determines whether SI and DI are to be incremented (DF =
0) or decremented (DF = 1) after each move.
The MOVSB instruction tells the assembler to move data as bytes; the MOVSW implies the
string is to be moved as words.
Usage MOVS dest, src (This usage is misleading; movement of data still happens from
DS:SI to ES:DI)
MOVSB
MOVSW
Flags None
Clocks and Size
Operands
none/ (dest/src)
Clocks
Size in Bytes
8086
286
386
486
18
5
7
7
ROL
ROR
Example
SAR
SHL/SAL
[DS:SI] to
To move a string of length 4 bytes from SRC to DST
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/movs-movsb-movsw[3/9/2019 9:32:45 PM]
1
MOVS/MOVSB/MOVSW - Microprocessors@BITS
SHRD/SHLD
MOV SI, SRC
Data Transfer
MOV DI, DST
CMPXCHG
MOV CX, 04H
LAHF
CLD; Clear the direction flag
LAR
LDS/LES
REP MOVSB
LEA
MOV
MOVS
Comments
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions/movs-movsb-movsw[3/9/2019 9:32:45 PM]
MOVS/MOVSB/MOVSW - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions/movs-movsb-movsw[3/9/2019 9:32:45 PM]
MOVS/MOVSB/MOVSW - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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OUTS/OUTSB/OUTSW - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
String Instructions ‎ > ‎
Arithmetic
Instructions
OUTS/OUTSB/OUTSW
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
Transfers a data byte/word from
[DS:SI] to a port specified in the
incremented/decremented depending on the value of the DF.
DX register. SI is
Usage OUTS port, src
OUTSB
OUTSW
Flags None
Clocks and Size
Operands
string
Clocks
Size in Bytes
8086
286
386
486
Not implmented
5
14
17
MUL
NEG
SBB
Example
Move a byte from STR to the port PORT
SUB
XADD
Bit Manipulation
Instructions
BSWAP
MOV SI, offset STR
MOV DX, <addr. PORT>
OUTSB
Logical AND
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/outs-outsb-outsw[3/9/2019 9:33:20 PM]
1
OUTS/OUTSB/OUTSW - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions/outs-outsb-outsw[3/9/2019 9:33:20 PM]
OUTS/OUTSB/OUTSW - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions/outs-outsb-outsw[3/9/2019 9:33:20 PM]
OUTS/OUTSB/OUTSW - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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REP - Microprocessors@BITS
Microprocessors@BITS
Home
String Instructions ‎ > ‎
Arithmetic
Instructions
REP
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
Search this site
REP is a prefix written before one of the string instructions. It is used for repeating an
instruction count number of times, where count is stored in the CX register. After every
operation the CX register is decremented and the zero flag is tested; the process continues till
CX = 0.
Usage REP <String-Instruction>
Flags Depend on String instruction used
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
2
2
2
1
MUL
NEG
Example
SBB
SUB
REP MOVSB
XADD
(Should be preceded with a MOV CX, count instruction somewhere in the code.)
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Comments
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/rep[3/9/2019 9:33:56 PM]
1
REP - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions/rep[3/9/2019 9:33:56 PM]
REP - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions/rep[3/9/2019 9:33:56 PM]
REP - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Google Sites
REPE/REPNE/REPZ/REPNZ - Microprocessors@BITS
Microprocessors@BITS
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Home
String Instructions ‎ > ‎
Arithmetic
Instructions
REPE/REPNE/REPZ/REPNZ
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
REPE and REPZ are mnemonics for the same prefix; they stand for Repeat if Equal and
Repeat if Zero respectively. REPE/REPZ causes the succeeding string instruction to be
repeated as long as the comapred bytes or words are equal (ZF = 1) and CX is not yet
counted down to zero.
The REPNE and the REPNZ instructions stand for Repeat if Not Equal and Repeat if Not
Zero respectively and cause the string instruction to be repeated until the compared bytes or
words are equal (ZF = 1) or until CX = 0 (end of string.)
CX is decremented and the zero flag is tested after each operation.
Usage REPE/REPE/REPZ/REPNZ <String Instruction>
Flags Depend on string instruction used
Clocks and Size
Operands
none
Clocks
Size in Bytes
8086
286
386
486
2
2
2
1
BSWAP
Example
Logical AND
Logical NOT
REPNE SCASW
Scans a string of words (i.e. repeats SCASW) until a word in the string matches the word in
Logical OR
AX (as dictated by the SCASW instruction) or until all of the string has been scanned.
Logical XOR
RCL
RCR
Comments
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/repe-repne-repz-repnz[3/9/2019 9:34:31 PM]
1
REPE/REPNE/REPZ/REPNZ - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions/repe-repne-repz-repnz[3/9/2019 9:34:31 PM]
REPE/REPNE/REPZ/REPNZ - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions/repe-repne-repz-repnz[3/9/2019 9:34:31 PM]
REPE/REPNE/REPZ/REPNZ - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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SCAS/SCASB/SCASW - Microprocessors@BITS
Microprocessors@BITS
Search this site
Home
String Instructions ‎ > ‎
Arithmetic
Instructions
SCAS/SCASB/SCASW
AAA
AAD
AAM
AAS
ADC
ADD
CMP
SCAS(/B/W) compares a byte in AL or a word in AX with a byte or word pointed to by DI
in ES. The direction flag determines the direction of scan.
Used with the REP prefix to find the first occurrence of a specified byte(word) in a string.
Usage SCAS <String>
SCASB
DAA
SCASW
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
Flags AF,PF,OF,PF,SF,ZF
Clocks and Size
Operands
string
Clocks
Size in Bytes
8086
286
386
486
15
7
7
6
NEG
SBB
SUB
Example
Scan a string STR of 100 characters for the 'space' character, 20H
XADD
Bit Manipulation
Instructions
MOV CX, 100
MOV DI, offset STR
BSWAP
MOV AL, 20H
Logical AND
REPNE SCASB
Logical NOT
Logical OR
Logical XOR
Comments
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/scas-scasb-scasw[3/9/2019 9:35:07 PM]
1
SCAS/SCASB/SCASW - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions/scas-scasb-scasw[3/9/2019 9:35:07 PM]
SCAS/SCASB/SCASW - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions/scas-scasb-scasw[3/9/2019 9:35:07 PM]
SCAS/SCASB/SCASW - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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STOS/STOSB/STOSW - Microprocessors@BITS
Microprocessors@BITS
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String Instructions ‎ > ‎
Arithmetic
Instructions
STOS/STOSB/STOSW
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
The STOS instruction
copies a byte (word) from AL (AX) to a memory location stored in
[ES:DI]. DI is automatically incremented after the copy, the DF determines the
increment/decrement.
In effect, it replaces a string element with a byte (word) from AL (AX).
Usage STOS <String>
STOSB
DEC
STOSW
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
Flags None
Clocks and Size
Operands
string
Clocks
Size in Bytes
8086
286
386
486
11
3
4
5
SUB
XADD
Bit Manipulation
Instructions
Example
Copy AX to STR
BSWAP
MOV DI, offset STR
Logical AND
STOSW
Logical NOT
Logical OR
Logical XOR
Comments
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/stos-stosb-stosw[3/9/2019 9:35:37 PM]
1
STOS/STOSB/STOSW - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/string-instructions/stos-stosb-stosw[3/9/2019 9:35:37 PM]
STOS/STOSB/STOSW - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/string-instructions/stos-stosb-stosw[3/9/2019 9:35:37 PM]
STOS/STOSB/STOSW - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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AAA
AAD
AAM
AAS
ADC
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Microprocessors@BITS
Arithmetic Instructions
Bit Manipulation Instructions
ADD
Data Transfer
CMP
Home
DAA
Miscellaneous
DAS
Processor Control Instructions
DEC
Program Execution Transfer Instructions
DIV
Stack Instructions
IDIV
String Instructions
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
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SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
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ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
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CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Arithmetic
Instructions
AAA
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Jul 10, 2015, 12:56 PM
K.R. Anupama edited Logical AND
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Jan 23, 2014, 10:20 PM
pratik gangwal edited CALL
Jan 23, 2014, 10:08 PM
pratik gangwal created CALL
ADC
Jan 20, 2014, 3:59 PM
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ADD
Jan 20, 2014, 3:57 PM
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CMP
Jan 20, 2014, 3:51 PM
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DAA
Jan 20, 2014, 3:49 PM
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DAS
Jan 20, 2014, 3:26 PM
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DEC
Jan 20, 2014, 3:23 PM
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DIV
Jan 20, 2014, 3:18 PM
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IDIV
Jan 20, 2014, 3:09 PM
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IMUL
Jan 20, 2014, 2:49 PM
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INC
Jan 20, 2014, 2:44 PM
pratik gangwal created LAR
Jan 20, 2014, 2:40 PM
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AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
Search this site
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RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
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SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
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Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
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Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
Search this site
Home
AAA
Clock
AAD
8:46 PM
AAM
AAS
Jun 27, 51155 (Mon)
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
Copyright
The Instruction Set Dictionary is subject to copyright protection and may be used
only for private study by persons who are enrolled in this course. Any other use of
these materials must be with the express, written permission of any of the course
instructors from Goa campus
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/home[3/9/2019 9:40:22 PM]
Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
https://sites.google.com/site/microprocessorsbits/home[3/9/2019 9:40:22 PM]
Microprocessors@BITS
Program
Execution
Transfer
Instructions
CALL
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
…
https://sites.google.com/site/microprocessorsbits/home[3/9/2019 9:40:22 PM]
Microprocessors@BITS
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Subpages
AAA
Item
AAD
CALL
AAM
ENTER
AAS
INT
ADC
INTO
ADD
IRET
CMP
JAE/JNB
DAA
JA/JNBE
DAS
JBE/JNA
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
JB/JNAE/JC
JC
JCXZ
JE/JZ
JGE/JNL
JG/JNLE
JLE/JNG
JL/JNGE
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
Logical XOR
LOOP
RCL
LOOPE/LOOPZ
RCR
LOOPNE/LOOPNZ
ROL
TEST
ROR
SAR
Search this site
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SHL/SAL
SHR
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Subpages - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
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Subpages - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
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CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
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STOS/STOS…
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AAA
AAD
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AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
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SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
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ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
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CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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AAA
AAD
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AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
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SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
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ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/...icroprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:4ffcb698fc30ed64[3/9/2019 9:42:01 PM]
Page not found - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
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STOS/STOS…
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AAA
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Jan 20, 2014, 9:20 AM
Rohit Sant edited Bit Manipulation Instructions
Jan 20, 2014, 9:19 AM
Rohit Sant edited Arithmetic Instructions
Jan 20, 2014, 9:18 AM
Rohit Sant edited BT
Jan 20, 2014, 9:13 AM
Rohit Sant created BT
ADC
Jan 20, 2014, 9:11 AM
Rohit Sant edited MOVZX
ADD
Jan 20, 2014, 9:07 AM
Rohit Sant created MOVZX
CMP
Jan 20, 2014, 9:07 AM
Rohit Sant edited MOV
DAA
Jan 20, 2014, 9:06 AM
Rohit Sant edited LAHF
DAS
Jan 20, 2014, 9:02 AM
Rohit Sant created LAHF
DEC
Jan 20, 2014, 12:45 AM
shridevi muthkhod edited JMP
DIV
Jan 20, 2014, 12:39 AM
pratik gangwal created RET
IDIV
Jan 20, 2014, 12:34 AM
pratik gangwal edited SAHF
IMUL
Jan 20, 2014, 12:29 AM
pratik gangwal created SAHF
INC
Jan 19, 2014, 11:46 PM
shridevi muthkhod edited JMP
Jan 19, 2014, 11:40 PM
shridevi muthkhod created JMP
Jan 19, 2014, 11:39 PM
shridevi muthkhod edited LOOPNE/LOOPNZ
Jan 19, 2014, 11:38 PM
shridevi muthkhod edited LOOPE/LOOPZ
Jan 19, 2014, 11:36 PM
shridevi muthkhod edited LOOP
Jan 19, 2014, 11:32 PM
shridevi muthkhod edited JC
Jan 19, 2014, 11:29 PM
shridevi muthkhod edited JA/JNBE
Jan 19, 2014, 11:22 PM
shridevi muthkhod edited ENTER
Jan 19, 2014, 11:21 PM
shridevi muthkhod edited ENTER
Jan 19, 2014, 11:20 PM
shridevi muthkhod edited LEAVE
Jan 19, 2014, 11:08 PM
shridevi muthkhod edited LEAVE
Jan 19, 2014, 11:04 PM
shridevi muthkhod created LEAVE
AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
Search this site
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RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=25[3/9/2019 9:42:33 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=25[3/9/2019 9:42:33 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=25[3/9/2019 9:42:33 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Recent site activity - Microprocessors@BITS
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AAA
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Jan 16, 2014, 5:26 PM
Rohit Sant edited CLI
Jan 16, 2014, 5:23 PM
Rohit Sant created CLI
Jan 16, 2014, 5:23 PM
Rohit Sant edited CLD
Jan 16, 2014, 5:20 PM
Rohit Sant created CLD
ADC
Jan 16, 2014, 5:19 PM
Rohit Sant edited CLC
ADD
Jan 16, 2014, 5:18 PM
Rohit Sant created CLC
CMP
Jan 16, 2014, 5:17 PM
Rohit Sant edited STD
DAA
Jan 16, 2014, 5:17 PM
Rohit Sant deleted STD
DAS
Jan 16, 2014, 5:16 PM
Rohit Sant edited STI
DEC
Jan 16, 2014, 5:15 PM
Rohit Sant edited STI
DIV
Jan 16, 2014, 5:10 PM
Rohit Sant created STI
IDIV
Jan 16, 2014, 5:10 PM
Rohit Sant edited STD
IMUL
Jan 16, 2014, 5:07 PM
Rohit Sant created STD
INC
Jan 16, 2014, 5:07 PM
Rohit Sant created STD
Jan 16, 2014, 5:06 PM
Rohit Sant edited STC
Jan 16, 2014, 5:04 PM
Rohit Sant created STC
Jan 16, 2014, 5:03 PM
Rohit Sant created Processor Control Instructions
Jan 15, 2014, 10:08 PM
shridevi muthkhod edited Program Execution Transfer Instructions
Jan 15, 2014, 9:47 PM
shridevi muthkhod created Program Execution Transfer Instructions
Jan 15, 2014, 6:52 PM
Rohit Sant edited POPF/POPFD
Jan 15, 2014, 6:49 PM
Rohit Sant created POPF/POPFD
Jan 15, 2014, 6:49 PM
Rohit Sant edited PUSHF/PUSHFD
Jan 15, 2014, 6:45 PM
Rohit Sant created PUSHF
Jan 15, 2014, 6:43 PM
Rohit Sant edited POPA/POPAD
Jan 15, 2014, 6:35 PM
Rohit Sant edited PUSHA/PUSHAD
AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
older | newer
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=150[3/9/2019 9:47:31 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=150[3/9/2019 9:47:31 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=150[3/9/2019 9:47:31 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
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AAD
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AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/...roprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:788a7168d4310f8e[3/9/2019 9:47:59 PM]
Page not found - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/...roprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:788a7168d4310f8e[3/9/2019 9:47:59 PM]
Page not found - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/...roprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:788a7168d4310f8e[3/9/2019 9:47:59 PM]
Page not found - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
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STOS/STOS…
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Microprocessors@BITS
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AAA
Recent site activity
Jan 15, 2014, 6:34 PM
Rohit Sant edited PUSHA/PUSHAD
Jan 15, 2014, 6:33 PM
Rohit Sant edited POPA
Jan 15, 2014, 6:28 PM
Rohit Sant created POPA
Jan 15, 2014, 6:27 PM
Rohit Sant edited PUSHA
ADC
Jan 15, 2014, 6:23 PM
Rohit Sant created PUSHA
ADD
Jan 15, 2014, 6:21 PM
Rohit Sant edited POP
CMP
Jan 15, 2014, 6:15 PM
Rohit Sant created POP
DAA
Jan 15, 2014, 6:14 PM
Rohit Sant edited PUSH
DAS
Jan 15, 2014, 6:05 PM
Rohit Sant created PUSH
DEC
Jan 15, 2014, 6:02 PM
Rohit Sant edited Stack Instructions
DIV
Jan 15, 2014, 6:02 PM
Rohit Sant created Stack Instructions
IDIV
Jan 13, 2014, 5:43 PM
Rohit Sant edited CWD
IMUL
Jan 13, 2014, 5:39 PM
Rohit Sant edited CWD
INC
Jan 13, 2014, 5:35 PM
Rohit Sant created CWD
Jan 13, 2014, 5:35 PM
Rohit Sant edited CBW
Jan 13, 2014, 5:34 PM
Rohit Sant edited CBW
Jan 13, 2014, 4:58 PM
Rohit Sant edited CBW
Jan 13, 2014, 4:52 PM
Rohit Sant created CBW
Jan 13, 2014, 4:51 PM
Rohit Sant edited Miscellaneous
Jan 13, 2014, 4:49 PM
Rohit Sant created Miscellaneous
Jan 13, 2014, 4:48 PM
Rohit Sant edited AAD
Jan 13, 2014, 4:42 PM
Rohit Sant edited AAM
Jan 13, 2014, 4:25 PM
Rohit Sant created AAD
Jan 13, 2014, 4:25 PM
Rohit Sant edited IDIV
Jan 13, 2014, 2:18 PM
Rohit Sant edited IDIV
AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
Search this site
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RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=175[3/9/2019 9:48:26 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=175[3/9/2019 9:48:26 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=175[3/9/2019 9:48:26 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
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REP
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Jan 13, 2014, 2:06 PM
Rohit Sant created IDIV
Jan 13, 2014, 11:17 AM
Rohit Sant edited DIV
Jan 13, 2014, 11:01 AM
Rohit Sant created DIV
Jan 13, 2014, 10:59 AM
Rohit Sant edited AAM
ADC
Jan 12, 2014, 11:45 AM
pratik gangwal edited DAS
ADD
Jan 12, 2014, 11:41 AM
pratik gangwal edited DAS
CMP
Jan 12, 2014, 11:38 AM
pratik gangwal edited DAS
DAA
Jan 12, 2014, 11:38 AM
pratik gangwal created DAS
DAS
Jan 12, 2014, 11:36 AM
pratik gangwal edited AAS
DEC
Jan 12, 2014, 11:31 AM
pratik gangwal edited AAS
DIV
Jan 12, 2014, 11:27 AM
pratik gangwal created AAS
IDIV
Jan 12, 2014, 11:26 AM
pratik gangwal edited DEC
IMUL
Jan 12, 2014, 11:26 AM
pratik gangwal edited DAA
INC
Jan 12, 2014, 11:24 AM
pratik gangwal edited DEC
Jan 12, 2014, 11:23 AM
pratik gangwal edited DEC
Jan 12, 2014, 11:22 AM
pratik gangwal edited DEC
Jan 12, 2014, 11:22 AM
pratik gangwal edited DEC
Jan 12, 2014, 11:21 AM
pratik gangwal created DEC
Jan 12, 2014, 11:20 AM
pratik gangwal edited CMP
Jan 12, 2014, 11:08 AM
pratik gangwal created DAA
Jan 12, 2014, 11:07 AM
pratik gangwal edited AAA
Jan 12, 2014, 10:54 AM
pratik gangwal created AAA
Jan 12, 2014, 10:53 AM
pratik gangwal edited SUB
Jan 12, 2014, 10:45 AM
pratik gangwal created SUB
Jan 12, 2014, 10:40 AM
pratik gangwal edited INC
AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
Search this site
older | newer
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=200[3/9/2019 9:48:53 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=200[3/9/2019 9:48:53 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=200[3/9/2019 9:48:53 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
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STOS/STOS…
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AAA
Recent site activity
Jan 12, 2014, 10:34 AM
pratik gangwal edited SBB
Jan 12, 2014, 10:32 AM
pratik gangwal edited SBB
Jan 12, 2014, 10:30 AM
pratik gangwal edited CMP
Jan 12, 2014, 10:26 AM
pratik gangwal created INC
ADC
Jan 12, 2014, 10:25 AM
pratik gangwal edited ADC
ADD
Jan 12, 2014, 10:20 AM
pratik gangwal created ADC
CMP
Jan 12, 2014, 10:16 AM
pratik gangwal edited SBB
DAA
Jan 12, 2014, 10:16 AM
pratik gangwal edited ADD
DAS
Jan 12, 2014, 10:16 AM
pratik gangwal edited NEG
DEC
Jan 12, 2014, 10:16 AM
pratik gangwal edited CMP
DIV
Jan 12, 2014, 10:14 AM
pratik gangwal created CMP
IDIV
Jan 12, 2014, 10:13 AM
pratik gangwal edited SBB
IMUL
Jan 12, 2014, 10:13 AM
pratik gangwal edited NEG
INC
Jan 12, 2014, 10:13 AM
pratik gangwal edited NEG
Jan 12, 2014, 10:10 AM
pratik gangwal edited NEG
Jan 12, 2014, 10:06 AM
pratik gangwal created NEG
Jan 12, 2014, 10:03 AM
pratik gangwal edited SBB
Jan 12, 2014, 9:49 AM
pratik gangwal edited SBB
Jan 12, 2014, 9:45 AM
pratik gangwal created SBB
Jan 11, 2014, 5:43 PM
pratik gangwal created ADD
Jan 10, 2014, 9:09 PM
Rohit Sant edited AAM
Jan 10, 2014, 8:11 PM
Rohit Sant created AAM
Jan 10, 2014, 7:50 PM
Rohit Sant edited IMUL
Jan 10, 2014, 7:35 PM
Rohit Sant created IMUL
Jan 10, 2014, 7:34 PM
Rohit Sant edited MUL
AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
Search this site
older | newer
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=225[3/9/2019 9:49:19 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=225[3/9/2019 9:49:19 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=225[3/9/2019 9:49:19 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Recent site activity - Microprocessors@BITS
Microprocessors@BITS
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Arithmetic
Instructions
AAA
Recent site activity
Jan 10, 2014, 7:11 PM
Rohit Sant created MUL
Jan 10, 2014, 7:07 PM
Rohit Sant edited OUTS/OUTSB/OUTSW
Jan 10, 2014, 5:53 PM
Rohit Sant edited OUTS/OUTSB/OUTSW
Jan 10, 2014, 5:44 PM
Rohit Sant created OUTS/OUTSB/OUTSW
ADC
Jan 10, 2014, 5:42 PM
Rohit Sant edited INS/INSB/INSW
ADD
Jan 10, 2014, 5:18 PM
Rohit Sant created INS/INSB/INSW
CMP
Jan 9, 2014, 7:13 PM
Rohit Sant edited STOS/STOSB/STOSW
DAA
Jan 9, 2014, 6:00 PM
Rohit Sant created STOS/STOSB/STOSW
DAS
Jan 9, 2014, 5:56 PM
Rohit Sant edited LODS/LODSB/LODSW
DEC
Jan 9, 2014, 5:36 PM
Rohit Sant created LODS/LODSB/LODSW
DIV
Jan 9, 2014, 5:35 PM
Rohit Sant edited SCAS/SCASB/SCASW
IDIV
Jan 9, 2014, 5:35 PM
Rohit Sant edited SCAS/SCASB/SCASW
IMUL
Jan 9, 2014, 5:18 PM
pratik gangwal edited RCL
INC
Jan 9, 2014, 5:18 PM
pratik gangwal edited RCR
Jan 9, 2014, 5:17 PM
pratik gangwal edited RCR
Jan 9, 2014, 5:14 PM
pratik gangwal edited RCR
Jan 9, 2014, 5:13 PM
pratik gangwal created RCR
Jan 9, 2014, 5:12 PM
pratik gangwal edited RCL
Jan 9, 2014, 5:07 PM
Rohit Sant created SCAS/SCASB/SCASW
Jan 9, 2014, 4:51 PM
pratik gangwal created RCL
Jan 9, 2014, 4:48 PM
pratik gangwal edited ROL
Jan 9, 2014, 4:48 PM
pratik gangwal edited ROR
Jan 9, 2014, 4:47 PM
pratik gangwal edited ROR
Jan 9, 2014, 4:46 PM
pratik gangwal edited ROR
Jan 9, 2014, 4:42 PM
pratik gangwal created ROR
AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
Search this site
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RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=250[3/9/2019 9:49:46 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=250[3/9/2019 9:49:46 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=250[3/9/2019 9:49:46 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Recent site activity - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
Recent site activity
Jan 9, 2014, 4:06 PM
pratik gangwal edited SHL/SAL
Jan 9, 2014, 4:05 PM
pratik gangwal edited ROL
Jan 9, 2014, 4:04 PM
pratik gangwal edited SHL/SAL
Jan 9, 2014, 4:01 PM
pratik gangwal edited ROL
ADC
Jan 9, 2014, 3:58 PM
pratik gangwal edited SAR
ADD
Jan 9, 2014, 3:58 PM
pratik gangwal edited ROL
CMP
Jan 9, 2014, 3:56 PM
pratik gangwal created SHL/SAL
DAA
Jan 9, 2014, 3:55 PM
pratik gangwal created ROL
DAS
Jan 9, 2014, 3:52 PM
pratik gangwal edited Logical XOR
DEC
Jan 9, 2014, 3:52 PM
pratik gangwal edited SAR
DIV
Jan 9, 2014, 3:51 PM
pratik gangwal edited SAR
IDIV
Jan 9, 2014, 3:44 PM
pratik gangwal created Logical XOR
IMUL
Jan 9, 2014, 3:39 PM
pratik gangwal edited SHR
INC
Jan 9, 2014, 3:38 PM
pratik gangwal created SAR
Jan 9, 2014, 3:38 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:37 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:36 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:36 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:35 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:35 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:30 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:29 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:29 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:28 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:19 PM
pratik gangwal edited Logical OR
AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
Search this site
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RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=275[3/9/2019 9:50:13 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=275[3/9/2019 9:50:13 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=275[3/9/2019 9:50:13 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Recent site activity - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
Recent site activity
Jan 9, 2014, 3:16 PM
pratik gangwal edited SHR
Jan 9, 2014, 3:12 PM
pratik gangwal created SHR
Jan 9, 2014, 3:10 PM
pratik gangwal edited Logical OR
Jan 9, 2014, 3:10 PM
pratik gangwal created Logical OR
ADC
Jan 9, 2014, 3:03 PM
pratik gangwal edited Logical NOT
ADD
Jan 9, 2014, 2:50 PM
pratik gangwal edited Logical AND
CMP
Jan 9, 2014, 2:49 PM
pratik gangwal edited Logical AND
DAA
Jan 9, 2014, 2:43 PM
pratik gangwal edited Logical AND
DAS
Jan 9, 2014, 2:25 PM
pratik gangwal created Logical AND
DEC
Jan 9, 2014, 2:24 PM
pratik gangwal edited Logical NOT
DIV
Jan 9, 2014, 2:22 PM
pratik gangwal edited Logical NOT
IDIV
Jan 9, 2014, 9:55 AM
pratik gangwal created Logical NOT
IMUL
Jan 9, 2014, 9:47 AM
pratik gangwal edited Bit Manipulation Instructions
INC
Jan 9, 2014, 9:41 AM
pratik gangwal created Bit Manipulation Instructions
Jan 8, 2014, 9:24 AM
Rohit Sant edited CMPS/CMPSB/CMPSW
Jan 8, 2014, 9:08 AM
Rohit Sant created CMPS/CMPSB/CMPSW
Jan 8, 2014, 8:54 AM
Rohit Sant edited MOVS/MOVSB/MOVSW
Jan 8, 2014, 8:50 AM
Rohit Sant edited REPE/REPNE/REPZ/REPNZ
Jan 8, 2014, 8:47 AM
Rohit Sant edited MOVS/MOVSB/MOVSW
Jan 8, 2014, 8:32 AM
Rohit Sant created MOVS/MOVSB/MOVSW
Jan 6, 2014, 10:59 PM
Rohit Sant edited REPE/REPNE/REPZ/REPNZ
Jan 6, 2014, 10:39 PM
Rohit Sant edited REPE/REPNE/REPZ/REPNZ
Jan 6, 2014, 10:17 PM
Rohit Sant created REPE/REPNE/REPZ/REPNZ
Jan 6, 2014, 10:15 PM
Rohit Sant edited REP
Jan 4, 2014, 9:33 PM
Rohit Sant edited REP
AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
Search this site
older | newer
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=300[3/9/2019 9:50:39 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=300[3/9/2019 9:50:39 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=300[3/9/2019 9:50:39 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Recent site activity - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
Recent site activity
Jan 4, 2014, 8:33 PM
Rohit Sant created REP
Jan 4, 2014, 8:31 PM
Rohit Sant edited String Instructions
Jan 4, 2014, 8:26 PM
Rohit Sant created String Instructions
Dec 24, 2013, 2:16 PM
Rohit Sant edited Arithmetic Instructions
ADC
Dec 24, 2013, 2:14 PM
Rohit Sant edited Arithmetic Instructions
ADD
Dec 24, 2013, 2:13 PM
Rohit Sant created Arithmetic Instructions
CMP
Dec 14, 2013, 5:03 PM
Rohit Sant edited LDS/LES
DAA
Dec 14, 2013, 4:47 PM
Rohit Sant created LDS/LES
DAS
Dec 14, 2013, 4:36 PM
Rohit Sant edited LEA
DEC
Dec 14, 2013, 4:27 PM
Rohit Sant edited LEA
DIV
Dec 14, 2013, 4:19 PM
Rohit Sant created LEA
IDIV
Dec 14, 2013, 4:15 PM
Rohit Sant edited XLAT(B)
IMUL
Dec 14, 2013, 2:55 PM
Rohit Sant edited XLAT(B)
INC
Dec 14, 2013, 2:31 PM
Rohit Sant created XLAT
Dec 14, 2013, 2:25 PM
Rohit Sant edited XCHG
Dec 14, 2013, 2:15 PM
Rohit Sant created XCHG
Dec 14, 2013, 1:07 PM
Rohit Sant edited MOVSX [386+]
Dec 14, 2013, 1:05 PM
Rohit Sant edited MOVSX [386+]
Dec 14, 2013, 12:05 PM
Rohit Sant created MOVSX
Dec 14, 2013, 11:59 AM
Rohit Sant edited MOVS
Dec 14, 2013, 11:20 AM
Rohit Sant created MOVS
Dec 13, 2013, 5:42 PM
Rohit Sant edited Move
Dec 13, 2013, 5:39 PM
Rohit Sant edited Move
Dec 13, 2013, 5:31 PM
Rohit Sant edited Move
Dec 13, 2013, 5:29 PM
Rohit Sant edited Move
AAD
AAM
AAS
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
Search this site
older | newer
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=325[3/9/2019 9:51:05 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=325[3/9/2019 9:51:05 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=325[3/9/2019 9:51:05 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Recent site activity - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
Recent site activity
Dec 13, 2013, 5:28 PM
Rohit Sant edited Move
Dec 13, 2013, 5:25 PM
Rohit Sant edited Move
Dec 13, 2013, 2:36 PM
Rohit Sant edited Move
Dec 10, 2013, 11:12 PM
Rohit Sant edited Home
ADC
Dec 10, 2013, 11:06 PM
Rohit Sant edited Home
ADD
Dec 10, 2013, 11:02 PM
Rohit Sant edited Home
CMP
Dec 10, 2013, 11:01 PM
Rohit Sant edited Home
DAA
Dec 10, 2013, 10:58 PM
Rohit Sant edited Home
DAS
Dec 10, 2013, 10:35 PM
Rohit Sant edited Move
DEC
Dec 10, 2013, 10:25 PM
Rohit Sant created Move
DIV
Dec 10, 2013, 10:24 PM
Rohit Sant edited Data Transfer
IDIV
Dec 10, 2013, 10:23 PM
Rohit Sant created Data Transfer
IMUL
Dec 10, 2013, 10:22 PM
Rohit Sant deleted Data Transfer Instructions
INC
Dec 10, 2013, 10:21 PM
Rohit Sant created Data Transfer Instructions
Dec 10, 2013, 10:20 PM
Rohit Sant edited Home
AAD
AAM
AAS
MUL
NEG
SBB
Search this site
older | newer
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=350[3/9/2019 9:51:31 PM]
Recent site activity - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=350[3/9/2019 9:51:31 PM]
Recent site activity - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=350[3/9/2019 9:51:31 PM]
Recent site activity - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Page not found - Microprocessors@BITS
Microprocessors@BITS
Home
Arithmetic
Instructions
AAA
AAD
Search this site
Page not found
We're sorry, but we were unable to locate the page you requested.
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/...roprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:5a35d5d6f746ce51[3/9/2019 9:52:01 PM]
Page not found - Microprocessors@BITS
SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL
https://sites.google.com/...roprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:5a35d5d6f746ce51[3/9/2019 9:52:01 PM]
Page not found - Microprocessors@BITS
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
https://sites.google.com/...roprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:5a35d5d6f746ce51[3/9/2019 9:52:01 PM]
Page not found - Microprocessors@BITS
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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https://sites.google.com/...roprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:5a35d5d6f746ce51[3/9/2019 9:52:01 PM]