Circuit Design and Experimental Verification of Low-voltage Organic Field-effect
Transistor-based Common Source Amplifier
independent of the transistors size, enabling designers to
size the circuits in more efficient way. The expression of
transconductance efficiency can be derived as (1) and its
value can be extracted from a normalized OFET transfer
curve as shown in Fig. 1(a).
𝐼
𝑔𝑚
𝐼𝐷
𝜕ln𝐼𝐷
=
𝜕𝑉𝐺
=
𝐷 ]
𝜕ln[(𝑊/𝐿)
(1)
𝜕𝑉𝐺
By analyzing the operating principle of field effect
transistors (FET), it can be seen that in the subthreshold
region, the transconductance efficiency significantly
enhances due to the exponential relationship between drain
current and gate voltage and the value has a close
relationship with SS as shown (2).
I. INTRODUCTION
𝑔𝑚
Organic field-effect transistors (OFETs) have
increasingly attracted attentions to flexible sensors due to
well compatibility with low-temperature high throughput
processing, superior mechanical flexibility, and feasibility
for combination of front-end sensing and amplification [1].
Organic amplifier circuit is required to in-situ amplify the
sensing signals to better resist the interference of noise
from external environment and therefore improve the
signal-to-noise (SNR) of the sensor system [2]. However,
the large subthreshold swing (SS) of solution processed
OFET would be a critical hurdle preventing the amplifier
from achieving high gain and low power consumption
simultaneously. Moreover, the lack of accurate OFET
compact model, especially in subthreshold operating
region, brings difficulties for circuit designers to design
low-power subthreshold circuits [3].
In this work, fully printable low-voltage OFET
amplifier is designed by using transconductance efficiency
(gm/ID) circuit design methodology [3] and realized based
on low trap-state density OFET (LTDOFET) technology
[4]. The circuit design methodology specifies both
saturation and subthreshold region for quickly sizing the
amplifier for low power circuit design. This is useful to get
rid of the dependence on the inaccurate OFET model and
improve the efficiency of circuit design [5]. The realized
common source amplifier shows high-gain of 15 V/V at
low operating voltage of 3 V, and demonstrates reliable
amplification of input small signal. Finally, a low-voltage
high-gain common source amplifier was realized and
demonstrated the reliable amplification of the input small
signal.
𝐼𝐷
II. CIRCUIT DESIGN METHOD
The gm/ID ratio is a measure of the efficiency to translate
current into transconductance. Higher gm/ID means greater
transconductance can be obtained at a constant current
value, which is a very useful figure-of-merit in low power
circuit design. What's more, transconductance efficiency is
=
1 𝜕𝐼𝐷
𝐼𝐷 𝜕𝑉𝐺
=
𝜕ln𝐼𝐷
𝜕𝑉𝐺𝑆
= ln10/ (ln10 ⋅
𝜕𝑉𝐺𝑆
𝜕ln𝐼𝐷
)=
ln10
𝑆𝑆
(2)
Traditional organic common source amplifier in sensing
applications is based on diode-connected load topology
and the schematic is shown in Fig. 1(b). Under this
topology, the low-frequency small-signal voltage gain can
be analyzed as shown below (3):
|𝐴𝑉 | = 𝑔𝑚1 ⋅
1
𝑔𝑚2
||
1
𝑔𝑑𝑠2
≈
𝑔𝑚1
𝑔𝑚2
=
𝑔𝑚1 /𝐼𝐷
𝑔𝑚2 /𝐼𝐷
(3)
Usually 1/gds is much larger than 1/gm except for short
channel FET device, so we can ignore 1/gds. Therefore, the
voltage gain depends on the ratio of the transconductance
of the drive transistor (T1) and load transistor (T2). With
the circuit topology and device characteristics can be used
to design low-power high-gain 1-stage amplifier according
to the simplified design flow chart (Fig. 2).
VDD
40
10-9
30
10-11
20
10
2
-13
10
gm/I D (V-1)
Abstract - The request for efficient circuit design and
solution/printing-compatible manufacturing of high
performance low-voltage amplifiers have gradually
become more and more urgent. In this work, a
transconductance efficiency based circuit design
methodology is introduced for quick sizing of an
organic low-voltage common source amplifier, which is
further verified by a fully solution-processed amplifier
circuit. The amplifier is developed based on a low trapstate density OFET (LTDOFET) technology and
demonstrated reliable amplification of the input small
signal.
Keywords: Organic field-effect transistor, Circuit Design,
Low voltage, Subthreshold operation, and Organic
amplifier
|ID_normalized| (A)
2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) | 978-1-7281-8176-9/21/$31.00 ©2021 IEEE | DOI: 10.1109/EDTM50988.2021.9421046
Li’ang Deng1, Wei Tang1, Lei Han1, Yukun Huang1, Xiaojun Guo1
1
Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai, China
e-mail: x.guo@sjtu.edu.cn; phone: +86-21-34207430
VIN
1
VOUT
0
-3
-2
-1
0
1
GND
VGS (V)
(a)
(b)
Fig. 1 (a) Typical transfer curve of OFET device after
normalization and extracted gm/ID curve; (b) Schematic of the
proposed amplifier
According to (2), the maximum transconductance
efficiency is restrained by the SS of the device. Further
more, besides high transconductance efficiency, supply
voltage is another concerning issue for designing an
amplifier applied in the field of biochemical sensing.
However, conventional OFETs can only operate well in
high supply voltage due to the high threshold voltage and
the large SS of more than 1000 mV/dec, which leads to
small transconductance efficiency [1]. Therefore, it is very
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10-6
3
-8
10
10
Select circuit topology
according to Specs.
|ID |(μA)
|ID| (A)
encouraging to obtain steep SS OFETs and provide a circuit
design method of high efficiency to construct high
performance organic amplifier.
-10
VGS = - 3 V
2
-2V
1
10-12
VDS = -3 V
VDS = -0.3 V
-3
List the expression of the target parameter
(gm/ID as the independent variable)
-2
-1
0
VGS (V)
-1V
0
0
1
-1
-2
VDS (V)
(a)
Determine the DC operating point of each node
in the circuit
Size the transistors according to the constraints
Fig. 2 Simplified design flow chart of gm/ID methodology.
III. EXPERIMENTAL VERIFICATION
A. Fabrication of LTDOFET
The OFET was fabricated on PEN foil with bottom-gate
bottom-contact structure by all solution processes as
shown in Fig. 3. The gate and source/drain (S/D) electrodes
were inkjet printed from nano-silver inks with a
piezoelectric inkjet printer (Dimatix, DMP 2831).
Polymeric ES2110 (~600 nm) and PVCN (~100 nm) layers
were spin-coated to form the gate dielectric. Self-assembly
monolayers (per-fluorobenzene thiol, PFBT) was used to
modify the surface of Ag S/D electrodes. A low trap-state
density channel was deposited from TIPS-pentacene/PS
blend solution using a soft-contact coating (SCC) method
and encapsulated by CYTOP.
ES2110
Gate
Substrate
1. Inkjet printing
S/D
The sizing design flow is shown in Fig. 2. Design details
in this work for the application of gm/ID methodology are
described below:
Conventional diode-connected load topology (Fig. 1(b))
is selected to achieve high gain at low voltage (VDD = 3V).
The expression of target (small signal gain) is derived as
shown in (3), so T1 needs to be biased in large gm/ID region
(brown box of Fig. 1(a)) while T2 needs to be biased in
small gm/ID region (blue box of Fig. 1(a)). Therefore, VGS
of T1 and T2 should be biased at -0.6 V and -1.5 V, which
can make the DC operating point of the output node at
VDD/2. The constraint generated by Kirchhoff Current Law
(KCL) is that the channel currents of T1 and T2 must be
equal. The normalized currents corresponding to the two
transistors under different bias conditions are
approximately 6×10-13 A and 3×10-10 A respectively (as
shown in Fig. 1(a)). To meet the above constraints, the ratio
of 𝑊/𝐿 between T1 and T2 is shown in (4)：
(𝑊/𝐿)1
=
(𝑊/𝐿)2
𝐼𝑇2,𝑛𝑜𝑟𝑚𝑎𝑙𝑖𝑧𝑒𝑑
𝐼𝑇1,𝑛𝑜𝑟𝑚𝑎𝑙𝑖𝑧𝑒𝑑
≈
3×10−10 𝐴
6×10−13 𝐴
OSC
VOUT
VDD
PVCN
ES2110
Gate
Substrate
PVCN
ES2110
Gate
Substrate
4. Inkjet printing
3. Solution coating
N/A
PVCN
ES2110
VIN
5. Soft-contact coating
OSC
PVCN
ES2110
Gate
Substrate
S/D
S/D
T1
GND
(Via)
T2 V
OUT
(a)
3
6. Solution coating
Fig. 3 The manufacturing process of OFET.
B. Device Characterization and Circuit Sizing
The device presents well-behaved low-voltage (≤ 3V)
transfer and output characteristics as shown in Fig. 4. The
extracted SS is 83 mV/dec, and the device exhibits
characteristics of near-zero threshold voltage, which
ascribes from the LTDOFET technology [4]. The obtained
low SS and low operating voltage characteristics are
attractive to design a low-power high-gain amplifier,
which is expected to be used in in-situ sensing detection.
2
1
0
0
(b)
20
VDD = 3 V
VDD = 3 V
15
VDD = 2 V
AV (V/V)
S/D
VIN
GND
Substrate
VOUT (V)
OSC
PVCN
ES2110
Gate
Substrate
(4)
VDD
Via
CYTOP
S/D
= 500: 1
C. Realization of Amplifier
2. Solution coating
S/D
(b)
Fig. 4 Fabricated OFET (W/L = 20000 μm/40 μm) operating
characteristic curve: (a) Transfer curves and (b) Output curves.
Determine the operating region of each transistor
Gate
Substrate
-3
VDD = 1 V
VDD = 2 V
10
VDD = 1 V
5
1
2
3
VIN (V)
(c)
4
5
0
0
1
2
3
4
VIN (V)
(d)
Fig. 5 (a) Cross-section structure and (b) photo-image of the
fabricated circuit; (c) The transfer performance and (d) lowfrequency small signal voltage gain at different low supply
voltages.
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Due to the aforementioned design, OFET common
source amplifier was fabricated as shown in Fig. 5(a). In
this circuit, W/L of T1 and T2 are 20000 μm/40 μm and 150
μm /150 μm respectively. The via-hole was formed by
laser-drill and electrically connected with silver ink paste.
Fig. 5(b) shows the photo of the fabricated amplifier. Fig.
5(c) demonstrates the performance of the fabricated
amplifier operating at different supply voltages and Fig.
5(d) shows the results of the extracted low-frequency small
signal voltage gain at different supply voltages. Under low
supply voltage of 3 V, the fabricated amplifier can achieve
more than 10 times of low-frequency small signal
amplification.
D. Amplification Verification
VDD1
R1
VDD2
VINPUT
R1
T1
VOUT
VTEST
R2
T2
R2
VDD1
VTEST
used to increase the influence of external electromagnetic
interference on the front-end signal VTEST. In this way, a
noise input of about 10 mV peak-to-peak is obtained and
inversely amplified by about 7 times by the low-voltage
organic high-gain amplifier as shown in Fig. 6(c).
IV. CONCLUSIONS
In summary, gm/ID circuit design methodology is
proposed for efficient design of low-voltage OFET
amplifier and experimentally verified by fully printable
common source amplifier based on LTDOFET technology.
It is proved that this circuit design methodology enables
quickly sizing of the amplifier without the need for
accurate OFET model. The realized flexible amplifier
shows high-gain of up to 15 V/V at low supply voltage of
3 V. It is found that a noise input of about 10 mV peak-topeak can be inversely amplified by about 7 times at a
biasing voltage near 3.1 V, demonstrating reliable
amplification of input small signal.
GND
ACKNOWLEDGMENT
GND
(a)
VINPUT
The authors gratefully acknowledge the funding support
from NSFC of China under Grant 61804094 and 61674102.
(b)
10 mV
References
25 s
[1]
VOUT
10 mV
≈
25 s
(c)
Fig. 6 (a) Schematic of the test setup; (b) Photo of thin film
resistor; (c)Test signal obtained before and after amplification.
In order to verify the amplification of the fabricated
amplifier, an input signal (VINPUT) is introduced to simulate
the actual sensing signal in practical application (Fig. 6(a)).
Here, a classic test structure is utilized, which is widely
used for transducing temperature, pressure or some other
form of signals into voltage signal [6]. Two resistors in
series are fabricated by screen printing of widely-used
conducting polymer PEDOT: PSS (Fig. 6(b)), where the
resistance of R1 and R2 is 1 KΩ and 0.75 KΩ respectively.
The resistance values are designed to produce a suitable
VTEST (3.1 V) to bias the amplifier near the high-gain
region according to Fig. 4(a). Small resistances are used to
increase heat production at low supply voltage and
therefore thermal noise. Moreover, an extended 1m-long
Cu cable wire (As shown by the red line in Fig. 6(a)) is
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2021 Electron Devices Technology and Manufacturing Conference (EDTM)
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