Digital Logic Design
Asynchronous Counters
Counters
 Introduction: Counters
 Asynchronous (Ripple) Counters
 Asynchronous Counters with MOD number
<2
n
 Asynchronous Down Counters
 Cascading Asynchronous Counters
2
Introduction: Counters
 Counters are circuits that cycle through a specified
number of states.
 Two types of counters:
 synchronous (parallel) counters
 asynchronous (ripple) counters
 Ripple counters allow some flip-flop outputs to be
used as a source of clock for other flip-flops.
 Synchronous counters apply the same clock to all
flip-flops.
3
Asynchronous (Ripple) Counters
 Asynchronous counters: the flip-flops do not



change states at exactly the same time as they do
not have a common clock pulse.
Also known as ripple counters, as the input clock
pulse “ripples” through the counter – cumulative
delay is a drawback.
n
n flip-flops  a MOD (modulus) 2 counter.
(Note: A MOD-x counter cycles through x states.)
Output of the last flip-flop (MSB) divides the
input clock frequency by the MOD number of the
counter, hence a counter is also a frequency
divider.
4
Asynchronous (Ripple) Counters
 Example: 2-bit ripple binary counter.
 Output of one flip-flop is connected to the clock
input of the next more-significant flip-flop.
HIGH
Q0
J
C
K
CLK
FF0
CLK
1
2
3
Q0
Q1
J
C
K
FF1
4
Q0
Q0
0
1
0
1
0
Q1
0
0
1
1
0
Timing diagram
00  01  10  11  00 ...
5
Asynchronous (Ripple) Counters
 Example: 3-bit ripple binary counter.
HIGH
Q0
J
CLK
C
K
C
K
Q0
FF0
CLK
1
2
Q1
J
C
K
Q1
FF2
FF1
3
4
5
Q2
J
6
7
8
Q0
0
1
0
1
0
1
0
1
0
Q1
0
0
1
1
0
0
1
1
0
Q2
0
0
0
0
1
1
1
1
0
Recycles back to 0
6
Asynchronous (Ripple) Counters
 Propagation delays in an asynchronous (ripple-
clocked) binary counter.
 If the accumulated delay is greater than the clock
pulse, some counter states may be misrepresented!
CLK
1
2
3
4
Q0
Q1
Q2
tPLH
(CLK to Q0)
tPHL (CLK to Q0)
tPLH (Q0 to Q1)
tPHL (CLK to Q0)
tPHL (Q0 to Q1)
tPLH (Q1 to Q2)
7
Asynchronous (Ripple) Counters
 Example: 4-bit ripple binary counter (negativeedge triggered).
HIGH
Q0
J
CLK
C
K
FF0
Q1
J
C
K
FF1
Q2
J
C
K
FF2
Q3
J
C
K
FF3
8
n
Asyn. Counters with MOD no. < 2
 States may be skipped resulting in a truncated
sequence.
 Technique: force counter to recycle before going
through all of the states in the binary sequence.
 Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)
C
All J, K
inputs are
1 (HIGH).
Q
J
B
Q
CLK
Q
CLR
J
A
Q
CLK
K
Q
CLR
J
CLK
K
Q
CLR
K
B
C
9
n
Asyn. Counters with MOD no. < 2
 Example (cont’d):
C
All J, K
inputs are
1 (HIGH).
Q
B
J
Q
CLK
Q
CLR
J
A
Q
CLK
K
Q
CLR
J
CLK
K
Q
CLR
K
B
C
Clock
A
B
C
1
2
3
4
5
6
7
8
9
10 11 12
MOD-6 counter
produced by clearing
(a MOD-8 binary
counter) when count
of six (110) occurs.
NAND 1
Output 0
10
n
Asyn. Counters with MOD no. < 2
 Example (cont’d): Counting sequence of
circuit (in CBA order).
1
Clock
A 0
0
B
C
NAND 1
Output 0
Temporary
state
0
111
2
1
0
0
3
0 1
1 1
0 0
000
4
5
6
7
0
0
1
0
0 1
0 0
1
1
0 0
9
10 11 12
001
110
010
101
8
Counter is a MOD-6
counter.
011
100
11
n
Asyn. Counters with MOD no. < 2
 Exercise: How to construct an asynchronous MOD5 counter? MOD-7 counter? MOD-12 counter?
 Question: The following is a MOD-? counter?
F
Q
J
Q
K
CLR
E
Q
J
Q
K
CLR
D
Q
J
Q
K
CLR
C
D
E
F
C
Q
J
Q
K
CLR
B
Q
J
Q
A
K
CLR
Q
J
Q
K
CLR
All J = K = 1.
12
n
Asyn. Counters with MOD no. < 2
 Decade counters (or BCD counters) are counters
with 10 states (modulus-10) in their sequence.
They are commonly used in daily life (e.g.: utility
meters, odometers, etc.).
 Design an asynchronous decade counter.
(A.C)'
HIGH
J
CLK
Q
D
J
Q
C
J
Q
B
J
Q
C
C
C
C
K
K
K
K
CLR
CLR
CLR
A
CLR
13
n
Asyn. Counters with MOD no. < 2
 Asynchronous decade/BCD counter (cont’d).
HIGH
J
CLK
Q
D
J
C
K
Q
C
J
C
K
CLR
2
J
C
K
CLR
1
B
Q
4
5
A
(A.C)'
C
K
CLR
3
Q
CLR
6
7
8
9
10
Clock
D
0
1
0
1
0
1
0
1
0
1
0
C
0
0
1
1
0
0
1
1
0
0
0
B
0
0
0
0
1
1
1
1
0
0
0
A
0
0
0
0
0
0
0
0
1
1
0
11
NAND
output
14
Asynchronous Down Counters
 So far we are dealing with up counters. Down
counters, on the other hand, count downward
from a maximum value to zero, and repeat.
 Example: A 3-bit binary (MOD-23) down counter.
1
J
CLK
Q
Q0
J
Q
Q1
C
K Q'
C
Q'
K
J
Q
Q2
C
K Q'
3-bit binary
up counter
1
J
CLK
Q
C
Q'
K
Q0
J
Q
C
K Q'
Q1
J
Q
C
K Q'
Q2
3-bit binary
down counter
15
Asynchronous Down Counters
 Example: A 3-bit binary (MOD-8) down counter.
000
001
1
J
CLK
Q0
Q
J
Q
Q1
J
C
K Q'
C
Q'
K
Q2
Q
111
010
C
K Q'
110
011
101
100
CLK
1
2
3
4
5
6
7
8
Q0
0
1
0
1
0
1
0
1
0
Q1
0
1
1
0
0
1
1
0
0
Q2
0
1
1
1
1
0
0
0
0
16
Cascading Asynchronous Counters
 Larger asynchronous (ripple) counter can be
constructed by cascading smaller ripple counters.
 Connect last-stage output of one counter to the
clock input of next counter so as to achieve highermodulus operation.
 Example: A modulus-32 ripple counter constructed
from a modulus-4 counter and a modulus-8
counter.
Q0
J
CLK
Q
C
Q'
K
Q1
J
Q
C
K Q'
Modulus-4 counter
Q2
J
Q3
J
Q
C
Q'
K
Q
C
K Q'
Q4
J
Q
C
K Q'
Modulus-8 counter
17
Cascading Asynchronous Counters
 Example: A 6-bit binary counter (counts from
0 to 63) constructed from two 3-bit counters.
A0 A1 A2
Count
pulse
A3 A4 A5
3-bit
binary counter
3-bit
binary counter
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
:
0
0
0
0
0
0
:
0
0
0
0
1
1
:
0
0
:
1
0
0
:
0
0
:
1
0
0
:
0
1
:
1
0
1
:
18
MOD-10 Self Stop Counter
MOD-10 Self Stop Counter Timing
Diagram
Random Sequence Counters
• These type of counters will count random
sequence and design through combinational
logic and seuential logic.
Designing Steps
1. Length of Counter
2. Output Table
3. K-map for combinational part output
4. Circuit designing
Random Sequence Counters
Q. Design random sequence counter which will
count the following random sequence.
0,4,2,8,10,0,11,9
Step 1: Length of counter
2n = 23 = 8 total number of count
3 JK Flip-Flop required
Toggle Mode is used
Random Sequence Counters
Step 2. Output Table
Sequential Part
Y2 Y1 Y0
Combinational Part
Q3 Q2 Q1 Q0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
1
1
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
0
0
1
Random Sequence Counters
Step 3. Design K-Map for the output of
Combinational part
Q0  Y2 Y1
Q1  Y1 Y0  Y2 Y0
Random Sequence Counters
Q2  Y2 Y1 Y0
Q3  Y1 Y0  Y2 Y1  Y2 Y1
Step 5 Circuit Realization and timing Diagram
Random Sequence Counter
• Design 3-bit even counter.
• Design 3-bit odd counter.
• Design asynchronous random sequence
counter which will count the following
random sequence.
5,8,13,0,8,9
Random Sequence Counter
• Design random sequence counter which count
the following random sequence.
4,8,12,6,4,0
Step 1: Length of counter
3 JK Flip-Flop required
Toggle Mode is used
Random Sequence Counters
Step 2. Output Table
Sequential Part
Y2 Y1 Y0
Combinational Part
Q3 Q2 Q1 Q0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
1
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
Random Sequence Counters
Step 3. Design K-Map for the output of
Combinational part
Q0  GND
Q1  Y1 Y0
Random Sequence Counters
Q2  Y1  Y0
Q3  Y1 Y0  Y2 Y1 Y0
Step 5 Circuit Realization and timing Diagram
Ripple Counter ICs - 7493
• 7493: a divide-by-2 and a divide-by-8
• MR1,MR2 can be utilized to do MOD-N.
Ripple Counter ICs – 7493 (cont’d)
• External connection as a MOD-16 counter.
74LS93 IC MOD-6 COUNTER
Ripple Counter ICs – 7493 (cont’d)
• External connection as a MOD-12 counter.
Random Sequence Counter
• Design 3 bit random sequence counter which
count the following sequence.
If C = 0 Count = 2,4,6,8,10,12,14,16
If C = 1 Count = 1,3,5,7,9,11,13,15
Solution: Step 1 Length of Counter
23 = 8 = 3 JK Flip Flops
Toggle Mode
Output Table
Sequential Part
Y2 Y1 Y0
IF C = 0
Q4 Q3 Q2 Q1 Q0
IF C = 1
Q4 Q3 Q2 Q1 Q0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
0
1
0
0
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
K-MAP
Q0  C
Q1  C Y0  C Y0
K-MAP
Q2  C Y1 Y0  C Y1 Y0  C Y1
Q3  C Y2 Y1  C Y2 Y0  C Y2 Y1 Y0  C Y2
K-MAP
Q4  C Y2 Y1 Y0
Random Sequence Counters
• Design ripple random sequence counter which
count the following sequence.
If C1C2 = 00; Count = 0, 2, 4, 6
If C1C2 = 01; Count = 6, 4, 2, 0
If C1C2 = 10; Reset
If C1C2 = 11; Preset
Random Sequence Counters
Output Table
Y1 Y0
C2 C1 = 00
Q2 Q1 Q0
C2 C1 = 01
Q2 Q1 Q0
C2 C1 = 10
Q2 Q1 Q0
C2 C1 = 11
Q2 Q1 Q0
0
0
0
0 0
1
1 0
0
0 0
1
1 1
0
1
0
1 0
1
0 0
0
0 0
1
1 1
1
0
1
0 0
0
1 0
0
0 0
1
1 1
1
1
1
1 0
0
0 0
0
0 0
1
1 1
Random Sequence Counter
FOR Q0
Q0  C2 C1
FOR Q1
Q1  C2 C1 Y0  C2 C1 Y1  C1 C2
Random Sequence Counter
Q 2  C 2 C1 Y1  C 2 C1 Y1  C 2 C1