MLX81325 Smart LIN Driver for small motors <100W
Datasheet

1 Features and Benefits
Microcontroller: Melexis MULAN3 core
 Communication CPU Mlx4 for LIN protocol
handling
 Application CPU Mlx16, 16 bit RISC-CPU, Cprogrammable
 Programmable digital watch-dog with
several different modes
 19 inputs interrupt controller
 Common purpose timer
Memories
 32 Kbyte Flash (8k x 32)+ 16 Kbyte ROM
(8k x 32) with ECC, shared between Mlx16
and Mlx4
 2 Kbyte RAM (1024 x 16), shared between
Mlx16 and Mlx4
 2 x 256 Byte NVRAM (128 x 16) with ECC,
only accessible by the Mlx16
Periphery
 pre-driver for small NFETs (<30nC@25kHz
PWM) to drive 2x DC, BLDC or Stepper
motor
 8 pins for Digital IO, ADC, Timer/Capture,
Master/Slave SPI
 5 programmable 16-bit PWM modules
with frequencies 10…50kHz
 PWM-synchronized fast internal current
sense circuit for sensorless sine drive
 28 MHz +/-5% PLL clock derived from
internal RC-oscillator
 integrated watchdog, independent from
system-clock
 on-chip temperature sensor with +/-10°C
accuracy
 10 bit ADC < 6 µs conversion, auto-DMA
storage, 28 channels, 0.75-1.5-2.5V
reference
 overcurrent detection; overvoltage and
undervoltage protection
 overtemperature protection
Voltage regulator
 normal operating voltage VS = 5.5V...28V*
(*operating voltage up to 36V limited to
24h over lifetime)
 undervoltage interrupt setting between
4V…9V
REVISION 1.7 - 27. Apr 2020
3.3V regulator for >25mA current to
supply 3x Hall + 1x Triaxis sensor
 MCU control in 3.5V...28V range, without
losing memory/register content
 low SLEEP MODE current of typ. < 25uA;
periodic wake-up timer < 100uA
Bus interface
 support for PWM, LIN 2.x, SAE J2602
 wake-up possible via LIN, external pin
(IO[3]) or internal wakeup timer
Automotive AEC-Q100 Qualified
2 Application Examples



Smart thermal valves, grille shutters
Small BLDC water pumps, oil pumps
DC motor positioning for Windowlift,
Sunroofs, Seats, Doors,..
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
3 Ordering Information
Order Code
Temp. Range
Package
Delivery
Remark
MLX81325 LLQ-BMA-003-RE
-40 - 150 °C
QFN32 5x5
Reel
MLX81325B; NVRAM
patch
MLX81325 LLQ-BMA-103-RE
-40 - 150 °C
QFN32 5x5
Reel
MLX81325B (ILS bond
option), NVRAM patch
Table 3.1: Ordering Information
MLX81325 LLQ xxx 000 RE
Delivery Form: RE = Reel
Option Code, MLX internal
Bond option, 0: Pin 16=LINOUT; 1: Pin 16=ILS2
Assembly house
Customer name, M=Melexis for all Flash
Silicon Version: Character [A...Z]
Package Code: LQ=QFN
Temperature Code: L=-40 to 150°C
Product Name
REVISION 1.7 - 27. Apr 2020
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
4 Contents
1
2
3
4
5
6
7
Features and Benefits....................................................................................................................... 1
Application Examples ....................................................................................................................... 1
Ordering Information ....................................................................................................................... 2
Contents........................................................................................................................................... 3
History.............................................................................................................................................. 7
Referred documentation .................................................................................................................. 8
Technical description ....................................................................................................................... 9
7.1 Package data QFN32 (5x5, 32 leads) [1] ..........................................................................................9
7.2 Marking instruction ...................................................................................................................... 10
7.3 Pin out description ....................................................................................................................... 11
7.3.1
Option code 0 .................................................................................................................. 12
7.3.2
Option code 1 .................................................................................................................. 12
7.3.3
Electrical Characteristics ................................................................................................. 13
7.4 Absolute Maximum Ratings ......................................................................................................... 13
7.5 Operating Conditions ................................................................................................................... 15
7.6 Electrical parameter specification ............................................................................................... 16
8
MLX81325 – Typical application schematic .................................................................................... 25
9
Functional description .................................................................................................................... 27
9.1 Block-Diagram .............................................................................................................................. 27
9.2 System behavior description ....................................................................................................... 28
9.2.1
The supply system of MLX81325 .................................................................................... 28
9.2.2
Power On .......................................................................................................................... 28
9.2.3
Power Off ......................................................................................................................... 30
9.2.4
System initialization and Trimming ................................................................................. 30
9.2.5
Entering SLEEP MODE (GO TO SLEEP MODE = GTSM) .................................................. 30
9.2.6
WAKE UP from SLEEP MODE ........................................................................................... 31
9.2.7
Entering HOLD MODE ...................................................................................................... 32
9.2.8
Releasing HOLD MODE .................................................................................................... 32
9.2.9
System behaviour in case of different undervoltage conditions .................................. 33
9.3 Digital Part .................................................................................................................................... 33
9.3.1
CPU core MULAN3 – MULtiple CPU with Analog and Network support ...................... 33
9.3.1.1
9.3.1.2
9.3.1.3
9.3.1.4
9.3.1.5
9.3.1.6
9.3.1.7
9.3.1.8
9.3.1.9
9.3.2
MULAN3 compared to MULAN2........................................................................................ 33
MULAN3 CPU Performance ............................................................................................... 34
Change PRIO MLX4/MLX16 ................................................................................................ 34
MULAN3 Architecture ....................................................................................................... 34
MULAN3 Address space..................................................................................................... 35
Memory mapping .............................................................................................................. 36
MULAN3 included periphery – 15bit Timer ....................................................................... 37
MULAN3 included periphery - Watchdog .......................................................................... 38
MULAN3 included periphery - ADC interface .................................................................... 41
Memories ......................................................................................................................... 48
9.3.2.1
9.3.2.2
RAM sharing ...................................................................................................................... 48
ROM / Flash sharing........................................................................................................... 48
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
9.3.2.3
9.3.2.4
9.3.3
Mlx16 interrupts .............................................................................................................. 55
9.3.3.1
9.3.3.2
9.3.3.3
9.3.3.4
9.3.3.5
9.3.3.6
9.3.3.7
9.3.4
9.3.5
General introduction and features .................................................................................... 67
Block diagram and description .......................................................................................... 67
PWM frequency control .................................................................................................... 69
Synchronization of the PWM modules .............................................................................. 70
Independent mode ............................................................................................................ 71
Mirror mode ...................................................................................................................... 72
PWM control and command ports .................................................................................... 73
Interrupts connections ...................................................................................................... 75
Timers ............................................................................................................................... 75
9.3.6.1
9.3.6.2
9.3.6.3
9.3.6.4
9.3.6.5
9.3.6.6
9.3.6.7
9.3.6.8
9.3.6.9
9.3.6.10
9.3.6.11
9.3.7
Introduction ....................................................................................................................... 55
Interrupt sources ............................................................................................................... 55
Interrupt management ...................................................................................................... 55
Interrupt priorities ............................................................................................................. 56
Mlx16 interrupt table ........................................................................................................ 57
Interrupt vectors................................................................................................................ 58
External Interrupts connection .......................................................................................... 59
Ports-Map......................................................................................................................... 62
PWM ................................................................................................................................. 67
9.3.5.1
9.3.5.2
9.3.5.3
9.3.5.4
9.3.5.5
9.3.5.6
9.3.5.7
9.3.5.8
9.3.6
Flash macro ....................................................................................................................... 48
NVRAM .............................................................................................................................. 50
Introduction and Features ................................................................................................. 75
Block diagram and description .......................................................................................... 77
Timer mode ....................................................................................................................... 77
Dual Timer Compare mode................................................................................................ 79
Dual Timer Capture mode ................................................................................................. 82
Timer Capture/Compare mode ......................................................................................... 84
Pulse accumulator mode ................................................................................................... 86
Debouncer mode ............................................................................................................... 87
PWM mode ........................................................................................................................ 89
Timers IO ports .................................................................................................................. 93
Interrupt connections ........................................................................................................ 95
SPI Interface ..................................................................................................................... 96
9.3.7.1
9.3.7.2
9.3.7.3
9.3.7.4
9.3.7.5
9.3.7.6
9.3.7.7
Features ............................................................................................................................. 96
Applications ....................................................................................................................... 96
Block diagram and description .......................................................................................... 96
Notes about IO ports usage ............................................................................................... 98
Master mode ..................................................................................................................... 99
Slave mode ........................................................................................................................ 99
SPI IO ports ...................................................................................................................... 100
9.4 Analogue- and Mixed Signal Part .............................................................................................. 105
9.4.1
Oscillator concept .......................................................................................................... 105
9.4.1.1
RC-Oscillator .................................................................................................................... 106
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
9.4.1.2
9.4.1.3
9.4.1.4
9.4.1.5
9.4.1.6
9.4.1.7
9.4.2
Supply sensor ................................................................................................................. 110
9.4.2.1
9.4.2.2
9.4.3
Architecture ..................................................................................................................... 116
Principle ........................................................................................................................... 117
ADC trigger selection ....................................................................................................... 118
Memory needs................................................................................................................. 118
Timings ............................................................................................................................ 121
ADC interface ports ......................................................................................................... 121
ADC Channel selection ..................................................................................................... 124
Watching the API by Analogue Watchdog (AWD) ....................................................... 125
9.4.6.1
9.4.6.2
9.4.7
Features ........................................................................................................................... 111
Digital IO output configuration ........................................................................................ 112
Digital IO input description .............................................................................................. 114
Test interface description ................................................................................................ 115
AD converter system ..................................................................................................... 116
9.4.5.1
9.4.5.2
9.4.5.3
9.4.5.4
9.4.5.5
9.4.5.6
9.4.5.7
9.4.6
Temperature measurement: ........................................................................................... 110
Over-Temperature detection .......................................................................................... 111
Multi-purpose IO pins .................................................................................................... 111
9.4.4.1
9.4.4.2
9.4.4.3
9.4.4.4
9.4.5
Block Diagram .................................................................................................................. 110
Supply voltage sensor filter ............................................................................................. 110
Temperature Sensor ...................................................................................................... 110
9.4.3.1
9.4.3.2
9.4.4
Phase locked loop (PLL) configuration ............................................................................. 106
Lock detection and clock monitor.................................................................................... 106
Clock Monitor .................................................................................................................. 108
1MHz and ADC Clock generation ..................................................................................... 108
Clock system ports ........................................................................................................... 109
Interrupts connections .................................................................................................... 110
AWD Ports ....................................................................................................................... 125
Interrupt connections ...................................................................................................... 126
Output drivers ................................................................................................................ 127
9.4.7.1
9.4.7.2
9.4.7.3
9.4.7.4
9.4.7.5
9.4.7.6
9.4.7.7
9.4.7.8
Features ........................................................................................................................... 127
Driver switching ............................................................................................................... 127
Block Diagram .................................................................................................................. 128
Motor control logic .......................................................................................................... 129
Motor Protection Sensors................................................................................................ 132
Output driver ports .......................................................................................................... 133
Phase to PWM alignment ................................................................................................ 134
Protection signals routing to ports and interrupts .......................................................... 134
9.4.8
Driver current sensing ................................................................................................... 136
9.5 LIN interface ............................................................................................................................... 137
9.5.1
Introduction ................................................................................................................... 137
9.5.2
LIN Physical Layer .......................................................................................................... 137
9.5.3
Application Recommendations for the pins LIN_IN and LIN_OUT.............................. 138
9.5.4
LIN special application modes ....................................................................................... 138
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
9.5.4.1
9.5.4.2
9.5.4.3
9.5.4.4
9.5.5
LIN Slave Node Position Detection (auto-configuration)............................................. 142
9.5.5.1
9.5.5.2
9.5.6
LIN BSM global timing ...................................................................................................... 142
LIN BSM local timing ........................................................................................................ 143
LIN auto-configuration block description ..................................................................... 143
9.5.6.1
9.5.6.2
9.5.6.3
10
Special application mode 1 - external physical layer ....................................................... 138
Special application mode 2 - external protocol layer....................................................... 139
Special application mode 3 - direct access from application CPU ................................... 139
LIN special modes port configuration .............................................................................. 140
Current generator............................................................................................................ 144
Current generator port interface ..................................................................................... 146
Current generator calibration .......................................................................................... 147
ESD and EMC ................................................................................................................................ 148
10.1 Automotive Qualification Test Pulses according to ISO7637-2/3 and ISO16750-2 ................ 148
10.1.1 Test Pulses on Supply Lines (directly connected to Car Battery) ................................ 148
10.1.2 Test Pulses on LINin and LINout Lines .......................................................................... 149
10.1.3 Test pulses on signal lines, incl. LININ, LINOUT ............................................................ 149
10.1.4 EMC Test pulse definition ............................................................................................. 150
10.1.5 Typical Application Circuitry .......................................................................................... 152
10.1.5.1 External Circuitry on Supply Lines.................................................................................... 152
10.1.5.2 External Circuitry on LIN Lines ......................................................................................... 153
10.1.5.3 External Circuitry on Signal Lines ..................................................................................... 153
11
12
13
14
15
Debugging Facilities...................................................................................................................... 154
Assembly Information .................................................................................................................. 154
Contact......................................................................................................................................... 156
Disclaimer .................................................................................................................................... 156
Appendix ...................................................................................................................................... 157
15.1 Detailed Ports Map .................................................................................................................... 157
REVISION 1.7 - 27. Apr 2020
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Datasheet
5 History
The following listed versions of MLX81325 specification were published to be valid. Always the highest version is
valid for the actual produced version of the IC, any older version may be used in reference to the state of
development of the IC in past. Please refer to column IC revision letter to select the matching spec version.
IC Revision
Main changes in Specification
Date Stamp
Spec
Version
MLX81325A
Initial Version
Aug. 11,
2016
REV 1.0
MLX81325A

update of ESD standard definition in Table 7.3
update of conditions, limits in Table 7.6
Sept. 29,
2016
REV 1.1


improve description in chapter Window mode

correction in chapter AWD Ports

update of portsmap - ports DRVCFG and ANA_OUTG
REV 1.2

corrections in chapters 9.4.7.6 and 9.4.7.7
June 16,
2017

parameter tTxD_to included in Table 7.5

update of parameter tWU_LIN in Table 9.1

update of some limits and conditions in Table 7.6

Testinterface description included in chapter 9.4.4

Update of port ANA_OUTA (include TRIMCPHS[3]; only valid for
MLX81325B)

Bondoption ‘ILS’ included (in chapter 3, chapter 7.3, chapter
9.1)

Update of application schematics, chapter 8

Chapter 9.4.1.3 included

2 values in Table 9.60 corrected
Port ANA_INB in Table 9.20 corrected
Dec. 19,
2017
REV 1.3


Correction in Table 9.36

Updates in Table 7.5 parameters e,g, VBOOST, ISLEEP, ErrADC,
Vadc_vsm_off, Vcs_err; some test conditions

Rework of table for LIN AutoConfig related parameter

Update in Table 9.1 parameter tWU_int

Correction of port description for XI0_MASK, XI1_MASK
Correction in Table 9.20, port ANA_OUTA
Aug. 31,
2018
REV 1.4


Corrections in chapter 9.5.6

Update values in Table 7.5 – Pre-driver resistance; condition
for IHOLD

Correction of minor errors

Correction of OV description in chapter 9.4.7 (check also bits
OV_VS)
July 29, 2019
REV 1.5

Update in chapters 9.3.1.9 and 9.4.5.1 to place ADC
tables mandatory in RAM memory

Correction for XI0_PEND/XI1_PEND in chapter 15.1

Correction of minor errors

Update order codes in chapter 3
MLX81325A
MLX81325B
MLX81325B
MLX81325B
MLX81325B
REVISION 1.7 - 27. Apr 2020
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
IC Revision
Main changes in Specification
Date Stamp
Spec
Version
MLX81325B

Update order codes in chapter 3
Update Marking in chapter 7.2, 7.3.1 and 7.3.2
Sept 09,
2019
REV 1.6


Insertion of chapter to NVRAM patch mechanism 9.3.2.4.3

Correction in Equation 25
Apr 27, 2020
REV 1.7

Update Figure 7-1

Correction in Table 9.40: SPI ports – Status and Control bits 1
(Bit SPI_CPHA)
MLX81325B
6 Referred documentation
Following documents are referred to in this document:
[1] Automotive Electronics Council, "AEC-Q100 Failure Mechanism Based Stress Test Qualification for
Integrated Circuits", AEC-Q100-REV-H, September 11, 2014
[2] LIN consortium, "LIN specification package 2.0," 2003-09-16.
[3] LIN consortium, "LIN specification package 2.1," 2006-11-24.
[4] LIN consortium, “LIN Slave Node Position Detection Implementation Note” draft rev. 0.21, 2005-10-04
[5] Mulan Documentation
[6] Mlx16x8 Data Book, Softdist download area
[7] Melexis LIN API documentation, Softdist download area
The descriptions in this document overrule the descriptions in the referred documents.
REVISION 1.7 - 27. Apr 2020
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Datasheet
7 Technical description
7.1 Package data QFN32 (5x5, 32 leads)
Figure 7-1: Package data QFN32
REVISION 1.7 - 27. Apr 2020
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
7.2 Marking instruction
81325
Part number
zzzzzz
Lot Number
Assembly Date Code: Year Week
xxx-y
Option Code
1
yyww
Silicon version; customer code; assembly house
Figure 7-2: Marking example on IC package QFN32 5x5 package
REVISION 1.7 - 27. Apr 2020
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
7.3 Pin out description
voltage
remarks and description
1
W
Pwr HV
Motor phase W
2
HSV
Pwr HV
High side driver output phase V
3
V
Pwr HV
Motor phase V
4
HSU
Pwr HV
High side driver output phase U
5
U
Pwr HV
Motor phase U
6
HST
Pwr HV
High side driver output phase T
7
T
Pwr HV
Motor phase T
8
LSW
Pwr HV
Low side driver output phase W
9
LSV
Pwr HV
Low side driver output phase V
10
LSU
Pwr HV
Low side driver output phase U
11
LST
Pwr HV
Low side driver output phase T
12
ILS
Pwr LV
Positive input of the current sensor
13
GNDM
Ground
Power and digital ground
14
GNDL
Ground
LIN ground
15
LININ
Pwr HV
LIN transceiver BUS pin, slave only, connected to master side
16
LINOUT
Pwr HV
LIN transceiver BUS pin, slave only, connected to end of bus side (for option
code 0xx)
16
ILS2
Pwr LV
Negative input of the current sensor (for option code 1xx)
17
IO7
Ana LV
General Purpose Digital I/O pins / Analog input for ADC
18
IO6
Ana LV
General Purpose Digital I/O pins / Analog input for ADC
19
IO5
Ana LV
General Purpose Digital I/O pins / Analog input for ADC
20
IO4
Ana LV
General Purpose Digital I/O pins / Analog input for ADC
21
IO3
Ana HV
General Purpose Digital I/O pins / Low/High-Voltage input for ADC, Wake up
source
22
IO2
Ana LV
General Purpose Digital I/O pins / Analog input for ADC
23
IO1
Ana LV
General Purpose Digital I/O pins / Analog input for ADC
24
IO0
Ana LV
General Purpose Digital I/O pins / Analog input for ADC
25
VDDA
Pwr LV
Regulator output (~3.3 V), external blocking capacitors
26
GNDA
Ground
Ground pin for analog
27
VDDD
Pwr LV
Regulator output (~1.8 V), external blocking capacitors for Digital part
28
VS
Supply HV
Battery supply voltage for Analog part; external protection against reverse
polarity needed, external blocking capacitors
29
CPDRV
Pwr HV
Charge pump clock
30
VSM
Supply HV
Battery supply voltage for Drivers Part; external protection against reverse
Pin
Nr
Pin
name
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MLX81325 Smart LIN Driver for small motors <100W
Pin
Nr
Datasheet
Pin
name
voltage
remarks and description
polarity needed, external blocking capacitors
31
VBOOST
Pwr HV
Charge pump voltage
32
HSW
Pwr HV
High side driver output phase W
VDDA
GNDA
VS
VDDD
VSM
CPDRV
HSW
VBOOST
7.3.1 Option code 0
W
IO0
HSV
IO1
V
IO2
HSU
IO3
MLX81325
U
IO4
HST
IO5
T
IO6
LININ
LINOUT
GNDL
GNDM
ILS
LST
LSV
IO7
LSU
LSW
Option code 0xx
Table 7.1 Pin out description 0
VDDA
GNDA
VS
VDDD
VSM
CPDRV
VBOOST
HSW
7.3.2 Option code 1
W
IO0
HSV
IO1
V
IO2
HSU
IO3
MLX81325
U
IO4
HST
IO5
T
IO6
ILS2
LININ
GNDL
GNDM
ILS
LST
LSV
IO7
LSU
LSW
Option code 1xx
Table 7.2 Pin out description 1
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Datasheet
7.3.3 Electrical Characteristics
7.4 Absolute Maximum Ratings
All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum ratings
given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding
any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device.
Reliable operation of the MLX81325 is only specified within the limits shown in “Operating conditions”.
Parameter
Battery supply voltage
Symbl
Condition
VS
t < 500 ms
VSM
VS.tr1
VS.tr2
VS.tr3
Limit
Min
-0.5
-0.5
VDDA-0.3
VDDA-0.3
-100
t < 500 ms
ISO 7637-2 pulse 1 [1]
VS=13.5V, TA=(23 5)°C
ISO 7637-2 pulse 2 [1]
VS=13.5V, TA=(23  5)°C
ISO 7637-2 pulses 3A, 3B -150
Unit
Max
28 (36V [9] )
45
28 (36V [9] )
45
V
V
V
V
V
+75
V
+100
V
125
mA
[1]
Battery supply current
IVSM_max
Output voltage
Output voltage
LIN Bus
VDDA
VDD1V8
VLIN
VBUS.tr1
VBUS.tr2
VBUS.tr3
VS=13.5V, TA=(23  5)°C
maximum DC or RMS
supply current VSM
-0.3
-0.3
-27
-100
T < 500ms
ISO 7637-2 pulse 1 [2]
VS=13.5V, TA=(23  5)°C
ISO 7637-2 pulse 2 [2]
VS=13.5V, TA=(23  5)°C
ISO 7637-2 pulses 3A, 3B -150
3.6
1.95
45
V
V
+75
V
+100
V
200
mA
VS+0.3
V
45
V
[2]
ILIN_max
Voltage on Analogue HV
VAN_HV
Voltage on PIN VBOOST
VAN_VBOOST
Voltage on Analogue HV
VAN_HSx
Voltage on Analogue HV
VAN_LSx
Voltage on pin ILS
VAN_ILS,
VAN_ILS2
VIO_LV
Voltage on IO[7:4] and
IO[2:0]
REVISION 1.7 - 27. Apr 2020
VS=13.5V, TA=(23 5)°C
Maximum current in
-200
LININ or LINOUT
IO3 with internal divider -0.3
T, U, V, W outputs[8]
switching transients at
36V motor drive
-0.3
VBOOST+0.3 V
-0.3
-0.5
VREF+0.3
V
VDDA+0.3
V
-0.3
VDDA+0.3
V
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Datasheet
Parameter
Symbl
Voltage on IO[3]
Current on IO[7:0]
Maximum latch–up free
current at any pin
VIO_HV
IIN_DIG
ILATCH
Maximum latch–up free
current at driver pins
ESD capability of pin LIN
ILATCH_driver
ESDHBM_LIN
ESD capability of pin LIN
ESDIEC_LIN
ESD capability of any other ESDHBM
pin, except LIN
ESD capability at any pin
ESDCDM
Storage temperature
Tstg
Junction Temperature
TJ
Thermal resistance MLF32 Rth
Condition
Limit
Min
-0.3
-10
according JEDEC JESD78, -100
AEC-Q100-004
@ t= 10 msec
-250
Unit
Max
VS+0.3
10
100
V
mA
mA
250
mA
Human body model,
acc. AEC-Q100-002 [7][4]
acc. IEC 61000-4-2 [6]
Human body model [7]
-6
+6
kV
-6
-2
+6
+2
kV
kV
Charge Device Model,
acc. ANSI/ESDA/JEDEC
JS-002
-500
+500
V
-55
-40
~ 32
150
175
°C
°C
K/W
in free air
[3]
Table 7.3: Absolute maximum ratings
[1]
[2]
[3 ]
[4 ]
[6 ]
[7]
[8]
[9]
ISO 7637 test pulses are applied to VS via a reverse polarity diode and >22µF/100nF blocking capacitor;
ISO 7637 test pulses for 24V car battery needs to be protected by external components;
ISO 7637 test pulses are applied to BUS via a coupling capacitance of 1nF (as required by German OEM)
ISO 7637 test pulses for 24V car battery needs to be protected by external components;
Simulated value for low conductance board (JEDEC).
ESD is applied on LIN pin against shorted GND pins
Equivalent to discharging a 150pF capacitor through a 330Ω resistor conform to IEC Standard 1000-4-2.
Equivalent to discharging a 100pF capacitor through a 1.5kΩ resistor.
In case of negative voltages applied on T, U, V, W pins, voltage can go lower than -0.3V please refer to the available application notes.
36V operation is limited to maximum 24 hours over life; 28..36V motor driving may require 100..500 Ohm resistor at Vboost pin to protect
in case of pcb switching transients >45V
REVISION 1.7 - 27. Apr 2020
Page 14 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
7.5 Operating Conditions
The IC can have 6 different hardware modes. The exact functionality of these modes depends on the hardware
and software configuration:






Reset:
 Triggered by hardware. When VS or VDDA or VDDD drop below a critical level, the complete
chip is powered down.
 The analogue and digital supply regulators are disabled. No functionality is available in this
mode.
Normal mode. Main application running
 Microcontroller fully functional
 Analogue fully functional
Power Saving Mode
 Application CPU halted
 Wake-up by interrupt.
Under voltage: triggered by the hardware under voltage detection interrupt. (VS_UV)
 Microcontroller fully functional.
 Analogue functionality under software control.
 Reduced current capability on VDDA below VS=5.5V.
Over voltage: triggered by the hardware over voltage detection interrupt. (VS_OV)
 Microcontroller fully functional
 Analogue functionality under software control.
Sleep Mode: Triggered by the software.
 Microcontroller powered down
 Digital and analogue supply powered down.
 Sleep Mode and wake-up functionality running on help supply Vaux
Parameter
Symbol
Conditions
Limit
Typ
Unit
Supply Voltage Range
VS
Min
5.5
Supply Voltage Range
Low battery
Ambient Temperature
Junction Temperature for
FLASH Program and Erase
Junction Temperature for
NVRAM Program and Erase
VS_lb
3.5[1]
Max
28
(36 [2])
5.5
TA
TJFLPR
-40
0
150
85
C
C
TJNVPR
-40
165
C
V
V
Table 7.4: Operating Conditions
[1]
[2]
IC will work down to 3.5V with reduced analogue characteristics, Digital part still works,
Memories will keep their content. Some analogue parameter will drift out of limits, but chip function can be guaranteed.
Before going down to 3.5V the VS has to be at the startup of the IC for a certain time > 5.5V to guarantee a correct reset!
The VS range below 5.5V is only characterized. No production test
IC will work up to 36V with reduced analogue characteristics, Digital part still works, Memories will keep their content. 36V operation is limited
to maximum 24 hours over life; 28..36V motor driving may require 100..500 Ohm resistor at Vboost pin to protect in case of pcb switching
transients >45V
REVISION 1.7 - 27. Apr 2020
Page 15 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
7.6 Electrical parameter specification
Following characteristics are valid over the full temperature range of Tj = -40°C to +165°C and a supply range of
28V (36V for max. 24h over life time) ≥ VS=VSM > 5.5V unless otherwise noted.
With 5.5V ≥ VS > 3.5 V the controller still works, Memories keep their contents, analogue parameters cannot be
guaranteed. The VS has to be at the startup of the IC for a certain time > 5.5V to guarantee a correct reset!
If several pins are charged with transients above VS and below VSS, the summary of all substrate currents of the
influenced pins should not exceed 10mA for correct work of the device.
All voltages refer to ground of IC, which is built by short of all existing ground pins, which were split to meet EMC
performance and lowest possible noise influence.
Parameter
Symbol
Conditions
Min
Global parameters
Normal working
current
Inom
Sleep Mode current
Isleep
Holding mode current Ihold
Frequencies
Frequency of the
frc_1M
trimmed RC oscillator
Frequency of the PLL fpll
Settling time of the
PLL
Frequency separate
10kHz RC oscillator
for the analogue
REVISION 1.7 - 27. Apr 2020
tsetpll
frc_10k
all pins are inputs, trimmed
PLL to 28 MHz; no external
loads, Normal LIN
communication
chip in sleep mode; T ≤ 150 °C
VS = 13 V, T ≤ 35 °C
VS = 13 V, T > 35 °C
VS = 18 V
VS > 18 V
all pins are inputs, chip is fully
trimmed using MLX trimming
parameters, chip in holding
mode;
only characterized; no
production test,
No motor, Mlx16 in halt
T Wake up MLX16: 25ms
ADC: 2 conversions every 25ms
Drivers: ON , CP on
MLX4: connected
Watchdog: ON
LINAA: off [9]
Limit
Typ
Max
Unit
10
30
mA
30
80
100
200
µA
µA
µA
µA
7
mA
RC oscillator is trimmed
1-5%
1
1+5%
MHz
System RC oscillator is
trimmed
RC oscillator is trimmed, PLL
is switched on
Value of Frc_10k will be
measured on MLX test and
put into the Flash;
28-5%
28
28+5%
MHz
250
µs
20
kHz
5
10
Page 16 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Parameter
Symbol
Conditions
Min
Watchdog
Temperature
dependency of the
10kHz RC oscillator
Tc_Frc_10k
Startup time of the
system after Power
On
tstartup_POR
Startup time of the
Charge pump
tstartup_CP
This value can be used for
calculation of the final
frequency of the Analogue
WD.
100%*(Frc_10k(max)-10
Frc_10k@35deg)/(Frc_10k@3
5deg)
100%*(Frc_10k(min)Frc_10k@35deg)/(Frc_10k@3
5deg)
CVDDA=100nF;
CVDDD=100nF
Time until the first Flash
instruction can be executed,
Not tested in production; for
information only
Time from CP start
(DIS_DRV=0) till
VBOOST =VS+ 6V for VS>12V;
motor not running during
startup,
Cfly=100 nF, Cboost = 1 µF
VDDA related parameters (external C: 47nF … 220nF)
3.3V supply voltage VDDA
with trimmed VBG
range
External output
Iddout_VDDA
current capability
VDDD related parameters (external C: 47nF … 220nF)
1.8V supply voltage
VDDD
after trimming
range
External output
Iddout_VDDD
current capability
VDDA based UV RESET parameters
Undervoltage reset
Vuvr_hl_VDDA
on
Undervoltage reset
Vuvr_lh_VDDA
off
Hysteresis for
Vhyst_uvr_VDDA guaranteed by design
undervoltage reset
Debouncing for UVR tuvr_VDDA
VDDD based UV RESET parameters
Undervoltage reset
Vuvr_hl_VDDD
on
Undervoltage reset
Vuvr_lh_VDDD
off
REVISION 1.7 - 27. Apr 2020
Limit
Typ
3.15
1.77
Unit
Max
10
% of
Frc_10k
3.3
1.85
20
ms
5
ms
3.45
V
25
mA
1.93
V
0
mA
2.7
2.85
3
V
2.85
3
3.15
V
0.1
V
1
3
10
µs
1.525
1.6
1.675
V
1.6
1.675
1.75
V
Page 17 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Parameter
Symbol
Conditions
Hysteresis for
Vhyst_uvr_VDDD guaranteed by design
undervoltage reset
Debouncing for UVR tuvr_VDDD
POR parameters (VS based; for information only)
POR off
Vpor_lh
only for information
POR on
Vpor_hl
only for information
Hysteresis for POR
Vhyst_por
only for information
VS – Programmable under voltage interrupt parameters (Brown out)[1]
Programmable range Vuv_range
PRUV[2:0]:
for under voltage
000
level
001
010
011
100
101
Hysteresis for under Vhyst_uv
voltage
Debouncing for under tuv
only for information
voltage
VS - Over Voltage (Load dump) interrupt related parameters
Level for load dump Vld_lh
PROV:
interrupt on
0
1
Level for load dump
interrupt off
Vld_hl
Hysteresis for load
Vhyst_ld
dump interrupt
Debouncing for load tld
dump interrupt
ADC (10Bit) related parameters
ADC full scale range fsr3
(code 0x3FF
fsr2
corresponds to fsr)
fsr1
fsr0
Differential
nonlinearity
Integral nonlinearity
DNL
INL
Quantization steps
RESADC
Minimum conversion Tconv
Time
REVISION 1.7 - 27. Apr 2020
PROV:
0
1
Min
0.05
1
Limit
Typ
Unit
Max
V
3
10
3.6
3.15
µs
V
V
mV
60
3.5
4.5
5.5
6.5
7.5
8.5
0.1
4
5
6
7
8
9
4.5
5.5
6.5
7.5
8.5
9.5
1
V
V
V
V
V
V
V
10
30
60
µs
31.5
37
33
38.5
34.5
40
V
V
29.5
34.5
31
36
32.5
37.5
V
V
1
2
3
V
100
µs
2.55
1.53
0.765
V
V
V
V
-1
+1
LSB
-3
+3
LSB
only for information
50
ADC_REF[1:0]=11
ADC_REF[1:0]=10
ADC_REF[1:0]=01
ADC_REF[1:0]=00
ADC reference disabled
only characterized; no
production test
only characterized; no
production test
guaranteed by design
frequency = 2MHz
frequency = 4MHz
guaranteed by design
2.45
1.47
0.735
2.5
1.5
0.75
off
1024
LSB
µs
6
3
Page 18 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Parameter
Symbol
Minimum sampling
time
Tsamp
Minimum time
between 2 ADC
conversions
Tcycl
ADC error (excluding ErrADC
ADC reference and
INL)
Conditions
Min
Time between channel select 3
and start of conversion (4
MHz)
guaranteed by design
Tcycl = Tsamp + Tconv (for
6
4MHz) w/o channel change
Tcycl = Tsamp + Tconv (for
7
4MHz) with channel change
guaranteed by design
LV channels
-1
HV channels (with predivider) -3
IO[7:0] related parameters
Leakage current in
Ileakio[7:0]
1/16 divider on IO3 disabled. -5
IO[7:0]
Fast Digital Input; (not active in SLEEP MODE)
Digital input
Vinhio[7:0]
threshold level L => H
Digital input
vinlio[7:0]
threshold level H => L
1
Digital input
Vinhystio[7:0]
Hysteresis
Digital Input for WAKE UP on IO3 (VAUX supplied)
Vinlhio_wu
Digital WU input
Active in SLEEP MODE
threshold level
L => H
0.1
Digital WU input
threshold level
H => L
Vinhlio_wu
Hysteresis
Vhystio_wu
µs
µs
1
%
3
%
5
µA
2.4
V
V
V
V
Active in SLEEP MODE
1.2
0.1
VouthIO[7:4, 2:0] Iload = 2mA
Low Voltage Push-Pull Stage of IO3 (not active in SLEEP MODE)
Output voltage low
VoutlIO[3]
Iload = 1mA, SPI_EN = 1;
SPIOUT = 0
Output voltage high VouthIO[3]
Iload = 1mA, SPI_EN = 1;
SPIOUT = 1
IO Voltage Range for ADC measurement
Input Voltage Range Vin_adc_IO[7:4,
for ADC measurement 2:0]
REVISION 1.7 - 27. Apr 2020
Unit
Max
2.7
Low Voltage Push-Pull Stage of IO7..4, IO2..0 (not active in SLEEP MODE)
Output voltage low
VoutlIO[7:4, 2:0] Iload = 2mA
Output voltage high
Limit
Typ
For information only
V
0.4
VDDA 0.4
V
0.4
VDDA 0.4
0
V
V
V
2.5
Page 19 of 182
V
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Parameter
Symbol
IO3_HV Input Voltage Vin_adc_IO3
range for ADC
measurement
Temperature Sensor related parameters
Temperature Shutdown circuit
Over temperature
Tot_on
shutdown interrupt
Tot_off
Conditions
For information only
Measurement of V(IO3)/16
tested by special test mode
only
Min
0
Limit
Typ
Unit
Max
36
V
170
180
190
C
140
150
160
C
10
guaranteed by design
Temperature Sensor (for ADC measurement)
Temperature range
Trange
Sensor measures IC junction -40
temperature
Temperature
TEMP_GAIN
measurement gain
Accuracy
Tacc
Measurement error versus
-10
absolute Junction
temperature after calibration,
guaranteed by design
VSM Sensor related parameters
C
Tot_hyst
Input range
Output Capability
VS_min
180
C/LSB
0.5
10
@ ADC_REF[1:0]=11
@ ADC_REF[1:0]=10
@ ADC_REF[1:0]=01
@ ADC_REF[1:0]=00
Tsettling_ADC
Time to charge the ADC
sampling cap,
only characterized; no
production test
C
V
5.5
VS_max
C
0.3
36
24
12
off
V
0.5
µs
Low-Pass Filter cut-off Fvs_filter
frequency (@VSM)
-3dB cut=off frequency, only
characterized; no production
test
0.7
1.5
kHz
VSM sensor filter
Offset
Referred to input voltage
(VSM)
-400
400
mV
9
V
Vadc_vsm_off
Motor Driver related parameters
Bottom pre-driver
FET Gatedrive voltage VREF
Ron charge
REVISION 1.7 - 27. Apr 2020
R_LS_HIGH
Assured output voltage when
VSM ≥ 7 V
6
5.5 V < VSM < 7 V
If no undervoltage detected
VSM - 1
VS=VSM = 8V…36V
Tested at 13V in production
10
8
V
30
60
Page 20 of 182
Ohm
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Parameter
Symbol
Conditions
Min
Limit
Typ
Max
Unit
Ron discharge
R_LS_LOW
VS=VSM = 8V…36V
Tested at 13V in production
10
25
50
Ohm
Top pre-driver
Ron charge
R_HS_HIGH
VS=VSM = 8V…36V
Tested at 13V in production
8
40
80
Ohm
Ron discharge
R_HS_LOW
VS=VSM = 8V…36V
Tested at 13V in production
8
40
80
Ohm
Charge Pump
Charge pump output
voltage
VBOOST
VSM + 7 VSM + 8
VSM ≥ 10 V
VSM + 5.5
8 ≤ VSM < 10 V
VSM + 3
5.5V < VSM < 8 V (BAT54S only,
Tj<=150degC)
IloadVBOOST ≤ 3 mA
VSM + 9.5
VSM + 9.5
VSM + 8
V
V
V
Ohm
(Charge pump diodes BAV99 or
BAT54S, Tj<=150°C); production
test with BAT54S
CPDRV output
resistance
R_CPDRV_HIGH
R_CPDRV_LOW
CP output frequency CP_FREQ
Dead Time for FET switching
Dead Time
T_DEAD
Motor Current Sensor parameters
Current sensor input V_CURR_IR
range
Iload=2mA
Tested at 13V in production
15
40
120
10
26
60
40
50
60
Programmable with 3 bits.
ANA_OUTG[4:2]
000
001
010
011
100
101
110
111
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
Acs
Current sensor
reference
Vcs0
V(ILS) = 0
Current sensor
calibration error
Vcs_err
measured at the output of the -20
current sensor (ADC input)
Current sensor low
tcs_filter
Guaranteed by design
REVISION 1.7 - 27. Apr 2020
µs
µs
µs
µs
µs
µs
µs
µs
Allowed input range of shunt -100
voltage (eg. 100 mOhm shunt:
1A = 100mV)
For information only
Current sensor Gain
9.5
100
10
0.5
mV
10.5
1.25
0.25
kHz
V
20
mV
1
µs
Page 21 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Parameter
Symbol
Conditions
pass filter time
Limit
Typ
Max
Unit
260
300
330
mV
1
2
4
8
1.5
3
6
12
2
4
8
16
µs
µs
µs
µs
1.5
2
2.5
V
Typical RC is formed with
R = 40kOhm and C = 5pF
Overcurrent detection (via comparator)
Short circuit detection Voc
level
Debouncing for OC
Toc
Digital filter based on RC
clock
Programmable with 2 bits.
DEB_OC[1:0]
00
01
10
11
External FET monitoring
Detection level
Vds
Filter Time
Min
Vds over voltage level when
FET is on
Tvds
Time from Fet on till Vds
monitoring start.
Programmable with 2 bits.
IO:VDS_MASKTIME[1:0]
00
01
10
11
1.6
3.2
4.8
6.4
µs
µs
µs
µs
LIN AutoConfig related parameter (TA =0°C. ... 50°C, characterized; production test @35°C)
Functional range LIN
auto-addressing
VS
TA=0°C … 50°C
9
-
15
V
Bus pull-up source 1
for auto-addressing
PRE-Selection Phase -
IPU,AA,PRE,1
VBUS=0V … 2.5V
-0.75
-0.40
-0.15
mA
Bus pull-up source 2
for auto-addressing
Selection Phase
IPU,AA,SEL
VBUS=0V … 2.5V
-2.26
-2.0
-1.84
mA
BUS voltage range
VBUS
0
-
2.5
V
PRE-Selection phase
current threshold
ITH_PRE
1.0
1.2
1.4
mA
Selection phase
current threshold
ITH_SEL
1.0
1.2
1.4
mA
Shunt between LIN_IN & LIN_OUT (TA < 50°C, characterized; production test @35°C)
REVISION 1.7 - 27. Apr 2020
Page 22 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Parameter
LIN shunt resistor
Symbol
Conditions
Rshunt (internal)
Min
Limit
Typ
Max
Unit
0.61
0.78
0.96
Ω
200
300
60
mA
LIN related parameters ISO_DIS_17987-4 , SAE J2602, 8V ≤ VBAT ≤ 18V.
DC Parameters
Transmitter
Short circuit bus
current
Pull up resistance
bus,
normal & standby
mode [8]
Pull up current,
SLEEP MODE
Input Leakage at the
receiver incl. PU
Bus reverse current,
recessive
IBUS_LIM
RSLAVE
ILIN_PU-Sleep
IBUS_PAS_dom
IBUS_PAS_rec
Bus reverse current
loss of battery
IBUS_NO_BAT
Bus current during
loss of ground
Transmitter
dominant voltage
Transmitter
recessive voltage
BUS input
capacitance;
MLX Value for LIN
conformance test
Receiver
Receiver dominant
voltage
Receiver recessive
voltage
Centre point of
receiver threshold
Receiver Hysteresis
IBUS_NO_GND
AC Parameters
Propagation delay
receiver [2], [3], [6]
Propagation delay
receiver [2], [3], [6]
REVISION 1.7 - 27. Apr 2020
VBUS = VBAT = 18V, driver on
VBUS = VBAT = 36V , driver on
VolBUS
VohBUS
CBUS
VBUS=0, VBAT=12V, SLEEP
MODE
VBUS=0, VBAT=12V
VBUS=0, VBAT=24V
driver off,
8V<VBAT≤27V,Tj>=150degC
27V<VBAT<36V,
VBUS > VBAT
VS = 0V, 0V < V BUS < 18V
18V < VBUS < 36V
LIN 2.1
VS=VGND=12V, 0 < VBUS < 18V
VS=VGND=24V, 0 < VBUS < 36V
network load =500Ω /
TxDx = 0
TxDx open
40
75
20
-100
µA
-1
-2
mA
20
50
µA
23
100
µA
-1
-2
0
1
2
0.2
mA
0.8
1
VS
35
pF
0.4
VS
1
25
Pulse response via 10k,
VPULSE = 12V,
VS open
VBUSdom
VBUSrec
VBUS_CNT
VBUS_hys
trx_pdf
trx_pdr
0.6
VBUS_CNT=( VBUSdom+
VBUSrec )/2
VBUS_cnt =( VBUSrec VBUSdom)
CRxD =25pF
falling edge
CRxD =25pF
rising edge
kOhm
0.475
0.15
VS
VS
0.5
0.525
VS
0.175
VS
6
µs
6
µs
Page 23 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Parameter
Symbol
Conditions
Prop. delay receiver
symmetry [6]
Receiver debounce
time [7]
LIN duty cycle 1 [3] [4]
trx_sym
trx_pdf - trx_pdr
Min
-2
trec_deb
LIN rising & falling edge
0.5
D1
0.396
LIN duty cycle 2 [3] [4]
D2
LIN duty cycle 3 [3] [4]
D3
LIN duty cycle 4 [3] [4]
D4
trec(max) –
tdom(min) [5]
trec(min) –
tdom(max) [5]
TxD dominant
timeout [6]
Δt3
20kbps operation ,
normal mode
20kbps operation ,
normal mode
10.4kbs operation ,
low speed mode
10.4kbs operation ,
low speed mode
10.4kbs operation ,
low speed mode
10.4kbs operation ,
low speed mode
Normal mode, VTxD = 0V
Δt4
tTxD_to
Limit
Typ
Unit
Max
2
µs
4
µs
-
0.581
0.417
-
0.590
-
15.9
µs
17.28
µs
64
ms
Table 7.5: Electrical parameters
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
PLL should be switched off at brown out condition. Analog parameters are not guaranteed during brown out.
This parameter is tested by applying a square wave signal to the LIN. The access to internal signals RxD,TxD will be performed by test mode. The
minimum slew rate for the LIN rising and falling edges is 50V/µs.
See figure 1: LIN timing diagram
Standard loads for duty cycle measurements are 1KΩ/1nF, 660Ω/6.8nF, 500Ω/10nF, internal termination disabled
In accordance to SAE J2602
Parameter in relation to internal signal TxD
Internal MLX value to suppress spikes; only proved during characterisation: not measured in production
The pull-up resistance is always connected to the LIN-bus; Only when LIN Auto-addressing firmware code is included, the pull-up can be
disconnected during the LIN Auto-Addressing sequence
IHOLDmax increases by ~0.5mA in case LINAA is switched on.
As shown in figure, both worst case duty cycles can be calculated
as follows :
Dwc1 = tBUS_rec(min) / 2 * tBit
Dwc2 = tBUS_rec(max) / 2 * tBIT
Thresholds for duty cycle calculation in accordance to LIN2.x:
Baud rate
20kBaud
10.4kBaud
tBit
50µs
96µs
Dwc1
D1
D3
Dwc2
D2
D4
THREC(MAX)
0.744 VS_TX
0.778 VS_TX
THDOM(MAX)
0.581 VS_TX
0.616 VS_TX
THREC(MIN)
0.422 VS_TX
0.389 VS_TX
THDOM(MIN)
0.284 VS_TX
0.251 VS_TX
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Figure 7-3: LIN timing diagram: Relation between propagation delay and duty cycle
8 MLX81325 – Typical application schematic
In the following schematic example, all external components are indicated that are needed to protect the IC
against EMC / ESD pulses.
VBAT
VSM
MLX81325
VS
CPDRV
VBOOST
GND
LIN_IN
LIN_OUT
GNDL
HSW
HSV
HSU
HST
LININ
LINOUT
BLDC motor
connections
T
U
V
W
VDDD
VDDA
U
V
W
LST
LSU
LSV
LSW
ILS
GNDA
IO[7:0]
GNDM
Figure 8-1: Typical BLDC motor schematic with MLX81325
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The following schematic is an example for a differential shunt measurement of the external current. All external
components are indicated that are needed to protect the IC against EMC / ESD pulses.
VBAT
VSM
MLX81325
VS
CPDRV
VBOOST
GND
LIN_IN
LIN_OUT
GNDL
LININ
LINOUT
VDDD
VDDA
GNDA
IO[7:0]
HSW
HSV
HSU
HST
BLDC motor
connections
T
U
V
W
U
V
W
LST
LSU
LSV
LSW
ILS
ILS2
GNDM
Figure 8-2: Typical BLDC motor schematic with MLX81325 with bond option 1xx (differential shunt
measurement)
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9 Functional description
9.1 Block-Diagram
VDDA
VDDD
VS CPDRV VBOOST VSM
GNDA
Supply System
Digital WD with
separate RCO
Overtemp
detection
Charge Pump
3.3V / 1.8V
POR
VDS
COMP
IO7
IO ports
IO6
IO5
IO4
HST
HSU
HSV
HSW
Aux. Supply
IO0, …, IO7
Temperature
LIN Rx-Tx
access
Vs, Vsm
LIN ACFG
Mux
28:1
VREF
10-bit ADC
Autosequence
Idrv
T
U
V
W
Vt, Vu, Vv, Vw
IO3
IO2
IO1
IO ports
Wake-up
SPI
COMP
Idrv
OC_DRV
OPA
IO0
LST
LSU
LSV
LSW
GNDM
ILS
ILS2 (bond option 1xx)
5x PWM timer
Temp Sensor
PWM control
Supply Sensor
PWM clock
generation
Auto-config
HW multiplier
co-processor
LINOUT
(bond option
0xx)
OC_DRV
GNDL
Interrupt
controller
RC- osc.
+ PLL
f main
2 Kbyte
Flash
SPI
Common Timer
Appl CPU
MLX16
M
M
U
32 Kbyte
ROM
16 Kbyte
NVRAM
4x128 Bytes
Melexis
Integrated LIN
Controller
(Protocol
Boot Loader)
LIN- PHY
RAM
Digital
watchdog
VDS
LININ
16bit
bitTimer
TimerUnits
Units
16
withDouble
Double
with
CaptureCompare
Compare
Capture
Multi-CPU
debugger
NV Memory
program interface
Test Controller
Figure 9-1: Functional block diagram
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9.2 System behavior description
The following chapter describes the behaviour of the MX81325 under normal and special conditions. At first,
entering and leaving RESET has to be done carefully by API. Initialization of the system as well as saving any
needed data later to memory is the precondition to keep application running correctly.
9.2.1 The supply system of MLX81325
Inside MLX81325 a set of different supplies deliver voltage to various parts of the system. The following section
describes how different supplies are used.
 IC supply voltage VS
The car battery voltage VBAT is connected via the Reverse Polarity Diode to the IC Supply voltage VS.
A big capacitor in range of several µF on VS is needed in case of VBAT brake down. This capacitor is important to
guarantee a certain remaining charge for writing the non-volatile Memory.
A small capacitor of about 100 nF is needed to stabilize VS for emission reasons, to insure a stable application in
case of negative transients.
 Auxillary supply VAUX
This internal voltage supplies those blocks of the MLX81325, which are basically used to control the main
supplies (VDDA,VDDD), SLEEP MODE, reset etc. VAUX is always active as long as enough voltage on VS is
available. Any blocks needed in SLEEP MODE are supplied by this voltage.
 Analogue Supply VDDA
This voltage supplies the analogue part of the MLX81325. It is switched off during SLEEP MODE. The regulator is
designed for an external capacitor in the range of 47 nF … 220 nF.
 Digital Supply VDDD
This voltage supplies the digital part of the MLX81325. It will be switched off during SLEEP MODE.
The regulator is designed for an external capacitor in the range of 47 nF … 220 nF.
It is not allowed to use this voltage to supply external components (Iddout_VDDD = 0 mA).
9.2.2 Power On
The following block diagram shows an overview over the different Power supplies and the reset circuits:
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VS
VDD
VDD
VDD
Regulator
VAUX OUT
(2 … 3.6V)
Regulator
VDDD OUT
(1.85V)
Regulator
VDDA OUT
(3.3V)
TRIMVDDA
TRIMVDDD
VDD
Bandgap
VBG
(1.2xV) OUT
VDD
UV_VDDA
VDD
POR
IN VLH:3.6V OUT
VHL:3.15V
IN
UV_VDDD
OUT
VLH:3V
VHL:2.85V
IN
OUT
VLH:1.675V
VHL:1.6V
TRIMBGP
UV_VDDD
UV_VDDA
POR
MRB
Figure 9-2: power-on block diagram
After connecting power to VS pin (assuming any needed external components are applied correctly) the system
will start to work. The on-chip supplies start to build the system voltages after reaching the defined minimum
voltage level on VS pin.
The MRB (for Master Reset, low active) is a digital signal which keeps the complete IC in reset state, as long as
one of the supplies is below the specified value.
MRB is active after Power On VS under the following condition
 as long as VS stays below the POR level (Vpor_lh) or
 as long as VDDA stays below its under voltage reset level (Vuvr_lh_VDDA) or
 as long as VDDD stays below its under voltage reset level (Vuvr_lh_VDDD).
VS
VDDA
Vuvr_lh_VDDA
VAUX
Vpor_lh
Vuvr_lh_VDDD
VDDD
t
tdelay
EN_REG
PORB
UVB_VDDD
UVB_VDDA
MRB
t
Figure 9-3: power on sequence
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With rising edge PORB after VS ramping up, the bandgap and the undervoltage detection circuits for VDDA and
VDDD are switched on. After a built in delay time of typ.150 µs the bandgap has reached the valid voltage level
and the regulators for VDDA and VDDD are switched on. If VDDA and VDDD are above the undervoltage levels
the Master Reset is switched off (MRB = 1) and the system starts to work.
For an external capacitor of 100 nF at the pins VDDA and VDDD a typical startup time of the system is about 1ms.
9.2.3 Power Off
When VDDA or VDDD are below the under voltage levels, MRB is set active which disables all functions of the
chip.
If VS drops below its POR level, it will disable the VDDA and VDDD regulator and set the MRB active.
In case of application relevant data has been changed in the RAM area of the NVRAM and the power supply is
going down, API has to start immediately saving values into NVRAM.
The available time for this save operation is limited by the energy of the external capacitor at VS.
Note that too short save operations can cause invalid data in the memory.
Saving data in NVRAM can be triggered by the under voltage interrupt or by measuring the VS with the ADC.
9.2.4 System initialization and Trimming
For correct system startup some analog registers in the IO part will be restored after every RESET or WAKE UP by
writing with values taken from the nonvolatile memory.
These values have been stored during Melexis chip test. The defined addresses are reserved for Melexis and it is
not allowed to be changed by API. Please see also the memory map for details, what parameters are stored
under what addresses.
Startup steps:
1. Trimming of the bandgap
2. Trimming of the VDDA supply voltage
3. Trimming of the VDDD supply voltage
4. Trimming of the Biasing
5. Trimming of the RC Oscillator
6. Trimming of Watchdog RC Oscillator
7. Trimming of the ADC Reference voltages VRH1..3
8. Trimming of current sensor
9. Configure PLL
9.2.5 Entering SLEEP MODE (GO TO SLEEP MODE = GTSM)
The SLEEP MODE of MLX81325 is enabled by a write to a special port location. This mode is used to save power
by switching off any not needed function, keeping only some minimum parts alive, which will watch events or
conditions for possible WAKE UP requests. To enter SLEEP MODE the following sequence has to be performed:
API takes first care of saving any needed data into non-volatile memory, because SLEEP MODE will force system
to switch off power supplies. Any register content of CPU, the content of volatile memories etc get lost. So API
should prepare the system to store information needed after restarting by WAKE UP or next Power On.
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The API starts the system shutdown process by stopping the communication and application CPU
(M4_RB = 0, HALT = 1 and setting GTSM = 1).
Note that the system shutdown cannot be canceled by any wake-up mechanism as long as the process is not
completed.
With rising edge of GTSM the following sequence is started:
 GTSM is filtered, must be 25µs…50 µs high
 Internal GTSM pulse is generated
 Bandgap (VBG), undervoltage detection circuits and regulators for VDDA and VDDD are switched off.
 System is in SLEEP MODE
 WAKE UP is possible by LIN, external pin IO3 or internal WAKE UP timer.
9.2.6 WAKE UP from SLEEP MODE
Before sending SLEEP MODE request API has to ensure, that in minimum one WAKE UP source is enabled,
otherwise only LIN activity or POR via VS can restart from SLEEP MODE.
After WAKE UP the software starts identically as after power on.
There are 3 different sources for a WAKE UP:
 A falling edge on the LIN bus, followed by a dominant voltage level for longer than the specified
value (twu_LIN) and a subsequent rising edge will cause a wake up.
If the Sleep mode was initiated by a short on the LIN (failure), and the short was removed
afterwards, the LIN wakes up immediately by the next rising edge.
The integrated filter prevents a WAKE UP via EMC interferences.
 Falling and Rising edge on digital input IO3 (with debouncing).
 The configurable internal WAKE UP timer.
The source of the WAKE UP can be read from register 0x281E:
 Bit 8 - LIN wake up
 Bit 9 - IO3 wake-up
 Bit 10 - Internal wake-up timer
For an external capacitor of 100 nF at the pins VDDA and VDDD a typical startup time of the system out of SLEEP
MODE is about 1 ms.
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Vuvr_lh_VDDD and Vuvr_lh_VDDA
VDDA
VAUX
VDDD
VBG
t
WAKEUP
MRB
VBG_ON,
UV det. on
VDDA_ON
VDDD_ON
GTSM
t
Figure 9-4: wake-up
Parameter
Symbol
Conditions
Min
Limits
Typ
Unit
Max
Wake up related parameters
Wake up filter time pin
IO[3]
tWU_IO[3]
SLEEP MODE, IO[3] rising
& falling edge
25
50
µs
Wake up filter time pin LIN tWU_LIN
SLEEP MODE,
LIN rising & falling edge
30
150
µs
Internal WAKE UP Timer
SLEEP MODE,
Programmable via 2 Bits
(INT_WU[2:1]);
tWU_int
0.4
0.8
1.6
s
Table 9.1: wake-up parameters
9.2.7 Entering HOLD MODE
With the halt command instead of SLEEP with DIS_GTSM (0x28CC, bit 0) set to 1 system goes to HOLD mode –
CPU is frozen, all supplies and configurations are kept, all memories keep their content, all timers, PWMs,
interrupts are working in accordance to initial configuration, ADC routine ongoing, all analogue cells are working
in accordance to their configuration, This mode is used for motor holding when no rotation and no control
needed while DRIVERs must be active.
9.2.8 Releasing HOLD MODE
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Any interrupt will remove HALT from CPU, thus system will go back to normal operation mode. Pay attention that
system is not in SLEEP MODE, thus wake up events will be ignored.
9.2.9 System behaviour in case of different undervoltage conditions
The following table shows an overview, how the MLX81325 behaves, if the different voltages have the following
values:
VS
VDDA
VDDD
System behaviour
VS > 5.5 V
> Vuvr_hl_VDDA
> Vuvr_hl_VDDD
Normal working range
3.5 ≤ VS < 5.5 V
> Vuvr_hl_VDDA
> Vuvr_hl_VDDD
Under Voltage
Digital part fully functional.
Current consumption on VDDA should
be limited by software.
Analog parameters cannot be
guaranteed.
≥ 3.5 V
≤ Vuvr_hl_VDDA
X
Reset: MRB=Low; VAUX is still on;
analogue and digital parts are in reset
State
≥ 3.5 V
X
≤ Vuvr_hl_VDDD
Reset: MRB=Low; VAUX is still on;
analogue and digital parts are in reset
State
2.5 ≤ VS < 3.5 V
X
> Vuvr_hl_VDDD
reduce analog and digital current
consumption as much as possible
Chip function cannot be guaranteed.
RAM content is kept
Table 9.2: under-voltage conditions
9.3 Digital Part
9.3.1 CPU core MULAN3 – MULtiple CPU with Analog and Network support
The MLX81325 is designed with the Melexis 4 Bit / 16-Bit-Risc-CPU MULAN3.
For more information regarding the MULAN3 (CPU architecture, instruction set, register set, addressing modes
etc.) see the references in chapter 6.
The MULAN3 core has included the Mlx16x8 co-processor for fast multiplication and division of 32bit values (for
further information see [6]).
9.3.1.1 MULAN3 compared to MULAN2
MULAN3 is the 100% function compatible to MULAN2.
The differences are in memory organization and interrupt vectors for the system level interrupts, i.e.
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







MULAN3 adds 16K byte ROM. The power up code and the SW for the LIN-CPU (MLX4) is executed
from ROM. The ROM contains a boot loader supporting flash reprogramming over LIN and will be
provided by Melexis in a software platform.
the ROM will be located at addresses C000 to FFFF, 8K is used by MLX4 (C000 to DFFF), 8K by MLX16
(E000 to FFFF)
MULAN3 will include a BIST block for testing the ROM
the far page 6 (FP6) will be pointing into ROM at address FF00
MULAN3 redirects all level 0 interrupts (reset, Stack, Protection Error, Invalid Address, Program
Error) into ROM (to FP6)
MULAN3 changes the interrupt type of Protection error, Invalid Address Error and Program Error (=
flash error) type to JUMP (instead of CALL)
port bits are added to control the relocation of MLX4 code from ROM to FLASH (in CONTROL_EXT2
port)
port bits are added to determine the access priority for reading the ROM from MLX4 or MLX16 (in
CONTROL_EXT2 port)
9.3.1.2 MULAN3 CPU Performance
The system clock of the MLX81325 is based on a main clock up to 32MHz (internal RC oscillator with PLL). Except
for the debouncing times for some WAKE UP sources from standby mode and the digital watchdog, all timings
are derived from this system clock.
The startup configuration is 28MHz to guarantee safe work under all conditions. ROM code is adapted to that
28MHz.
PLL Frequency
T junction
28 MHz (+/-5%)
165 C
30 MHz (+/-5%)
150 C
32 MHz (+/-5%)
100 C
Table 9.3: Temperature dependency of max. PLL frequency
9.3.1.3 Change PRIO MLX4/MLX16
“SEL PRIO” bit (0x2054, bit 0) can lower the priority of MLX4 for DMA and increase the priority of MLX16 in order
to gain CPU power on MLX16. “SEL PRIO” bit is set by default ‘0’ giving the priority to MLX4. When set to ‘1’ the
MLX16 gets priority over the MLX4 meaning the MLX16 will execute his main instructions in 4Tclk. MLX4 will
execute in 3 or 4 Tclk. This bit can be set to ‘1’ before start of the main application and before start of the LIN
application
Identical approach had been selected for ROM access priority controlled by the bit "ROM_PRIO" in the port
CONTROL_EXT2, address 0x205F, bit0. "ROM_PRIO"='0' (=reset value) gives MLX4 the priority on ROM accesses,
setting it to '1' will prefer MLX16 over MLX4.
9.3.1.4 MULAN3 Architecture
The architecture of MULAN3 is shown on the figure below.
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RB
System
Clock
Custom digital and analog
Test
controller
Mlx16
periphery
Mlx4
periphery
Mulan3
Interrupt
controller
NVRAM
Mlx16-(X)8
CPUs
interface
Mlx4
ROM
Flash
Arbiter
RAM
arbiter
ROM
Flash
RAM
Mlx4 - Mlx16 shared resources
Figure 9-5: MULAN3 architecture
This architecture has been selected for the following reasons:
 separation of protocol load from application software load by 2 processors
 keeping the protocol adaptable to different revision by software solut ion
 protocol safety is implemented, the risk to crash the communication by a software error in the
application software is minimized
 full CPU power of the MLX16x8 for application
 flash in application through LIN or SPI possible
9.3.1.5 MULAN3 Address space
Mlx4 and Mlx16 share a common ROM/Flash and RAM. From the 2 CPUs a unified 16 bits bus is created (Von
Neumann architecture). The ROM/Flash, the RAM, the NVRAM and the Mlx16-(x)8 peripherals are hooked on this
bus. Two arbiters are in charge of creating a unique memory address and corresponding access signals for
ROM/Flash and RAM.
Notes:
 The NVRAM is only accessed by the Mlx16, so it does not need an arbiter.
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9.3.1.6 Memory mapping
The unified 16 bits bus is accessing devices as shown on the table below:
Memory space
ROM
(16k Byte)
E000
-
FFFF
C000
-
DFFF
6000
-
BFFF
4000
3000
2800
2000
1200
1180
1100
10FE
1080
1000
0800
0000
-
5FFF
3FFF
2FFF
27FF
1FFF
11FF
117F
10FF
10FD
107F
0FFF
07FF
FLASH
(32 kByte)
Not Used
Mlx16 User ports
Mlx16 System Ports
Not used
NVRAM Melexis Area
NVRAM / NVRAM
NVRAM Melexis Data
NVRAM / NVRAM
NVRAM / NVRAM
Not used
RAM (1)
8k
MLX16
8k
MLX4 + MLX16
24k
System Write
To
User Write
From
Size
in used by
Bytes
MLX16 Fetch
Allowed
MLX16
8k
MLX4 + MLX16
2k
2k
MLX16
MLX16
(2)
128
128
2
126
128
2k
MLX reserved
MLX16
MLX reserved
MLX16
MLX16
MLX4 + MLX16
(2)
(1)
(1): See RAM sharing for Mlx4-Mlx16 distribution and protection
(2): Fetch enabled in this area for patch codes (Mlx16)
Figure 9-6: memory map
There are some restrictions for accessing certain areas depending on the type of access:




Mlx4 can fetch anywhere from physical addresses 0x4000 to 0x5FFF (12 bits word address)
Mlx16 can on fetch in:
 ROM/FLASH:
Normal case
 RAM:
For test purposes
Mlx4 and Mlx16 can read any RAM location (limited to 256 bytes for Mlx4)
Mlx4 and Mlx16 have specific rules for writing in RAM
The predefined pages of the Mlx16-(x)8 are encoded as shown on the table below.
Name
Address in 32K Flash size
Note
Fp0:
BF00
Last FLASH / ROM page (used by interrupt controller)
Fp1:
BE00
Could be used for C runtime
Fp2:
BD00
Could be used for C runtime
Fp3:
BC00
Could be used for C runtime
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Name
Address in 32K Flash size
Note
Fp4:
BB00
Could be used for C runtime
Fp5:
BA00
Could be used for C runtime
Fp6:
FF00
ROM for Level 0 interrupts
Fp7:
1000
NVRAM
Dp:
0000
Mlx16 private RAM
Io:
2800
User Ports
Ep:
1000
NVRAM (First page)
Table 9.4: predefined pages
9.3.1.7 MULAN3 included periphery – 15bit Timer
The timing generation principle is shown on Figure 9-7.
1 MHz derived from fPLL
Programmable
Counter
from 1 to 32768
TIMER _IT (*)
( 1µs to
32768µs)
1
15
Port TIMER
(*) : Can be disabled by interrupt
controller
Figure 9-7: Timer
A 15 bits free running counter clocked by 1MHz (refer to 9.4.1.5) is available to generate TIMER_IT interrupt at a
rate varying from 1µs (TIMER [14:0] = 0) to 32768µs (TIMER [14:0] = 32767). The timer is made of a down
counting loadable binary counter. It is enabled by TMR_EN (bit 15) of port TIMER. Once enabled, each time it
reaches 0x0000; it is reloaded by the value of port TIMER [14:0] and generates a TIMER_IT interrupt. Reading
port TIMER reads the current value of the counter when TMR_EN = 1 or an unknown value when TMR_EN = 0.
IO port: TIMER
Address: 2806-2807h
Bit[7]
Bit[6]
Access mode: Word, byte – Read
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
TIMER[7:0]
Bit[15]
Bit[14]
TMR_EN
Bit[13]
Bit[12]
Bit[11]
TIMER[14:8]
Table 9.5: IO port TIMER
The generation of long timer delays can be done in software.
The timer should be disabled before being reloaded.
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9.3.1.8 MULAN3 included periphery - Watchdog
9.3.1.8.1 Introduction and features
The MULAN3 core contains a separate watchdog (WD) running on a 250 kHz clock derived from the MULAN3
main clock.
It can work in one of the following main modes:
 Simple timer Watchdog
 Window Watchdog
 Intelligent Watchdog
The timeout delays programmable in wide range by using a clock pre-divider
The WD outputs are only interrupts.
9.3.1.8.2 Applications
The Watchdog block is used in association with the MLX16. According to the selected mode the block waits for a
MLX16 acknowledge between different time limits, or else a System reset interrupt is generated.
A MXL16 acknowledgement resets the internal WD counter.
 In the Simple Timer mode:
the Watchdog it is a resettable free-running up counter. The acknowledge signal should appear
before the internal WD counter reaches a predefined timeout value.
 In Window mode:
the WatchDog is a resettable free-running up counter. The acknowledge signal should appear only
within a time window starting at half the predefined timeout value.
 In Intelligent WatchDog mode:
the WatchDog can have its counter programmed with different values.
When the predefined timeout value is reached, an WD attention interrupt is generated and then
A new waiting sequence starts. The acknowledge signal should appear before the end of this second
sequence.
The WD attention interrupt and the System reset interrupt will be used by the software.
9.3.1.8.3 Block diagram and description
The functional block diagram of the Watchdog block is shown in Figure 9-8.
WD_MODE
WD_TO
WD_DIV
WD_CNT
CK250K
Clock
prescaler
8 bits counter
Reset
User Mode (from CPU)
WD_TG
Timeout Unit
- mode control
- timeout generation
- window checking
- protection mode
checking
WD Reset Interrupt (SYS_WD_RST)
WD Attention Interrupt (WD_ATT)
Protection Error Intrrupt (SYS_PROT_ERR)
WD_ERR
WD_WND
Figure 9-8: Functional diagram of the Watchdog block.
The WatchDog mode, simple timer, window or intelligent is selected via the control bit WD_MODE. All modes
use a timeout value WD_TO, what determines the watchdog timeout WD_TO. An 8 bit free-running counter
WD_CNT is counting using the pre-scaled input clock until it reaches the value WD_TO.
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Datasheet
The WD prescaler module supports the following ratios WD_DIV: 1/8, 1/32, 1/128, 1/512 of the 250kHz input
clock frequency. And the watchdog time-out value is defined by the following equation:
TimeOut 
1
 2 2WD _ DIV  8  WD _ TO
FCK
Equation 1
Where: Fck=1/Tck is the frequency of the WD input clock
WD_DIV is the WD predivider value, defined in IO port WCTRL
WD_TO is the time out value, defined in IO port WDT
For a given time, several combinations of WD_TO and WD_DIV can be found. It is recommended to use WD_TO
values as big as possible and to reduce WD_DIV.
Examples of timeout values for different Tosc values are given in Table 9.6.
Timeout (ms) for 250kHz input clock
1
5
10
50
100
WD_DIV
WD_TO
WD_DIV
WD_TO
WD_DIV
WD_TO
WD_DIV
WD_TO
WD_DIV
WD_TO
0
31
0
156
1
78
2
98
2
195
Table 9.6: Example of WD_DIV and WD_TO setting with Fck=250kHz.
The operating mode can be set only once after resetting, what usually happens in the system initialization. To
change the mode, a new system reset is needed. To acknowledge the watchdog, the Time Out value WD_TO in
the port WDCTRL must be written.
The IO port associated to the Time Out value WD_TO is the low byte of the port WDCTRL.
The IO port associated to the Tag value WD_TG is the port WTG.
The IO port associated to the Control and flag bits, e.g WD_MODE, is the high byte of the port WDCTRL.
9.3.1.8.4 Timer mode
In Timer mode the watchdog reset interrupt is generated simply when reaching the timeout value.
 The block can be acknowledged anytime by writing a dummy value into port WDCTRL. This restarts
the free-running counter.
 The timeout value WD_TO is fixed and can be changed only before enabling the watchdog.
 An attempt to change the control bit WD_MODE or WD_DIV sets the flag bit WD_ERR to 1. An
interrupt PROT_ERR is generated.
9.3.1.8.5 Window mode
In Window mode the acknowledgement must happen in a “window” between the half timeout and the timeout.
 An acknowledgement outside this window causes a CPU watchdog reset.
 The timeout value WD_TO is fixed and can be changed only before enabling the watchdog.
 The control bit WD_WND is set to 1 while the window is valid.
 An attempt to change the control bit WD_MODE or WD_DIV sets the flag bit WD_ERR to 1. An
interrupt PROT_ERR is generated.
 After the timeout programmed, WD_TO an attention interrupt WD_ATT is generated
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
The watchdog reset USER_WD_RST occurs only in case WD_TO had not been updated 1/8 of the
timeout after the first interrupt WD_ATT.
9.3.1.8.6 Intelligent mode
The Intelligent mode is different from the previous ones, as it supposes the software to allocate for a given task a
given amount of time and a tag.
 After the timeout programmed, WD_TO:
 An attention interrupt WD_ATT is generated,
 the software can verify it’s state using the tag WD_TG,
 The software can write a new couple of timeout value and tag.
 The watchdog reset USER_WD_RST occurs only in case WD_TO and WD_TG had not been updated
1/8 of the timeout after the first interrupt WD_ATT.
 An attempt to change the control bit WD_MODE sets the flag bit WD_ERR to 1. An interrupt
PROT_ERR is generated.
 To write new values in the IO port, the MULAN3 user bit USER must be set to 0, i.e. ‘System mode’
must be selected. Or else the flag bit WD_ERR is set to 1 and an interrupt PROT_ERR is generated.
9.3.1.8.7 Watchdog Control and Command ports
All the IO ports involved in Watchdog programming are resumed in Table 9.7 to Table 9.9:
 The Tag port WTG,
 The Status, Control and TimeOut port WDCTRL
IO port: WTG
Address: 0x2804
Bit[7]
Access mode: Word, Byte – Read and Write
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
WD_TAG[7:0]
Table 9.7: Watchdog ports – Tag value.
WD_TAG[7:0]:
tag value; using this port the Watchdog software can manage different owners
IO port: WDCTRL (high byte)
Address: 0x2803
Access mode: Word, Byte – Read and Write
Bit[7]
Bit[6]
WD_ERR
WD_WND
Bit[5]
Bit[4]
WD_MODE[1:0]
Bit[3]
Bit[2]
-
-
Bit[1]
WD_DIV[1:0]
Table 9.8: Watchdog ports – Status and Control port.
WD_ERR:
Flag for access error; depends on the Watchdog mode. Read and clear bit.
1 = WD access error detected; the interrupt PROT_ERR is generated
0 = no WD access error
WD_WND:
Flag to indicates the open windows; for windows mode only
1 = window is open, Watchdog acknowledge is allowed
0 = window is closed, no acknowledge allowed
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WD_MODE[1:0]:
Watchdog mode.
00 = Watchdog disabled
10 = Window Watchdog mode
01 = Timer Watchdog mode 11 = Intelligent Watchdog mode
WD_DIV[1:0]:
Predivider for Watchdog counter. The Watchdog counter clock frequency is divided by:
00 = division by 1*8
10 = division by 16*8
01 = division by 4*8
11 = division by 64*8
IO port: WDCTRL (low byte)
Address: 0x2802
Access mode: Word, Byte – Read and Write
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
WD_TO[7:0]
Table 9.9: Watchdog ports – Time Out value.
WD_TO[7:0]:
Time Out value; to be compare with the internal free running counter.
9.3.1.8.8 Interrupts connections
The MULAN3 integrated watchdog is connected directly to the Watchdog attention and watchdog reset
interrupts. For further detail refer to chapter “Interrupts”.
The interrupts are used shared with the separate analogue watchdog, as described in chapter “Analog Watchdog
(AWD)”
9.3.1.8.9 Reset state
After a Power-On-Reset or Watchdog-Reset the WD module is disabled and the IO ports are reset.
9.3.1.9 MULAN3 included periphery - ADC interface
9.3.1.9.1 Introduction and features
MULAN3 comprises an ADC frontend interface supporting the following features:
 flexible support of an ADC with Sample and Hold (S/H) and an analog multiplexer.
 single conversion
 multiple autonomous conversions on different input channels and using different reference voltages
 hardware-synchronized multiple conversions
 ADC autosequence table must be placed in RAM memory
The target of the interface is to limit the CPU support needed for this.
9.3.1.9.2 RAM needs
The ADC hardware runs autonomously through DMA (Direct Memory Access) in the CPUs RAM.
It uses a channels and a results table, which need to be initialized by software before starting the first conversion.
The channels table contains the data fields SIN (select ADC input channel) and SREF (select reference voltage,
hardware trigger source).
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For n channels, ( 4n + 2 ) bytes of RAM must be reserved. The base addresses for the two tables are set by the
ports ADC_SBASE (SBase, for the channels table) and ADC_DBASE (DBase, for the results table).
RAM
ADC controller action
DBase+n
ADCn
Write
DBase+1
DBase
ADC1
ADC0
Write
Write
SBase+n
0xFFFF
Read
SINn:SREFn Read
SBase+1
SBase
SIN1:SREF1 Read
SIN0:SREF0 Read
16 bits
Figure 9-9: RAM organization
The channels table is organized as follows:
Configuration word for one conversion, resides in RAM at addresses starting from ADC_SBASE
Bit[15]
...
Bit[8]
SIN[7]
...
SIN[0]
Bit[7]
...
Bit[0]
SREF[7]
...
SREF[0]
Table 9.10: channels table
SIN[7:0]
Input channel selector, max 8bit = 256 channels possible
SREF[7:4]
Hardware trigger source selection
SREF[3:0]
Reference voltage selection
After the last couple SINi:SREFi, a special marker (0xFFFF) is placed
Examples:
Below the RAM organisation for a single channel conversion and a conversion over four channels is given.
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RAM
DBase
SBase+1
SBase
ADC0
RAM
ADC controller action
DBase+3
DBase+2
DBase+1
DBase
ADC3
ADC2
ADC1
ADC0
Write
Write
Write
Write
SBase+3
SBase+2
SBase+1
SBase
0xFFFF
SIN3:SREF3
SIN2:SREF2
SIN1:SREF1
SIN0:SREF0
Read
Read
Read
Read
Read
ADC controller action
Write
0xFFFF
Read
SIN0:SREF0 Read
16 bits
16 bits
Figure 9-10: Single channel RAM
Figure 9-11: 4 Channels RAM
9.3.1.9.3 Interface function
Once the RAM has been initialized, the ADC interface can be started.
The START bit in the control register has to be set, and then conversions are triggered by events.
The events can be software events (SOFT_TRIG bit in the control register), or external events (pulses on the
HARD_TRIG input). The choice is done with the TRIG_SRCbit in the control register.
The first conversion uses SIN0 and SREF0, and automatically stores the result of the conversion in ADC0, the
second conversion SIN1 and SREF1, and automatically stores the result of the conversion in ADC1, etc...
Once the last conversion is done, (i.e. the next SINi:SREFi = 0xFFFF), the interface can do the following:
 Trigger an interrupt for the CPU and stop
 Trigger an interrupt and restart from SIN0:SREF0 if the loop bit is set in the control register.
9.3.1.9.4 Examples
1) A single shot conversion triggered by the software.
With a RAM organized like shown in Figure 9-10: Single channel RAM:
 Program the control register: START = 1, Trig_Src = 0 (to select the software trigger), loop=0 This will
open the sample and hold switch.
 The conversion will be started upon software request: soft_trig = 1. This also close the sample and
hold switch.
 When the conversion is completed, the result is stored in ADC0.
 An interrupt is generated and the interface is ready to resume.
2) A four channel conversion cycle, triggered by an external event and stopped at the fourth channel.
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With a RAM organized like shown in Figure 9-10: Single channel RAM:
 Program the control register: start = 1, trig_src = 1 (to select the external trigger), loop=0.
 SIN and SREF are put on the ADC input multiplexers, the sample and hold switch is opened (sample
position).
 When HARD_TRIG is set, the sample and hold switch is closed (hold position) and the conversion
starts.
 When the conversion is completed, the result is stored in RAM, the values for the next SIN and SREF
are read, and the interface waits for another trigger (note that if HARD_TRIG is still high, the next
conversion will start immediately).
 When SIN = SREF = 0xFF (after 4 conversions), an interrupt is generated and the interface is ready to
resume.
3) A four channel conversion cycle, permanently running, triggered by an external event.
With a RAM organized like shown on Figure 9-10: Single channel RAM:
 Program the control register: start = 1, trig_src = 1 (to select the external trigger), loop = 1.
 SIN and SREF are put on the ADC input multiplexers, The sample and hold switch is opened (sample
position).
 When HARD_TRIG is set, the sample and hold switch is closed (hold position) and the conversion
starts.
 When the conversion is completed, the result is stored in RAM, the values for the next SIN and SREF
are read, and the interface waits for another trigger (note that if HARD_TRIG is still high, the next
conversion will start immediately).
 When SIN = SREF = 0xFF (after 4 conversions), an interrupt is generated. The first couple of val ues for
SIN and SREF are read again and the conversions restart from the beginning.
9.3.1.9.5 Notes
By construction, DMA takes care of appropriate access to RAM, so there is no risk to read a wrong data.
In permanent conversion, the interrupt latency should be shorter than a conversion time to retrieve all the
conversion results of the same cycle.
With the interrupt disabled, the software can check the start bit in the control register to check if the conversion
is done. This bit is reset when the last conversion is done (loop bit not set). If the ADC is running in an endless
loop (loop bit set), the start bit is never reset and the user can read at any time the ADC values in the RAM. The
ADC values are however not necessarily consistent, i.e. all belonging to a single conversion cycle.
When using the HARD_TRIG input to trigger a conversion (trig_src bit is set), the first pulse on HARD_TRIG is
ignored to guarantee that the minimum conversion time is respected.
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9.3.1.9.6 Timing example
Sofware actions
Setup RAM
Start
START_ADC
SIN0
SIN1
SIN0
SREF0
SREF1
SREF0
SOC
EOC
DATA
DATA0
DATA1
INT
Event
Select first input
Wait for event
Save DATA0 in RAM
Check for last channel
Select next inputs
Wait for event
Save DATA1 in RAM
Check for last channel
Select next inputs
Wait for event
Figure 9-12: ADC Interface timing example
In this example, two channels have been defined, with event triggered start and permanent mode. CPU is
solicited every two conversions by an interrupt.
In order to stop the permanent conversion process, START can be asserted low and conversion(s) will stop after
the conversion of the current channel.
9.3.1.9.7 ADC control and command ports
There are 3 ports in the ADC interface:
 ADC_CONTROL port: control bits.
 ADC_SBASE: base address for SIN and SREF storage.
 ADC_DBASE: base address for conversion results.
Each port is 16-bits wide and accessible by bytes or words.
At reset, the control register is 0, SBase and DBase are X.
IO port: ADC_SBASE Address: 0x2812
Bit[7]
Bit[6]
Bit[5]
Access mode: Word, Byte – Read and Write
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
ADC_SBASE[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
ADC_SBASE[15:8]
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IO port: ADC_DBASE Address: 0x2814
Bit[7]
Bit[6]
Bit[5]
Access mode: Word, Byte – Read and Write
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
ADC_DBASE[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
ADC_DBASE[15:8]
Table 9.11: ADC Interface – Base addresses for input multiplexer and results
ADC_SBASE[15:0]:
base address for SIN (input channel) and SREF (reference voltage) storage
ADC_DBASE[15:0]: base address for conversion results
IO port: ADCCTRL Address: 0x2810
Access mode: Word, Byte – Read and Write
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
ADC_SYNC
_SOC
-
OVFM
OVF
-
LOOP
TRIG_SRC
START
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
ADC_EOC_SYNC
SOFT _TRIG
Table 9.12: ADC interface ports – Control register.
START
Start a conversion cycle.
If reset before the End Of Conversion interrupt is received, the cycle is
interrupted after the current conversion (the result of the current conversion
will be written in memory). Once a conversion cycle is finished, this bit is
cleared, unless the loop mode is enabled
TRIG_SRC
Selects the source of the conversion trigger.
If 0, the conversion is triggered by the SOFT_TRIG bit.
If trig_src is 1, the conversion is triggered by a external hardware pulse
LOOP
If 0, a single cycle of conversions is done when START is set.
If 1, the conversions cycle will start again with the first channel when the
special marker is detected. Resulting in an endless loop of conversions cycles.
This bit is never written by hardware.
OVF
This bit is the value of the ADC_OVF input sampled with the last ADC value.
This is a read only bit.
OVFM
Memorized occurrence of ADC overflow of a value in memory.
This bit is set when OVF is set, and has to be cleared by the software (by
writing 0).
SOFT_TRIG
When TRIG_SRC is 0 (software trigger selected), a conversion starts when this
bit is set.
This bit is automatically reset after a start of conversion.
ADC_EOC_SYNC
Synchronized End Of Conversion signal from the ADC.
This signal can be used to see if the current conversion is finished before
starting a new one. (i.e. it will be set for each conversion in a conversion
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cycle)
ADC_SYNC_SOC
0b0 = Do not discard first conversion; 0b1 = Discard first conversion
9.3.1.9.8 Interrupt connections
The ADC interface is connected directly to the ADC interrupt. For further detail refer to chapter 9.3.6.11
The ADC interface can cause protection error interrupts under following circumstances:
 the software tries to set the start bit or the soft_trig bit while the state machine is clearing it
 the software attempts to write in an area of the RAM protected by SHRAMH port.
9.3.1.9.9 External Hardware trigger connection
For details of the external hardware trigger routing towards the ADC interface please refer to the ADC input
multiplexer description.
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9.3.2 Memories
9.3.2.1 RAM sharing
RAMSize
M4
Private
MLX4 and MLX16 share the RAM by a mechanism controlled by 2 ports, SHRAML and SHRAMH. The principle is
shown in figure below:
MLX4 private
M4
Shared
MLX16 private
MLX16 + MLX4 shared
SHRAML = M4Private + M4Shared
SHRAMH = Last RAM Address - M4Private
Figure 9-13: MLX4 and MLX16 RAM sharing principle
Notes:

Ports SHRAMH and SHRAML can only be changed when Mlx4 is in reset (e.g. M4_RB = 0). When Mlx4
is running, writing to those ports has no action (e.g. ports are unchanged) and no er ror is flagged to Mlx16.
9.3.2.2 ROM / Flash sharing
The MLX4 has its code in the ROM, the MLX16 has its own code in the Flash and ROM. The SW for the integrated
LIN protocol is provided by Melexis and certified by external certification houses. The application SW is
developed by the customer.
9.3.2.3 Flash macro
The 32k byte flash memory is organized in 256 pages with 32 double-words each (32 user bits per double-word).
The 32 user bits are secured by a hardware ECC mechanism (ECC= Error Checking and Correcting) and additional
7 bits. By this the memory can correct single bit fail per double word, and detect double bit fail per double word.
The write of a flash memory page takes typically 5ms.
Flash erase takes place per 2Kbyte, Write to the Flash per 128Bytes.
Further the memory supports 2 special ranges:
- a latch based buffer, that is used to read or write the non-volatile memory array by page. This buffer has the
size of 1 page
- a configuration sector of 256bytes – this non-volatile memory part is not usable for the application, it is
dedicated to store Melexis reserved parameters
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39 bits
Mlx4 Word
Address
Data Bits
32 bits
Mlx16 Byte
Address
Check Bits
7 bits
BFFF
32 DW
Main Page 255
32 DW
Main Page 63
32 DW
Main Page 1
32 DW
Main Page 0
32 DW
Configuration Sector
Page 1
1K bits
128 Bytes
64 Words
32 DWords
Configuration Sector
Page 0
BF80
FFF
Mlx16
Fetch/Read
Area
5FFF
5F80
Mlx4 Fetch
Area
MAIN ARRAY
256K bits
32K Bytes
16K Words
8K DWords
40FF
4080
407F
000
4000
3FFF
3F80
Mlx16
Read Area
3F7F
3F00
CONFIGURATION
SECTOR ARRAY
2K bits
256 Bytes
128 Words
64 DWords
Figure 9-14: Flash organization (8Kx32)
The macro uses the 1.8 and 3.3 volt power supply to perform both read and in-system programming (ISP), built-in
charge pumps generate the high voltages for write and erase operations.
The Flash can be programmed:
 Via the test pin interface using the Melexis emulator under lab conditions
 In the application via the pin LIN
 Using the LIN protocol
 Using the Melexis boot loader and the Melexis programming tool
Temperature
Warranty
Max. cycles (program/erase)
1 000
85C
Data Retention
25C
>10 years
85C
10000h
125C
3000h
150C
1000h
Table 9.13 Flash Data
Data retention is still guaranteed after applying the maximum allowed number of cycles.
Flash memory Program and Write can be performed at junction temperature TJFLPR= 0°C…85°C
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9.3.2.3.1 Loading Application Software into Flash Memory
Per default, the system memory (Flash) contains a basic boot-loader, which has been programmed into each chip
during final test. Customers can order to program their software at chip test, please contact Melexis for further
logistic and commercial details.
There are 3 mechanisms of getting the Flash programmed:
A. Melexis programs it during production test
B. Via the emulator at the test pin interface: only allowed under LAB conditions
C. Customer programs it during EOL using the boot loader and MLX tool set.
The description, how to use this bootloader will be published in a separate application note.
Program it via the LIN bus at the customer is a subset of A), because there must already be a full LIN layer inside.
9.3.2.4 NVRAM
MLX81325 incorporates a 2 NVRAM blocks of 128 words x 16bit size (2K Bit), organized in 2 pages each.
With this NVRAM it is possible to store non-volatile information of the customer’s application data.
The macro uses the 1.8 and 3.3 volt power supply to perform both read and in-system programming (ISP), built-in
charge pumps generate the high voltages for the nonvolatile operations
The NVRAM has a built-in error detection and a single-error correction.
The block has three modes of operation:
 SRAM mode,
 Nonvolatile recall mode
 Nonvolatile store mode.
In SRAM mode, the memory operates like a static RAM with fast read and write cycles.
The SRAM can be read and written for unlimited number of times, while independent nonvolatile data resides in
NVRAM. The data of the NVRAM are unchanged during the SRAM mode.
In the nonvolatile modes the SRAM functions are disabled, because there is a data transfer between SRAM and
NVRAM. Once the recall or store cycle is initiated, further input or output are disabled until the cycle is
completed.
In nonvolatile store operation, all data from the SRAM are transferred in one parallel step to NVRAM. The store
cycle has to be initiated by a call to a library function.
The store operation takes typical < 15 ms per 64 words.
The nonvolatile recall mode is used for writing back the data from NVRAM to SRAM. Internally, recall is a twostep procedure. First, the SRAM data is cleared and second, the nonvolatile data is written to the SRAM. The
content of the SRAM will be overwritten.
The recall operation does not affect the data in the NVRAM cells, they can be recalled for an unlimited number of
times.
The NVRAM can be programmed:
 Via the test pin interface using the Melexis emulator under lab conditions
 By the application and the SW itself
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
In the application via the pin LIN
 Using the LIN protocol
 Using the Melexis boot loader and the Melexis programming tool
Temperature
Warranty
Max. cycles (program)
25C
100 000
150C
10 000
Data Retention
25C
>10 years
85C
10000h
125C
3000h
150C
1000h
Table 9.14 NVRAM Data
Application Hints:
 Melexis supports Read, Write and Store with library routines
 The store operation is completely under Software control. It can be done at any time by software.
9.3.2.4.1 NVRAM organization
Device
Page
Size
(words)
Read
Write
Addressrange
Usage
NVRAM2
2
(upper
words)
64
User
Testmode
highest nv
address
Melexis (Flash-, type
specific-, 1 word nv-)
trim data
NVRAM2
1
(lower
words)
64
User
User
Application Customer
NVRAM1
2
(upper
words)
64
User
System
63 words EOL
Trimming customer,
1 words nv trimming
(most upper word of
this page)
NVRAM1
1
(lower
words)
64
User
User
nv start
address
Application customer
Table 9.15: NVRAM organisation
Syntax:
User:
Write/Erase Access always possible
System:
Write/Erase Access possible only in system mode
Testmode:
Write/Erase Access possible only in test mode
Each page is separately selectable for nv operation. Each nvSRAM has its own Charge pump.
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It is not allowed for customer to change or delete the page 2 of NVRAM2 and the upper word of page 2 of
NVRAM1, because there are stored all the trimming data for the IC. A changing or deleting these data may result
in inaccurate or fail or even no more function of the IC.
9.3.2.4.2 NVRAM ports
IO port: NVCTRL Address: 0x2024
Bit[7]
Bit[6]
Bit[5]
Melexis reserved testmode bits
Bit[15]
Bit[14]
NV_SEL
Bit[13]
Access mode: Word, Byte – Read and Write
Bit[4]
Bit[3]
Bit[2]
NV1_MEM_ NV1_MEM_ NV_BIT_VFY
ALLC
SEL
Bit[12]
Bit[11]
Melexis reserved testmode bits
Bit[10]
Bit[1]
Bit[0]
NV_
SRAMWR
NV_BUSY
Bit[9]
Bit[8]
NV2_MEM_ NV2_MEM_
ALLC
SEL
MLX
reserved
testmode bit
Table 9.16: IO port NVCTRL
Melexis reserved
testmode bits
write is ignored, read back to all=0
NV_SEL
Selects NVRAM 1 or NVRAM 2 for Store/Recall operation
NV1(2)_MEM_ALLC
Enables write in both (0) or only one page (1)
NV1(2)_MEM_SEL
Selection between upper and lower block (writable in test mode and during
programming only, not writable for the application software)
NV_BIT_VFY
Melexis reserved, write to 0
NV_CONF[1] /
NV_SRAMWR
Write mode = NVCONF[1:0] :
- determine action of NVRAM block :
x0: SRAM mode
01: Recall (NV Area -> SRAM)
11: Store (SRAM -> NV Area)
Read mode = NV_SRAMWR:
- reflects differences between SRAM and nonvolatile NV area ;
0: SRAM = NV Area, 1: SRAM was written, it may differ to NV area
NV_CONF[0] / NV_BUSY
NV_BUSY
Read mode = NVRAM BUSY:
- cleared when operation done
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9.3.2.4.3 Patch mechanism - principle
In order to correct bugs in the ROM code, a specific hardware is available to replace an ROM space by a space in
NVRAM code. The principle of the mechanism is explained in the image below:
Figure 9-15: Patch mechanism
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Patch registers are PATCHi_I and PATCHi_A (i=0..3).
At reset the patches are disabled (Bits PATCHi_EN=0).
The initialization code decides if patches must be applied. If yes, patch ports are loaded.
Port PATCHi_A (i = 0) must be loaded with the address where the patch should start.
PATCHi_I must be loaded with the special instruction (a jump into far page) and the address into the far page.
Below figure shows how to execute the patch in NVRAM.
Fp7 value
In chapter 9.3.2.4.1. NVRAM1 Page 2 "63 words EOL" is correct, when patch is not used. This same NVRAM page
has also the patch loaded, and it is as follows (63 words will be reduced by 10 to 53 words, or even further if
more patch code is required.):
0x10EA = Patch Version (this version is checked against the ROM code version and must match; If not the patch is
not loaded.
0x10EC ==> PATCH0_I
0x10EE ==> PATCH1_I
0x10F0 ==> PATCH2_I
0x10F2 ==> PATCH3_I
0x10F4 ==> PATCH0_A
0x10F6 ==> PATCH1_A
0x10F8 ==> PATCH2_A
0x10FA ==> PATCH3_A
The PATCHi_I can be a single 16-bit instruction only. If more than 1x 16-bit instruction is needed for the patch,
this first instruction should be a FP-Jump or FP-Call to a FP7-page, which is the NVRAM 1 block (0x1000-0x10FF).
The exact address can any of the NVRAM 1 addresses modulo 8, e.g. 0x1080, 0x1088, 0x1090, ... (The addresses
0x1000, 0x1008, 0x1010, ... 0x1078 are not used, and kept free for application). In this FP7 the code-block with
jump-back or RETurn is placed.
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9.3.3 Mlx16 interrupts
9.3.3.1 Introduction
This chapter explains how the interrupts are handled inside MLX81325 chip. It clarifies and gives add on
information on the description of the interrupts in the MLX16x8 data book. It also gives the customer an
overview of the interrupt allocation table.
9.3.3.2 Interrupt sources
There are a number of different interrupt sources in the chip:
 system interrupts like system reset, stack overflow, address error …
 user block interrupts like PWM interrupts, timer interrupts …
 custom interrupts depending on the analogue part or IO pads
9.3.3.2.1 System interrupts






The system interrupts are the interrupts at position 0 to 8. For those interrupt routines, Melexis
provides an interrupt service routine to handle them correctly. These routines handle
the correct start-up and power down of the chip, i.e. the MULAN core,
communication between the MLX4 and MLX16x8 CPU’s,
NVRAM / NVRAM write routines,
invalid address errors,
stack overflows, …
9.3.3.2.2 User block interrupts
The user block interrupts comprise of interrupts coming from:
 Timer modules
 PWM modules
 SPI modules
 Watchdog attention interrupt
The user is supposed to write the appropriate interrupt handlers for these interrupts.
Those interrupts typically share a single interrupt line of the MULAN/Mlx16 interrupt controller. They are
organised in a second level interrupt controller as described below.
9.3.3.2.3 Custom interrupts
The analogue part can also generate a number of interrupts. There are up to 12 possible interrupt sources named
CUSTINT12 to CUSTINT0.
These interrupt sources can be used to implement e.g. IO interrupts etc.
All feed into a single block of the second level interrupt controller.
9.3.3.3 Interrupt management
9.3.3.3.1 Interrupt enabling and masking
Every non system interrupt can be enabled or masked. The mask bit does not disable the interrupt source.
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All the masking bits are grouped into dedicated ports; please refer to the ports map for detail. When the MASK
bit is set, the belonging interrupt is enabled.
After reset the MASK ports are reset, so all interrupts are disabled.
In case interrupts are:
 enabled with the enable flag, and
 disabled by priority,
the interrupt sources are still active. An interrupt is memorized only once, and it will be performed when CPU
runs on a priority again which enables this interrupt.
9.3.3.3.2 Pending interrupts
When an interrupt request (IRQ) occurs and it cannot be served immediately, the pending bit of this IRQ is set. All
the pending bits are into dedicated ports; please refer to the ports map for detail.
Even if interrupts are masked, the state of the sources can be checked by reading the pending bits.
The pending bit is set only once, even when more than one IRQ occurred before being serviced.
Software can clear a pending interrupt source by setting the corresponding bit in the IO port PEND / XIxPEND.
9.3.3.3.3 Call and jump interrupts
When an interrupt occurs, the interrupt controller suppresses the next instruction fetched from memory and
displays another instruction to the MLX16 CPU instead.
This instruction is typically a CALL to the specified interrupt vector address. (for reset and stack error a JUMP
instead of CALL is issued)
At the interrupt vector the priority is set and a jump to the appropriate interrupt service routine (ISR) follows. At
the end of the ISR a return can be placed, and the program counter returns to where it came from before the IRQ
occurred.
As after a stack error or a reset a return point can not be defined, those interrupts execute a JUMP to the vector
address.
9.3.3.4 Interrupt priorities
Every interrupt source has its own priority. The priorities are grouped into eight classes, from priority zero to
priority seven; zero is the highest priority, seven the lowest. An ISR can be interrupted by any other IRQ with the
same priority or higher – i.e. the same class or lower.
There are some mechanisms that define the interrupt priority:
The user priority defines the current working priority level of the running software. This is set by the UPR field in
the MLX16 M register and is used to decide, if an interrupt request is allowed to interrupt the current code (ISR
or normal routines).
The software priority (or absolute priority) defines the priority of the interrupt request. It must be higher or equal
than the current user priority (lower number) to allow to interrupt the current code. The software priority of the
non-system interrupts can be programmed through the corresponding port.
 The hardware priority (or priority position) is used as conflict resolver in case 2 interrupt sources of
same software priority are pending.
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9.3.3.4.1 User priority
During execution of every piece of code, there is a certain level of interrupt masking. The UPR bits in the M
register of the MLX16x8 -see MLX16x8 data book- define the interrupt priority of an IRQ that can interrupt the
currently executing code.
Every IRQ with a software interrupt priority equal or higher (equal or lower number) than this value can interrupt
this routine.
This is true for all pieces of code, ISR as well as the main loop. If during the main loop, these UPR bits are set to 4,
an IRQ of priority 5 will never be seen.
It is the responsibility of the application engineer to make sure that in the main loop these UPR bits have the
correct value so that all wanted interrupts can be acknowledged. In the Melexis firmware platform, this interrupt
level is set to seven (lowest priority) when entering the main function. This means that every IRQ can interrupt
the main function.
When entering an ISR, the first instruction has to be a Push, #constant instruction that pushes this M register on
the stack and sets a new value in the UPR bits (#constant parameter in this instruction, value from 0 to 7). By
writing a new value in the UPR bits in the ISR, another level of interrupts can be masked.
It is possible that an ISR of an IRQ with software priority 5 sets these bits to 2. By doing so, all IRQs with software
priority less or equal than 2 (higher or equal number) are blocked. This means that an ISR routine of an IRQ with
software priority 5 can block an IRQ with software priority 4 by changing the UPR bits in its ISR. This is called
“interrupt priority inversion” can lead to situations hard to explain.
The M register has to be manually restored when exiting the ISR by popping it from the stack. This has to be the
very last instruction of the ISR.
The Push and pop instructions to keep track of the M register and UPR bits are handled automatically in the
Melexis firmware platform.
9.3.3.5 Mlx16 interrupt table
On Table 9.17,
 Column “Pos” represents the interrupt input position in the interrupt controller.
 Column “Abs” represents the absolute priority of the input.
 Column “Rel” represents the relative priority for inputs having an identical absolute priority.
 Column “Type” defines which instruction will be issued by the interrupt controller in case of
interrupt.
Description
Pos
Priority
Abs Rel
Type
Note
PRIO
Reset + Watchdogs Reset
0
0
0
Jump
1,3,4
Stack error
1
0
1
Jump
1,3,4
Protection error
2
0
2
Jump
2,3,4
Invalid address
3
0
3
Jump
2,3,4
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Ports
MASK
PEND
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Description
Pos
Priority
Abs Rel
Type
Note
PRIO
Ports
MASK
PEND
MASK[0]
PEND[0]
Program error
4
0
4
Jump
2,3,4
Exchange request
5
1
0
Call
5
Task reset
6
1
1
Call
MASK[1]
PEND[1]
Watchdog attention
7
1
2
Call
MASK[2]
PEND[2]
Mutex
8
2
0
Call
MASK[3]
PEND[3]
LIN communication
9
5
0
Call
MASK[4]
PEND[4]
Timer
10
3-6
1
Call
PRIO[1:0]
MASK[5]
PEND[5]
ADC end of conversion
11
3-6
2
Call
PRIO[3:2]
MASK[6]
PEND[6]
End of NVRAM Write/Erase
12
3-6
3
Call
PRIO[5:4]
MASK[7]
PEND[7]
External Interrupt 0 - Timer1
13
3-6
4
Call
PRIO[7:6]
MASK[8]
PEND[8]
External Interrupt 1 - Timer 2
14
3-6
5
Call
PRIO[9:8]
MASK[9]
PEND[9]
External Interrupt 2 - PWMs
15
3-6
6
Call
PRIO[11:10]
MASK[10]
PEND[10]
External Interrupt 3 - SPI
16
3-6
7
Call
PRIO[13:12]
MASK[11]
PEND[11]
External interrupt 4 – IOs, flags
17
3-6
8
Call
PRIO[15:14]
MASK[12]
PEND[12]
Software interrupt
18
7
0
Call
MASK[13]
PEND[13]
Table 9.17 Mlx16 interrupt table
Notes:
1: Abort current instruction
2: Abort current instruction ► Return is NOT possible
3: No disable possible
4: Priority 0 can only be reached in system mode
5: For conformance test
Reminder:
For Mlx16(x)-8, the highest priority is 0 and the lowest is 7.
The absolute priority is compared to Mlx16 priority to trigger an interrupt
The relative priority is used by interrupt controller to decide between identical absolute priority
interrupts fired at the same time: Lowest is issued first.
Note:
The level 0 of priority is not reachable in user mode. When Mlx16(x)-8 sets priority to 0 in user mode, it is
interpreted as priority 1 by the interrupt controller.
9.3.3.6 Interrupt vectors
Table 9.18 shows the interrupt vectors table as well as the type of interrupt generated (call or jump).
Description
Priority
Type
Interrupt in Fp0:
Pos
Abs
Rel
Addr
Name
Reset + Watchdogs Reset
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0
0
0
Jump
Fp6:68
RST_WD_IT
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Description
Priority
Abs
Rel
Type
Pos
Interrupt in Fp0:
Addr
Name
Stack error
1
0
1
Jump
Fp6:70
STACK_IT
Protection error
2
0
2
Jump
Fp6:78
PROT_ERR_IT
Invalid address
3
0
3
Jump
Fp6:80
INV_AD_IT
Program error
4
0
4
Jump
Fp6:88
PROG_ERR_IT
Exchange request
5
1
0
Call
Fp0:90
EXCHANGE_IT
Task reset
6
1
1
Call
Fp0:98
TASK_RST_IT
Watchdog attention
7
1
2
Call
Fp0:A0
WD_ATT_IT
Mutex
8
2
0
Call
Fp0:A8
M4_MUTEX_IT
Signal, Handshake, Event, [Mutex]
9
5
0
Call
Fp0:B0
M4_SHE_IT
Timer
10
3-6
1
Call
Fp0:B8
TIMER_IT
ADC end of conversion
11
3-6
2
Call
Fp0:C0
ADC_IT
End of NVRAM Write/Erase
12
3-6
3
Call
Fp0:C8
EE_IT
External Interrupt 0 – Timer 1
13
3-6
4
Call
Fp0:D0
EXT0_IT
External Interrupt 1 - Timer 2
14
3-6
5
Call
Fp0:D8
EXT1_IT
External Interrupt 2 - PWMs
15
3-6
6
Call
Fp0:E0
EXT2_IT
External Interrupt 3 - SPI
16
3-6
7
Call
Fp0:E8
EXT3_IT
External interrupt 4 – Ext pin
17
3-6
8
Call
Fp0:F0
EXT4_IT
Software interrupt
18
7
0
Call
Fp0:F8
SOFT_IT
Table 9.18 Interrupt vector table
9.3.3.7 External Interrupts connection
The IC contains a second level interrupt controller extern from MULAN3 core, what supports up to 16 interrupt
sources for each of the 5 external interrupt inputs of MULAN3.
Every input of those second level controllers can be masked independently. Also separate clearing of pending
interrupts is supported by the according ports. The priority is defined in the setting for the level 0 external
interrupts in MULAN3 interrupt controller, as described in the previous chapter.
The sources are distributed to the five second level interrupt controllers as follows:
External Interrupt 1 sources
Interrupt Source
Description
TMR1_CAPA_IT
Pos
Rel Priority PORT
MASK
PORT
PEND
Capture Int Ch A, Timer TMR1_INT1
1
0
1
XI0MASK[9]
XI0PEND[9]
TMR1_CAPB_IT
Capture Int Ch B, Timer TMR1_INT5
1
1
2
XI0MASK[8]
XI0PEND[8]
TMR1_CMPA_IT
Compare Int Ch A, Timer TMR1_INT2
2
3
XI0MASK[7]
XI0PEND[7]
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Local name
Inside block
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Interrupt Source
Description
Local name
Inside block
Pos
Rel Priority PORT
MASK
PORT
PEND
1
TMR1_CMPB_IT
Compare Int Ch B, Timer TMR1_INT4
1
3
4
XI0MASK[6]
XI0PEND[6]
TMR1_OVF_IT
Overfow Int Timer 1
TMR1_INT3
4
5
XI0MASK[5]
XI0PEND[5]
Local name
Inside block
Pos
Rel Priority PORT
MASK
PORT
PEND
External Interrupt 2 sources
Interrupt Source
Description
TMR2_CAPA_IT
Capture Int Ch A, Timer TMR2_INT1
2
0
1
XI1MASK[9]
XI1PEND[9]
TMR2_CAPB_IT
Capture Int Ch B, Timer TMR2_INT5
2
1
2
XI1MASK[8]
XI1PEND[8]
TMR2_CMPA_IT
Compare Int Ch A, Timer TMR2_INT2
2
2
3
XI1MASK[7]
XI1PEND[7]
TMR2_CMPB_IT
Compare Int Ch B, Timer TMR2_INT4
2
3
4
XI1MASK[6]
XI1PEND[6]
TMR2_OVF_IT
Overfow Int Timer 2
4
5
XI1MASK[5]
XI1PEND[5]
TMR2_INT3
External Interrupt 3 sources×
Interrupt Source
Description
Pos
Rel
Priority
PORT
MASK
PORT
PEND
PWM1_CMPI
PWM1 compare interrupt
0
1
XI2MASK[15]
XI2PEND[15]
PWM1_CNTI
PWM1 counter interrupt
1
2
XI2MASK[14]
XI2PEND[14]
PWM2_CMPI
PWM2 compare interrupt
2
3
XI2MASK[13]
XI2PEND[13]
PWM2_CNTI
PWM2 counter interrupt
3
4
XI2MASK[12]
XI2PEND[12]
PWM3_CMPI
PWM3 compare interrupt
4
5
XI2MASK[11]
XI2PEND[11]
PWM3_CNTI
PWM3 counter interrupt
5
6
XI2MASK[10]
XI2PEND[10]
PWM4_CMPI
PWM4 compare interrupt
6
7
XI2MASK[9]
XI2PEND[9]
PWM4_CNTI
PWM4 counter interrupt
7
8
XI2MASK[8]
XI2PEND[8]
PWM5_CMPI
PWM5 compare interrupt
6
7
XI2MASK[7]
XI2PEND[7]
PWM5_CNTI
PWM5 counter interrupt
7
8
XI2MASK[6]
XI2PEND[6]
External Interrupt 4 sources
Interrupt Source
Description
Pos
Rel
Priority
PORT
MASK
PORT
PEND
SPI1_RI
SPI1 receive interrupt
0
1
XI3MASK[15]
XI3PEND[15]
SPI1_TI
SPI1 transmit interrupt
1
2
XI3MASK[14]
XI3PEND[14]
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External Interrupt 5 sources
Interrupt Source
Description
Pos
Rel
Priority
PORT
MASK
PORT
PEND
ANA_INA[15]
OVT - overtemp event
0
1
XI4MASK[15]
XI4PEND[15]
ANA_INA[14]
UV_VS - undervoltage event
1
2
XI4MASK[14]
XI5PEND[14]
ANA_INA[13]
OV_VS - overvoltage event
2
3
XI4MASK[13]
XI4PEND[13]
ANA_INA[12]
PLL INT - pll interrupt
3
4
XI4MASK[12]
XI4PEND[12]
ANA_INA[11]
OC_DRV - over currents sense
detection
4
5
XI4MASK[11]
XI4PEND[11]
ANA_INA[10]
VDS_MON - drain source voltage
monitor for extern HS driver
5
6
XI4MASK[10]
XI4PEND[10]
ANA_INA[9]
unused1
6
7
XI4MASK[9]
XI4PEND[9]
ANA_INA[8]
LIN_INT - LIN RX as int source
7
8
XI4MASK[8]
XI4PEND[8]
ANA_INA[7]
IOINT[7] - IO[7] pin interrupt
8
9
XI4MASK[7]
XI4PEND[7]
ANA_INA[6]
IOINT[6] - IO[6] pin interrupt
9
10
XI4MASK[6]
XI4PEND[6]
ANA_INA[5]
IOINT[5] - IO[5] pin interrupt
10
11
XI4MASK[5]
XI4PEND[5]
ANA_INA[4]
IOINT[4] - IO[4] pin interrupt
11
12
XI4MASK[4]
XI4PEND[4]
ANA_INA[3]
IOINT[3] - IO[3] pin interrupt
12
13
XI4MASK[3]
XI4PEND[3]
ANA_INA[2]
IOINT[2] - IO[2] pin interrupt
13
14
XI4MASK[2]
XI4PEND[2]
ANA_INA[1]
IOINT[1] - IO[1] pin interrupt
14
15
XI4MASK[1]
XI4PEND[1]
ANA_INA[0]
IOINT[0] - IO[0] pin interrupt
15
16
XI4MASK[0]
XI4PEND[0]
Table 9.19 External interrupt sources
1
ANA_INA[9] contains the LIN_RX input as static flag. It is not used as interrupt source and therefore ma rked
unused
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9.3.4 Ports-Map
For detail please refer to the block description and the detailed ports map in appendix
Addres
s
Name
15
14
13
12
11
10
9
2000
EEPROM,
CONTROL
Reserved
EE_
CPTEST
EE_VEE2
EE_VEE1
EE_TEST
EE_DMA
EE_
CTL[1:0]
2002
SHRAM
2004
PRIO
EXT4_IT_PRIO
2006
MASK
unused
EN_SOFT EN_EXT4 EN_EXT3_ EN_EXT2 EN_EXT1_I EN_EXT0_I EN_EE_IT EN_ADC_I EN_TIME EN_M4_S EN_M4_ EN_WD_ EN_TASK EN_EXCH
_IT
_IT
IT
_IT
T
T
T
R_IT
HE_IT
MUTEX_I ATT_IT
_RST_IT ANGE_IT
T
2008
PEND
unused
CLR_SOF CLR_EXT4 CLR_EXT3 CLR_EXT2 CLR_EXT1 CLR_EXT0_I CLR_EE_IT CLR_ADC CLR_TIME CLR_M4_ CLR_M4_ CLR_WD_ CLR_TASK CLR_EXCH
T_IT
_IT
_IT
_IT
_IT
T
_IT
R_IT
SHE_IT MUTEX_I ATT_IT
_RST_IT ANGE_IT
T
200A
M4IF
200C
PATCH0_I
PATCH0_I[15:8]
PATCH0_I[7:0]
200E
PATCH1_I
PATCH1_I[15:8]
PATCH1_I[7:0]
2010
PATCH2_I
PATCH2_I[15:8]
PATCH2_I[7:0]
2012
PATCH3_I
PATCH3_I[15:8]
2014
PATCH0_A
PATCH0_A[15:8]
PATCH0_A[7:1]
PATCH0_
EN
2016
PATCH1_A
PATCH1_A[15:8]
PATCH1_A[7:1]
PATCH1_
EN
2018
PATCH2_A
PATCH2_A[15:8]
PATCH2_A[7:1]
PATCH2_
EN
201A
PATCH3_A
PATCH3_A[15:8]
PATCH3_A[7:1]
PATCH3_
EN
201C
ANA_OUTA
201E
ANA_OUTB
2020
ANA_OUTC
8
7
6
5
4
3
2
1
0
WD_
BOOT
EE_WE
OUTC_
WE
OUTB_
WE
OUTA_
WE
MUTEX_
SHE
HALT
M4_RB
SHRAMH[7:0]
EXT3_IT_PRIO
SHRAML[7:0]
EXT2_IT_PRIO
EXT1_IT_PRIO
SLVIT[15] SLVIT[14 SLVIT[13] SLVIT[12] SLVIT[11] SLVIT[10]
]
TRIM_RCF
REVISION 1.7 – 27. Apr 2020
SLVIT[8]
SLVCMD[7:6]
NV_IT_PRIO
ADC_IT_PRIO
0<Reserved>
TIMER_IT_PRIO
SLVCMD[3:0]
PATCH3_I[7:0]
TRIMCPHS[3]
reserved
TR_BG
EXT_CE_SEL
B
SLVIT[9]
EXT0_IT_PRIO
TR_BIAS[5:2]
TRIMCPHS[2:0]
TR_BIAS[1:0]
TR_RCO[6:0]
TRIMCPOSC[2:0]
TR_V1V8
TR_PLL[7:0]
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Datasheet
Addres
s
Name
20222026
Melexis
reserved
2028
CKTRIM
202A
XI0MASK
XI0MASK[15:8]
XI0MASK[7:0]
202C
XI1MASK
XI1MASK[15:8]
XI1MASK[7:0]
202E
XI2MASK
XI2MASK[15:8]
XI2MASK[7:0]
2030
XI3MASK
XI3MASK[15:8]
XI3MASK[7:0]
2032
XI4MASK
XI4MASK[15:8]
XI4MASK[7:0]
2034
XI0PEND
XI0PEND[15:8]
XI0PEND[7:0]
2036
XI1PEND
XI1PEND[15:8]
XI1PEND[7:0]
2038
XI2PEND
XI2PEND[15:8]
XI2PEND[7:0]
203A
XI3PEND
XI3PEND[15:8]
XI3PEND[7:0]
203C
XI4PEND
XI4PEND[15:8]
XI4PEND[7:0]
203E
PLLCTRL
FBDIV[7:0]
2040
PLLSTAT
reserved
2042
LIN_XKEY
LIN_XKEY[15:8]
LIN_XKEY[7:0]
20442049
Melexis
reserved
should not be written
should not be written
204A
ANA_OUTD
204C
ANA_OUTE
204E
ANA_OUTF
DIS_PMOS_EXTIO[7:0]
ENABLE_EXTIO[7:0]
2050205E
Melexis
reserved
should not be written
should not be written
2800
VARIOUS
reserved
2802
WDCTRL
2804
XIN, WTG
2806
TIMER
15
14
13
12
11
10
9
8
7
6
5
4
should not be written
unused
WD_ERR WD_WND
PLL_CTLCK[3:0]
TR_ADCREF1
unused
TR_ADCREF3
EENV_DE EENV_SEC
D
unused
REVISION 1.7 – 27. Apr 2020
0
WD_DIV
WKUP
PHISTAT[1:0]
WD_TO[7:0]
WTG[7:0]
TIMER[14:8]
TIMER[7:0]
Page 63 of 182
PLL_EN
PLL_CM PLL_LOCK
ED
unused
unused
TMR_EN
PLL_SELX PLL_XTAL Reserved
TAL
ON
reserved
unused
WD_MODE
1
reserved, should not be written
TR_ADCREF2
ADCFREQ
2
should not be written
CKTRIM[5:0]
unused
3
EXTMEM SCOPE_BI
T
SWI
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Addres
s
Name
15
14
13
12
11
280C
MICEMRK
unused
280E
MICE
MC_EXCHG[15:8]
2810
ADC_CTRL
2812
ADC_SBASE
ADC_SBASE[15:8]
ADC_SBASE[7:0]
2814
ADC_DBASE
ADC_DBASE[15:8]
ADC_DBASE[7:0]
281A
AWD
281C
ANA_INA
281E
ANA_INB
2820
LIN_XCFG
28222829
Melexis
reserved
282A
TMR1_TCTRL
282C
TMR1_TREGB
TMR1_TREGB[15:8]
TMR1_TREGB[7:0]
282E
TMR1_TREGA
TMR1_TREGA[15:8]
TMR1_TREGA[7:0]
2830
TMR1_TCNT
TMR1_TCNT[15:8]
TMR1_TCNT[7:0]
2832
TMR2_TCTRL
TMR2_TCTRL[15:8]
TMR2_TCTRL[7:0]
2834
TMR2_TREGB
TMR2_TREGB[15:8]
TMR2_TREGB[7:0]
2836
TMR2_TREGA
TMR2_TREGA[15:8]
TMR2_TREGA[7:0]
2838
TMR2_TCNT
TMR2_TCNT[15:8]
TMR2_TCNT[7:0]
284A
PWM1_PPSCL,
PWM1_PCTRL
PWM1_PPSCL[15:8]
284C
PWM1_PPER
PWM1_PPER[15:8]
PWM1_PPER[7:0]
284E
PWM1_PLT
PWM1_PLT[15:8]
PWM1_PLT[7:0]
2850
PWM1_PHT
PWM1_PHT[15:8]
PWM1_PHT[7:0]
2852
PWM1_PCMP
PWM1_PCMP[15:8]
PWM1_PCMP[7:0]
ADC_EOC
10
REVISION 1.7 – 27. Apr 2020
8
OV_VS
PLL_INT
6
5
ADC_SYN
C
OC_DRV
VDS_MO
N
INTERNAL
_WU
unused
unused
2
1
0
ADC_
OVFM
ADC_OVF
unused
ADC_LOO ADC_TRIG
P
_SRC
ADC_
START
AWD_TIMER
unused
LIN_RX
IO_INT[7:0]
LOCAL
_WU
LIN_WU
unused
LIN_XPHY LIN_XPRO SLEEPB_LI
_ACTIVE _ACTIVE
N
LSM
should not be written
TMR1_MODE
3
MC_STAT[3:0]
AWD_CKD
IV
unused
TMR1_DIV
4
MC_EXCHG[7:0]
unused
UV_VS
7
unused
AWD_RS AWD_AT AWD_WR unused
T
T
ITE_FAIL
OVT
9
TMR1_EN TMR1_OVR TMR1_OV
CMP
B
RA
HSM
BYPASS
LIN_XOUT DISTERM LIN_EN_X LIN_EN_X
INV
PHY
PRO
should not be written
TMR1_DIN
unused
Page 64 of 182
TMR1_EDG2
TMR1_EDG1
TMR1_ST TMR1_EB
ART
LK
PWM1_E PWM1_E PWM1_M PWM1_E PWM1_E
CI
PI
ODE
XT
BLK
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Addres
s
Name
2854
PWM2_PPSCL,
PWM2_PCTRL
PWM2_PPSCL[15:8]
PWM2_PCTRL[7:0]
2856
PWM2_PPER
PWM2_PPER[15:8]
PWM2_PPER[7:0]
2858
PWM2_PLT
PWM2_PLT[15:8]
PWM2_PLT[7:0]
285A
PWM2_PHT
PWM2_PHT[15:8]
PWM2_PHT[7:0]
285C
PWM2_PCMP
PWM2_PCMP[15:8]
PWM2_PCMP[7:0]
285E
PWM3_PPSCL,
PWM3_PCTRL
PWM3_PPSCL[15:8]
PWM3_PCTRL[7:0]
2860
PWM3_PPER
PWM3_PPER[15:8]
PWM3_PPER[7:0]
2862
PWM3_PLT
PWM3_PLT[15:8]
PWM3_PLT[7:0]
2864
PWM3_PHT
PWM3_PHT[15:8]
PWM3_PHT[7:0]
2866
PWM3_PCMP
PWM3_PCMP[15:8]
PWM3_PCMP[7:0]
2868
PWM4_PPSCL,
PWM4_PCTRL
PWM4_PPSCL[15:8]
PWM4_PCTRL[7:0]
286A
PWM4_PPER
PWM4_PPER[15:8]
PWM4_PPER[7:0]
286C
PWM4_PLT
PWM4_PLT[15:8]
PWM4_PLT[7:0]
286E
PWM4_PHT
PWM4_PHT[15:8]
PWM4_PHT[7:0]
2870
PWM4_PCMP
PWM4_PCMP[15:8]
PWM4_PCMP[7:0]
2872
PWM5_PPSCL,
PWM5_PCTRL
PWM5_PPSCL[15:8]
PWM5_PCTRL[7:0]
2874
PWM5_PPER
PWM5_PPER[15:8]
PWM5_PPER[7:0]
2876
PWM5_PLT
PWM5_PLT[15:8]
PWM5_PLT[7:0]
2878
PWM5_PHT
PWM5_PHT[15:8]
PWM5_PHT[7:0]
287A
PWM5_PCMP
PWM5_PCMP[15:8]
PWM5_PCMP[7:0]
289A
SPI1_SPSCR,
SPI1_SPCR
289C
SPI1_SPIBRR
289E
SPI1_SPIDR
28BE
IOCFG
28C0
IODEB
15
SPI_RF
REVISION 1.7 – 27. Apr 2020
14
SPI_TF
13
12
11
10
9
8
7
SPI_OVRF SPI_MOD SPI_FRSS SPI_MOD SPI_MSTR SPI_ERRIE SPI_RFIE
F
OEN
FEN
ONLY
6
SPI_TFIE
SPI1_SPIBRR[15:8]
4
3
SPI1_SPIDR[15:8]
SPI1_SPIDR[7:0]
LINRXIFRB
IOIFRB[7:0]
IODEB[11:8]
IODEB[7:0]
Page 65 of 182
2
SPI_BYTE SPI_MSTR SPI_CPOL SPI_CPHA
MOD
SPI1_SPIBRR[7:0]
unused
IODEB[15:12]
5
1
0
SPI_EN
SPI_CKEN
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Addres
s
Name
28C2
DRVCFG_EXT
15
14
13
12
DIS_OT
DIS_OC
DIS_UV
11
10
unused
9
OVPM
DIS_OV
OVTPM DIS_SHOA
8
UVPM
VDSPM
OCPM
DIS_DRV
28C6
DRVCFG
28C8
IOWU
unused
28CA
IOIN
unused
28CC
ANA_OUTG
28CE
ANA_OUTH
EN_LIN
AA_DAC
28D0
ANA_OUTI
SEL_UV_
VS
28D2
ANA_OUTK
28D4
ANA_OUTL
28D6
ANA_OUTM
IO5_OUTCFG[1:0]
IO4_OUTCFG[1:0]
IO3_OUTCFG[2:0]
IO2_OUTC
FG[2]
28D8
ANA_OUTN
IO7_OUTCFG[15:14]
IO6_OUTCFG[13:12]
unused
SOFT_TX
28DA
ANA_OUTO
28DC
ANA_OUTP
Tvds[1:0]
unused
SH3
SH2
PROV
unused
5
4
unused
DRV_CFG_T[7:6]
DRV_CFG_W[5:4]
SH1
CDEN
PRUV[2:0]
CDOUTEN EN_LINA
A
unused
RST1
0
CPDRV
CS_CAL
DIS_VDS
DRV_CFG_V[3:2]
RST2
SWI_DAC VCMO_SE
_OUT
L_LINAA
unused
DRV_CFG_U[1:0]
unused
unused
DIS_GTS
M
GAIN[3:0]
CALSLVTRM[1:0]
_DISTER _SLEEPB_
M
LIN
_LSM
TRMISR[1:0]
_HSM
_BYPASS
unused
TMRCFG_T2_INA
IO2_OUTCFG[1:0]
IO1_OUTCFG[2:0]
IO0_OUTCFG[2:0]
SOFT_IO[7:0]
TMRCFG_T1_INB
LINAA_DAC_IN[9:8]
TMRCFG_T1_INA
LINAA_DAC_IN[7:0]
Table 9.20 Ports Map Overview
REVISION 1.7 – 27. Apr 2020
1
T_DEAD
LIN_KEY
unused
2
IOWU[3]
INT_WU
INACTIVE_
OVT
SEL_TX_OUT[2:0]
TMRCFG_T2_INB
3
IO_DEB[7:0]
unused
SH4
6
unused
DEB_OC[1:0]
DIV [1:0]
7
Page 66 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
9.3.5 PWM
There are 5 programmable 16 bit PWM modules with frequencies 10…50kHz.
9.3.5.1 General introduction and features
The description refers to a single PWM module only. The mapping to the real PWM counts and resolution used
can be found following the functional description.
Characteristics of one PWM module are:
 PWM resolution of up to 16 bit
 Programmable prescaler.
 Programmable duty cycle: 0 – 100%.
 Programmable phase shift and/or output period with double buffers.
 Mirror mode with double buffer for symmetrical output waveform creation.
 Programmable interrupt output signal anywhere within the PWM period.
 Fix interrupt output signal when new programmable data becomes active (PWM -Counter == 0 and
Master mode active)
 supports synchronized operation between multiple PWM modules (Master-Slave)
Warning:
Although the PWM signal can be set to any duty-cycle from 0% to 100%, the analog driver part connected to it is
not able to follow any duty-cycle. The minimum pulse that can be seen correctly on the driver outputs (U, V, W,
T) is 2us long.
This means that:
 at 25kHz, a signal with duty-cycle outside the 5% to 95% range will not be generated properly on the
driver output.
 at 10kHz, a signal with duty-cycle outside the 2% to 98% range will not be generated properly on the
driver output.
9.3.5.2 Block diagram and description
The functional block diagram of one PWM module is shown in Figure below. This diagram is identical for the
three implemented PWMs.
REVISION 1.7 – 27. Apr 2020
Page 67 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Master control inputs
SET_EXT
Mirror mode
= SET_OUT from MASTER
CNT
Update Shadow
Buffers Logik
SET_OUT
Low threshold (PLT)
SET_OUT
PLT
PLT shadow buffer
EXT
FPWMO
Mirror Pulse
Generation
PWMO
1
0 sel
CNT_EXT
Comparator
PLT ≤ CNT ≤ PHT
= CNT from MASTER
MODE
PLT
Period register (PPER)
SET_OUT
PHT
PHT shadow buffer
PPER shadow buffer
FPWMO
SET_OUT
High threshold (PHT)
1
CK
Prescaler
Counter with Jitter
add capability
0 sel
Independent mode
EXT
JI
Prescaler control
register (PPSCL)
CNT
CNTI
Counter equal to 0
CMPI
Equality Comparator
Compare reg (PCMP)
RSTB
EXT
EBLK
MODE
EPI
JI
SET_OUT
CNT
ECI
Control register (PCTRL)
Interrupt generation
Slave control
output(s)
Figure 9-16: Functional diagram of one PWM module.
One PWM module is programmed by the following IO ports:
PCTRL :
contains control and flag bits, determines the global operating state
PPER :
defines the PWM period duration in number of PWM clocks
PPSCL :
PWM prescaler, defines the relation from system to PWM clock
PLT, PHT:
low and high threshold ports define the PWM output shape
PCMP :
compare port determines the time for the programmable PWM interrupt
Each PWM module supports two main schemes to impact the shape of the generated output signal:
Independent mode, see paragraph 9.3.5.4 , or
Mirror mode, see paragraph 9.3.5.5
In mirror mode the output is a pulse centered on the middle of the output period,
In independent mode the duty cycle and the phase shift of the output are controlled by software with two
threshold levels.
Following PWM parameters are programmable by software:
 PPER: periode register
 PLT, PHT: 2 edges within the PWM period by 2 threshold values, low and high. Those thresholds
define duty cycle and phase shift in independent, or pulse length in mirror mode.
 PCMP :compare register, which triggers the PWM compare interrupt
These three parameters PPER, PLT and PHT are double buffered and updated at the end of the current output
period (CNT==0). This double buffer system prevents unexpected output waveform while modifying parameters.
REVISION 1.7 – 27. Apr 2020
Page 68 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
A programmable synchronous counter defines the period of the corresponding PWM output. A programmable
prescaler fixes the ratio between the clock of this counter and the input clock frequency.
The PWM module can create 2 interrupts, the fix counter interrupt CNTI at counter = 0, and the programmable
PWM compare interrupt CMPI. The compare interrupt triggers, when the internal counter reaches the value
programmed into port PCMP.
9.3.5.3 PWM frequency control
The PWM frequency is programmable by the ports PPSCL and PPER. The PPER port is not reset, it needs an initial
write before enabling a PWM module.
The PWM counters clock selector is controlled by the port PPSCL. The value of this port is not buffered and can
be updated at any time.
The period length value PPER is double buffered, its update is effective when the counter value CNT is equal to
00h. The PPER value is hardware limited to FEh, even if the PPER port is written to FFh, the shadow register will
be updated to FEh.
The frequency Fcnt of the PWM counter is given by the following equation:
Fcnt 
Equation 2
Where: Fck
Fcnt
M
N
Fck
M  1

1
2 
N
: PWM input frequency; equal to the PLL clock or the oscillator clock OSC.
: clock frequency of PWM internal counter
: Programmed predivider between 0 and 15. Value fixed in IO port PPSCL[7:4].
: Programmed predivider between 0 and 11. Value fixed in IO port PPSCL[3:0].
And the frequency Fpwmo of the PWM output PWMO is given by the equation:
Equation 3
Fpwm 
Fcnt
PPER  1
Where: Fpwm : PWM frequency
PPER : programmed period width, internal counter CNT is restarted,
when this value is reached.
Both equations can be combined as follows:
Equation 4
Fpwm 
Fck
1
1
 N 
M  1 2
PPER  1
 
9.3.5.3.1 PWM frequency parameter selection
When determining the parameters for the PWM frequency it needs to be taken into consideration, that there are
overlapping PWM frequency ranges:
REVISION 1.7 – 27. Apr 2020
Page 69 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Fck / 2N-1
Fck / 2N
Fck / 2N+1
PWM output resolution
PPERmax
PPERmax / 2
PWM output frequency
Figure 9-17: Relation between PWM resolution and frequency (M=0)
This reflects the PWM frequency formula as given below:
Fpwm 
Fck
1
1
 N 
M  1 2
PPER  1
 
Equation 5
For operating at highest possible resolution with the PWM frequency needed, the following definition scheme is
recommended:
 Select first the minimum value for N (PPSCL[3:0])
 select the maximum value for the period PPER
 choose the M value (PPSCL[7:4]) so that the target PWM frequency requirements are met
Example:
Assumptions:
PWM with 24kHz at max resolution is needed,
Fck=30MHz
Definition steps:
 start with N=0, M=0
 (PPER-1) = Fck/Fpwm = 32MHz / 24kHz = 1333
 PPER = 1332 => Fpwm = 32MHz/1333 = 24.01 kHz
 max resolution possible is > 10 bit (10bit=1024, 11bit=2048) for M = 0
9.3.5.4 Synchronization of the PWM modules
The PWM unit provides the synchronous operation of multiple PWM modules.
Synchronization means the PWM modules are running on one PWM counter at the same frequency, but with
different pulse shape.
To allow this, the PWM modules are connected internally in a daisy-chain-like hierarchical scheme.
PWM1
REVISION 1.7 – 27. Apr 2020
PWM2
PWM3
...
PWMx
Page 70 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Figure 9-18: internal daisy chain connection of PWM modules.
The PWM module generating the time regime is called “master”, the block running on an external counter (or
frequency resp.) is referred to as “slave”.
Every PWM module can be either master or slave to the previous one. A single master following multiple slaves is
also possible; all share then the time base of the master.
MASTER
SLAVE
SLAVE
MASTER
EXT=0
EXT=1
EXT=1
EXT=0
Figure 9-19: sample configurations with multiple master and slave modules.
This bit EXT controls if a PWM module operates as master or slave. EXT=1 means a PWM module is slave to the
previous PWM module.
After Reset all PWM modules act as independent masters, not taking into account the external connections.
9.3.5.5 Independent mode
In independent mode the duty cycle and the phase shift of the output are controlled by software with the two
threshold levels PHT and PLT. The independent mode ist the default operating scheme of the PWM modules, it
corresponds to the control bit MODE set to 0.
Assuming
 The control bit MODE is low,
 TCK is the input clock period,
 TCNT is the counter clock period
 The low threshold value PLT is lower than the high threshold value PHT, and
 The high threshold value HT is lower than the period value PPER,
the PWM output signal PWMO is depicted in Figure 9-20, the duty cycle is defined by the equation:
DCpwm 
Equation 6
Thigh
PHT  PLT 

PPER  1 PPER  1
output period, PPER + 1
TCNT
PWMO
Thigh = PHT-PLT
1
0
CNT=0
CNT=PLT
CNT=PHT
CNT=PPER
Figure 9-20: PWM output signal in independent mode.
REVISION 1.7 – 27. Apr 2020
Page 71 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
The compare always uses the PLT and PHT values in the shadow registers only, therefore the ports can be
updated at any time. The port values are transferred only after the PLT register was written, when the PWM
counter CNT getting equal to 0.
If the PWM module operates as slave (bit EXT=1 in PCTRL port), the external counter input CNT_EXT with the
master counter is used instead of the internal counter. The write of the masters PLT register will enable the
transfer of the threshold values and the period into the shadow registers for the slaves as well.
Special cases:
 PPER=0 : PWMO is frozen to the state being active at shadow register update
 PHT < PLT, PHT and PLT < PPER : identical phase shift and duty cycle, inverted PWMO signal
 PLT < PPER < PHT : PWMO stays at always high
 PHT < PPER < PLT : PWMO stays at always low
 PLT and PHT > PPER: PWMO is frozen to the state being active at shadow register update
 PHT = PLT, PHT and PLT < PPER : PWMO stays at always low
9.3.5.6 Mirror mode
When the control bit MODE is high, the mirror mode is selected. The output waveform will be a pulse with the
length specified in PLT port, centered in the PWM period (PPER+1).
Assuming
 The control bit MODE is high,
 TCK is the oscillator clock period,
 TCNT is the counter clock period,
The pulse length value PLT is lower than the period value PPER,
In such mode, the PWM output signal PWMO is depicted in Figure 9-21, and the duty cycle is defined by the
equation:
Thigh
PLT

PPER  1 PPER  1
Once the value Thigh has been written in the IO port PLT_x, the low and high threshold are update as follow:
The low threshold LT is computed and the resulting value is used to set LT , i.e. the previous value is discarded. If
this result is lower than 0, i.e. LT > PER, PWM, data are forced to 00h and the output PWMO will be forced to 0.
The high threshold HT is computed and the resulting value is use to set HT. If this result is greater than PER, i.e. LT
> PER, the output PWMO will be forced to 1.
The new desired pulse length value is memorized in buffer. Due to this double buffer mechanism, threshold
values can be updated at any time.
Equation 7
DCpwm 
Important: The new desired period value PER must be updated before LT.
REVISION 1.7 – 27. Apr 2020
Page 72 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
output period, PPER + 1
Thigh (↔ PLT)
TCNT
PWMO
Thigh/2
1
0
CNT=0
CNT=(PPER+1) / 2
CNT=(PPER+1)/2 – PLT/2
CNT=PPER
CNT=(PPER+1)/2 + PLT/2
Figure 9-21: PWM output signal in mirror mode.
In mirror mode the LT and HT values are recalculated only after the PLT port was written, when the PWM
counter CNT getting equal to 0
If the PWM module operates as slave (bit EXT=1 in PCTRL port), the external counter input CNT_EXT with the
master counter is used instead of the internal counter. The write of the masters PLT register will enable the write
of the shadow registers for the slaves as well.
Special cases:
 PLT = 0 : PWMO stays at always low
 PLT > PPER: PWMO stays at always high (also valid for PPER=0 )
9.3.5.7 PWM control and command ports
Most of the ports are not reset during power up. It is recommended to set all PWM related ports to a correct
value before releasing the RSTB bit in the control register PCTRL.
All the IO ports involved in PWM programming are resumed in Table 9.21 to Table 9.26:
IO port: PLT
Bit[7]
Access mode: Word – Read and Write
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
PLT[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
PLT[15:8]
Table 9.21: PWM ports – Low Threshold. (no Reset)
PLT[15:0]:
Low threshold level for PWM
IO port: PHT
Bit[7]
Access mode: Word – Read and Write
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
PHT[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
PHT[15:8]
REVISION 1.7 – 27. Apr 2020
Page 73 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Table 9.22: PWM ports – High Threshold. (no Reset)
PHT[15:0]:
High threshold level for PWM
Due to a double buffer mechanism the port values PHT and PLT can be updated at any time.
Writing the PWM low threshold (PLT) enables the transfer of the port values into the double-buffer shadow
registers by default. The shadow registers will be written next time the counter CNT gets equal 0.
IO port: PCMP
Bit[7]
Access mode: Word, - Read and Write
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
PCMP[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
PCMP[15:8]
Table 9.23: PWM bits – Compare Threshold. (no Reset)
PCMP[15:0]:
Compare level for PWM, not RESET!
The PWM comparator value PCMP is used to generate interrupt independently of the threshold values.
This interrupt signal CMPI will be high active during one period of CK. An interrupt is generated when control bit
PECI is high and CNT reaches the value of PCMP.
IO port: PPER
Bit[7]
Access mode: Word – Read and Write
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
PPER[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
PPER[15:8]
Table 9.24: PWM bits – Period value. (no Reset)
PPER[15:0]:
Period value for PWM (read the current value, after double buffer), no RESET!
IO port: PCTRL
Access mode: Byte – Read and Write
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
-
-
-
PWM_ECI
PWM_EPI
PWM_MODE
PWM_EXT
PWM_EBLK
Table 9.25: PWM ports – control bits. (Reset=00h)
unused
PWM_ECI:
Enable control for PWM comparator interrupt PCMPI
1 = interrupt output enabled
0 = interrupt output is forced to 0
PWM_EPI:
Enable control for PWM counter interrupt PCNTI
1 = interrupt output enabled
0 = interrupt output is forced to 0
Mode selector
1 = Mirror mode
0 = Independent mode
PWM_MODE:
PWM_EXT:
External counter selector
1 = PWM in slave mode, CNT=CEXT
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0 = PWM in master mode, CNT=CINT
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PWM_EBLK:
Enable signal
1 = PWM module enabled
0 = PWM module disabled
The prescaler port PPSCL controls the bits PWM_PRDV1[3:0] and PWM_PRDV0[3:0]. The IO port update can be
done at any time.
IO port: PPSCL
Bit[7]
Access mode: Byte – Read and Write
Bit[6]
Bit[5]
Bit[4]
Bit[3]
PWM_PRDV1[3:0]
Bit[2]
Bit[1]
Bit[0]
PWM_PRDV0[3:0]
Table 9.26: PWM ports – Prescaler value. (Reset=00h)
PWM_PRDV1[3:0]:
PWM prescaler, first part; clock frequency divided by ‘PWM_PRDV1[3:0]+1’
PWM_PRDV0[3:0]:
PWM prescaler, second part; clock frequency divided by ‘2 PWM_PRDV0[3:0]’
9.3.5.8 Interrupts connections
The PWM interrupts are connected into MULAN3 external interrupts block.
9.3.6 Timers
9.3.6.1 Introduction and Features
The MLX81325 comprises a Timers block with 2 Timers modules. Each of those timers are identical, and can work
in one of the following main function modes:
 Single 16-bits auto-reload timer
 Dual 16-bits timer compare
 Dual 16-bits timer capture
 16-bits timer compare and capture
 Single 16-bits pulse accumulator
 Programmable single input debouncer
 High resolution 16-bits PWM (no shadow register)
The Timer blocks are used in association with the MLX16x8. According to the selected mode the block generates
one digital output signal and up to 5 edge sensitive interrupt signals.
A programmable and resettable 16-bits synchronous counter is the principal part of a Timer block; and, except
for the Pulse accumulator mode, a programmable pre-divider fixes the ratio between the clock of this counter
and the input clock frequency.
For each exclusive mode, different parameters are programmable by software:
In Single 16-bits auto-reload timer mode:
 The pre-divider ratio between the CPU clock and the 16-bits timer clock
In Dual 16-bits timer, compare mode:
 The pre-divider ratio between the CPU clock and the 16-bits timer clock
 The two values to be compared to the 16-bits timer value
 In Dual 16-bits timer capture:
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

The pre-divider ratio between the CPU clock and the 16-bits timer clock
The active edge of each channel:
Rising or Falling, or Rising and falling
In 16-bits timer compare and capture mode:
 The pre-divider ratio between the CPU clock and the 16-bits timer clock
 The value to be compared to the 16-bits timer value

The active edge of the capture channel
Rising, or Falling, or Rising and falling
In Single 16-bits pulse accumulator mode:
 The active edge
Rising, or Falling, or Rising and falling
In Programmable single input debouncer mode:
 The debounce delay
In High resolution 16-bits PWM (no shadow register) mode:
 The period of the PWM output signal
 The duty cycle of the PWM output signal
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9.3.6.2 Block diagram and description
The functional block diagram of one Timer block is shown in the picture below. This diagram is identical for all
implemented Timers.
Channel B
Mode selector
TIMx_MODE[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Function
Timer
Dual timer compare
Dual timer capture
Timer capture/compare
Pulse accumulator
Debouncer
P.W.M.
not used (U.A.R.T.)
TREGB_x
Channel A
16 -bit register
TREGA_x
(TIMx_CAPB / TIMx_CMPB)
16-bit register
(TIMx_CAPA / TIMx_CMPA)
Equalty comparator
(EQ)
Equalty comparator
(Tx_EQ)
Edge selector
(EDGA)
Edge selector
(Tx_EDGA)
TxREGB
TxREGA
DATA
RESET
INTERRUPT
INTERRUPT
Interrupts
block
selector
Tx_INT1
Tx_INT2
Tx_INT3
Tx_INT4
Tx_INT5
INTERRUPT
EN_DIV
CK
Pre-divider
PCK
DATA
16-bit up counter
Tx_OUT_DEB
RESET
output
block
selector
TCNT_x
Control register
TIMx_DIV
TIMx_MODE
TIMx_ENCMP
TIMx_OVR
TIMx_DOUT
TIMx_EDGB
TIMx_EDGA
TIMx_START
TIMx_EBLK
Tx_OUT_PWM
DATA
RESET
TCTRL_x
Figure 9-22: Functional diagram of one Timer block.
Note: The symbol ‘x’ should be replaced depending on the Timer.
The IO port associated to the Control and flag bits, e.g. TIMx_EXT, is the port TCTRL_x.
The IO port associated to the counter value TIMx_CNT is the port TCNT_x.
The IO ports associated to the TIMER are the ports TREGA_x and TREGB_x.
The mode in which Timer unit work is defined by the control bits TIMx_MODE[2:0]. All modes use a common set
of hardware according to the selected mode:
 The hardware is connected or not to the input and output pins.
 Up to 5 interrupts signals Tx_INT[5:1] are generated. All interrupt are rising-edge sensitive and high
during one period of the main clock CK
 The digital output Tx_OUT_DEB is only active in Debouncer mode.
 The digital output Tx_OUT_PWM is only active in PWM mode.
9.3.6.3 Timer mode
9.3.6.3.1 Functional block diagram
This mode allows the block to generate an interrupt Tx_INT4, so called INT_TIMER, at fixed intervals.
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EN_DIV
TCNT_x
CNT_CK
Pre-divider
16-bit up counter
CK
RST
TIMx_CNT
2
TIMx_OUT_GE
16
Greater or Equal comparator
(TxGE)
control register
TX_INT1
Tx_INT2
INT_TIMER
Interrupts
block
Tx_INT3
Tx_INT4
Tx_INT5
unused
INT_TIMER
unused
16
TIMx_DIV0
TIMx_DIV1
TIMx_START
TIMx_CMPB
TCTRL_x
TREGB_x
Channel B
Figure 9-23: Timer block diagram.
Note: The symbol ‘x’ should be replaced by 1 or 2 depending on the Timer.
The IO port associated to the Compare value TIMx_CMPB is the port TREGB_x.
The counter clock, CNT_CK, is the CPU clock, CK, divided by a pre-defined number, TIMx_DIV, being 1, 16 or 256.
The counter is incremented on CNT_CK rising edge and a pre-defined comparator value, TIMx_CMPB, is loaded in
the 16-bits IO port TREGB_x.
The comparator output, TIMx_OUT_GE, is set to 1 if the counter value, TIMx_CNT, is bigger than or equal to
TIMx_CMPB. And the counter will be reset to ‘0000h’ on the next CK rising edge.
An interrupt, Tx_INT4=INT_TIMER, is generated if:
 the counter reaches the pre-defined comparator value, TIMx_CMPB, or if
 a new comparator value, TIMx_CMPB, bigger than the current counter value, CNT, is loaded in
IO_port TREGB_X.
This interrupt must be connected to a rising-edge sensitive interrupt input.
Assuming TIMx_CMPB<>0x0000, and clock enabled input EN_DIV=1, the period, TINT_TIMER, of the interrupt signal
INT_TIMER is given by the following equations:
Equation 8
FCNT_CK 
Equation 9
TINT_TIMER 
Equation 10
FINT_TIMER 
REVISION 1.7 – 27. Apr 2020
Fck
TIM x_DIV
TIMx_DIV
  TIMx_CMPB 1
Fck
1
TINT_TIMER

Fck
1

TIMx_DIV TIMx_CMPB 1 
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Or, if the comparator value TIMx_CMPB is extracted from the equation:

Fck
1
TIMx_CMPB 

TIMx
_
DIV
F
INT _ TIMER

Equation 11

 1

Where: Fck is the frequency of the CPU clock,
FCNT_CK is the frequency of the 16-bits up counter, and
TIMx_DIV = 1, 16, or 256.
If TIMx_CMPB=0x0000 the interrupt signal, INT_TIMER is frozen to 1.
9.3.6.3.2 Output signals
The different possibilities for the output signal are summarized Table 9.27.
TIMx_START
1
TIMx_CMPB
INT_TIMER
<> 0000h
TINT_TIMER
0
1
NOTES
= 0000h
TINT_TIMER 
TIMx_DIV
  TIMx_CMPB 1
Fck
TIMx_CMPB
stay endlessly to '1'
- 16-bits up counter reset to 0000h.
stay endlessly to '0'
- Timer mode is disabled.
- 16-bits up counter reset to 0000h.
1
0
0
0
0
Table 9.27: Timer output signal.
9.3.6.3.3 Usage and example
Typical usage: Timers
Example: Generating an interrupt every 11ms with an oscillator of 20 MHz.
With a pre-divider TIMx_DIV = 1:
TIMx_CMPB = (11E-3 * 20E6 / 1 ) - 1 = 21999910 = 35B5F8. Greater than 6553610 = FFFF8,
thus not valid
With a pre-divider TIMx_DIV = 16:
TIMx_ CMPB = (11E-3 * 20E6 / 16) - 1 = 1374910 = 35B58
SO using a pre-divider of 16 and a compare value of 0x35BF gives an interrupt period of 11ms.
9.3.6.4 Dual Timer Compare mode
9.3.6.4.1 Functional block diagram
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Channel A
TREGA_x
TIMx_CMPA
16
Greater or Equal comparator
(TxGE)
EN_DIV
CK
INT_CMPA
Pre-divider
TIMx_CNT
16
TCNT_x
Interrupts
block
CNT_CK
16-bit up counter
RST
TIMx_CNT
TIMx_OUT_GE
Tx_INT4
Tx_INT5
unused
INT_CMPA
unused
INT_CMPB
unused
16
Greater or Equal comparator
(TxGE)
control register
Tx_INT1
Tx_INT2
Tx_INT3
INT_CMPB
16
TIMx_START
TIMx_ENCMP
TIMx_CMPB
TCTRL_x
Channel B
TREGB_x
Figure 9-24: Dual timer compare block diagram.
Note: The symbol ‘x’ should be replaced by 1 or 2 depending on the Timer.
The IO ports associated to the Compare values TIMx_CMPA and TIMx_CMPB are the ports TREGA_x and
TREGB_x.
This mode uses the 16-bits counter as a free running counter. The counter clock, CNT_CK, is the CPU clock, CK,
divided by a pre-defined number, TIMx_DIV, being 1, 16 or 256. The counter is incremented on the CNT_CK rising
edge.
Two pre-defined comparator values, TIMx_CMPA and TIMx_CMPB, are loaded in the 16-bits IO ports TREGA_x
and TREGB_x.
The comparator output, TIMx_OUT_GE, is set to 1 if the counter value, TIMx_CNT, is bigger than or equal to
TIMx_CMPB. And the counter will be reset to ‘0000h’ on the next CNT_CK rising edge.
An interrupt, Tx_INT2=INT_CMPA, is generated when the counter value is equal to the pre-defined comparator
value TIMx_CMPA.
This interrupt must be connected to a rising-edge sensitive interrupt input.
The programmed time for this interrupt signal, TINT_CMPA, is given by the following equation:
Equation 12
TINT_CMPA 
TIMx_DIV
 TIMx_CMPA 1
Fck
Where: Fck is the frequency of the CPU clock, and
TIMx_DIV = 1, 16, or 256.
An interrupt, Tx_INT4=INT_CMPB, is generated if:
 the counter reaches the pre-defined comparator value, TIMx_CMPB, or if
 a new comparator value, TIMx_CMPB, greater than the current counter value, TIMx_CNT, is loaded
in port TREGB_x.
This interrupt must be connected to a rising-edge sensitive interrupt input.
The programmed time for this interrupt signal, TINT_CMPB, is given by the following equation:
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TINT_CMPB 
Equation 13
TIMx_DIV
 TIMx_ CMPB 1
Fck
The reset of the 16-bits counter is controlled with the control bits TIMx_ENCMP and TIMx_START.
Assuming bit TIMx_START is high and TIMx_CMPB<>0x0000
If TIMx_ENCMP is set to 1, the 16-bits counter is reset when its value reaches the comparator value
TIMx_CMPB.
The programmed time for interrupts INT_CMPA and INT_CMPB is given by Equation 12 and Equation 13.
Then if the bit TIMx_START is not set to 0 by CPU, the counting sequence is repeated indefinitely.
And the frequency at which the interrupt signals are generated is given by Equation 14.
Equation 14
FINT_CMPA  FINT_CMPB  FOUT 
1
Fck
1


TOUT TIMx_DIV TIMx_CMPB  1
Or, if the comparator value TIMx_CMPB is extracted from the equation:

Fck
1 
TIMx_CMPB 

 1
TIMx_
DIV
F
OUT 

Equation 15
If TIMx_ENCMP is set to 0, the 16-bits counter will be reset when the maximum counting value 0xFFFF is
reached.
The programmed time for interrupts INT_CMPA and INT_CMPB is given by Equation 12 and Equation 13. But if
the counter is running indefinitely, the frequency at which the interrupt signals are generated is given by:
Fck
1

TOUT TIMx_DIV 65536
Where: Fck is the frequency of the CPU clock, and
TIMx_DIV = 1, 16, or 256.
FOUT 
Equation 16
1

9.3.6.4.2 Output signals
The different possibilities for the output signals are summarized Table 9.28.
TIMx_S TIMx_E
TART NCMP
1
0
TIMx_CMPB TIMx_CMPA
-
INT_CMPA / INT_CMPB
< TIMx_CMPB
NOTES
TOUT
TOUT 
INT_CMPA
TIMx_DIV
 65536
Fck
INT_CMPB
0
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TIMx_CMPA
TIMx_CMPB
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TIMx_S TIMx_E
TART NCMP
TIMx_CMPB TIMx_CMPA
INT_CMPA / INT_CMPB
> TIMx_CMPB
NOTES
TOUT
INT_CMPA
0
INT_CMPB
0
1
1
<> 0x0000
< TIMx_CMPB
TIMx_CMPA
TIMx_CMPB
TOUT
TOUT 
INT_CMPA
TIMx_DIV
 TIMx_CMPB  1
Fck
INT_CMPB
0
> TIMx_CMPB
65535
TIMx_CMPA
TOUT
INT_CMPA
0
INT_CMPB
0
1
1
= 0x0000
TIMx_CMPA
65535
<> 0x0000
INT_CMPA
0
stay endlessly to '0'
- 16-bits counter reset to
0000h.
stay endlessly to '1'
INT_CMPB
1
0
= 0x0000
stay endlessly to '1'
INT_CMPA
1
INT_CMPB
1
stay endlessly to '1'
0
0
-
-
-
INT_CMPA
INT_CMPB
0
stay endlessly to '0'
0
stay endlessly to '0'
0
- Timer Compare mode
disabled
- 16-bits counter reset to
0000h.
Table 9.28: Timer compare output signals.
9.3.6.4.3 Usage and example
Typical usage: Delays
Example: Generating an interrupt on channel 1 in 100ms with an oscillator of 20 MHz and a pre-divider value,
DIV, set to 256.
 Read the counter. For example, counter value TIMx_CNT is equal to 1000 10 = 03E88.
 Add the value
DELAY = ( Tint1 * Fck / TIMx_DIV ) – 1 = (0.1 * 20E6 / 256) -1 = 7811 10 = 1E838
 Load the new value, TIMx_CMPB = TIMx_CNT + DELAY = 1000 10 + 781110 = 881110 = 226B8.
If the new loading value TIMx_CMPB is bigger than 6553510 (=FFFF8), take account that TIMx_CMPB values are
identical modulo 216: if the calculation gives TIMx_CMPB=7553510 (=1270F8), it must be replaced by
TIMx_CMPB=999910 (=270F8).
9.3.6.5 Dual Timer Capture mode
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9.3.6.5.1 Functional block diagram
Channel A
INT_CAPA
IN_CAPA
TREGA_x
Edge selector
(TxEDGA)
CK
TIMx_CAPA
TIMx_CNT
OVRA
16
EN_DIV
TCNT_x
CNT_CK
Pre-divider
CK
RST
16-bit up counter
INT_OVF
Tx_INT1
control register
TIMx_EDGB1 TIMx_EDGA1
TIMx_EDGB0 TIMx_EDGA0
Interrupts
block
TIMx_START
TCTRL_x
TIMx_CNT
16
Tx_INT2
Tx_INT3
Tx_INT4
Tx_INT5
INT_CAPA
OVRA
INT_OVF
OVRB
INT_CAPB
IN_CAPB
Edge selector
(TxEDGB)
CK
OVRB
TIMx_CAPB
TREGB_x
INT_CAPB
Channel B
Figure 9-25: Dual timer capture block diagram.
Note: The symbol ‘x’ should be replaced by 1 or 2 depending on the Timer speaking about.
The IO ports associated to the Capture values TIMx_CAPA and TIMx_CAPB are the ports TREGA_x and TREGB_x.
This mode uses the 16-bits counter as a free running counter. The counter clock, CNT_CK, is the CPU clock, CK,
divided by a pre-defined number, TIMx_DIV, being 1, 16 or 256. The counter is incremented on the CNT_CK rising
edge.
The input signal, IN_CAPA, is sampled by CPU clock, CK, and when an event is detected on channel A:
 The content of the free-running counter TIMx_CNT is saved in the 16-bits IO port TREGA_x,
 An interrupt, Tx_INT1=INT_CAPA, is generated.
The edge selector can be programmed with the control bits TIMx_EDGA[1:0] to detect the following events:
rising, falling, or rising and falling edges.
The input signal, IN_CAPB, is also sampled by CPU clock CK, and when an event is detected on channel B:
 The content of the free-running counter is saved in the 16-bits IO port TREGB_x,
 An interrupt, Tx_INT5=INT_CAPB, is generated.
The edge selector can be programmed with the control bits TIMx_EDGB[1:0] to detect the following events:
rising, falling, or rising and falling edges.
An interrupt, Tx_INT3=INT_OVF, is generated when the counter overflows, i.e. reaches the values 65535. Using
this interrupt the counter length can be extended by software.
The interrupt signals, Tx_INT2=OVRA and Tx_INT4=OVRB, respectively controlled by channel A and B, are
generated if two consecutive capture actions occur without CPU reading operation in between. The first value
memorized in the corresponding port is not overwritten. Be aware on interrupt management (priority, clear
pending operation) because up to 5 interrupt can be generated in the same time.
The interrupts INT_CAPA, INT_CAPB, and INT_OVF must be connected to rising-edge sensitive interrupt inputs.
The reset of the 16-bits counter is controlled with the control bit TIMx_ENCMP.
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If TIMx_ENCMP is set to 1, the 16-bits counter is reset when an event on IN_CAPB has been detected and after
the counter value had been transferred into TIMx_CAPB.
If TIMx_ENCMP is set to 0, the 16-bits counter will be reset when the maximum counting value 0xFFFF is
reached.
9.3.6.5.2 Output signals
The functionality of the Timer unit in Capture mode is summarized Table 9.29.
TIMx_S INT_CAPA / OVRA
TART
1
INT_CAPB / OVRB
event
detected (1)
event
CPU
detected (1) read
TIMx_CAPA
updated
TIMx_CAPA
not updated
NOTES
-
(1) According to the
programming of the
edge selector EDGA.
INT_CAPA
OVRA
1
-
event
detected (2)
event
CPU
detected (2) read
(2) According to the
programming of the
edge selector EDGB.
INT_CAPB
OVRB
0
INT_CAPA
OVRA
0
stay endlessly to '0'
0
stay endlessly to '0'
0
INT_CAPB
OVRB
TIMx_CAPB
updated
TIMx_CAPB
not updated
0
stay endlessly to '0'
0
stay endlessly to '0'
0
- Timer Capture mode
disabled
- 16-bits counter reset to
0000h.
Table 9.29: Timer capture output signals.
9.3.6.5.3 Usage and example
Typical usage: Time stamping events.
9.3.6.6 Timer Capture/Compare mode
9.3.6.6.1 Functional block diagram
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Channel A
TREGA_x
TIMx_CMPA
16
Equality comparator
(TxEQ)
TIMx_CNT
INT_CMPA
16
EN_DIV
CNT_CK
Pre-divider
CK
RST
16-bit up counter
control register
TIMx_EDGB1
TIMx_EDGB0
2
INT_OVF
TCNT_x
Interrupts
block
TIMx_START
TIMx_CNT
16
TCTRL_x
Tx_INT1 unused
INT_CMP
Tx_INT2
A
Tx_INT3
INT_OVF
Tx_INT4
OVRB
Tx_INT5
INT_CAPB
IN_CAP2
Edge selector
(TxEDGB)
CK
OVRB
TIMx_CAPB
TREGB_x
INT_CAPB
Channel B
Figure 9-26: Timer compare/capture block diagram.
Note: The symbol ‘x’ should be replaced by 1 or 2 depending on the Timer speaking about.
The IO port associated to the Compare value TIMx_CMPA is the port TREGA_x.
The IO port associated to the Capture value TIMx_CAPB is the port TREGB_x.
Compare Channel A
This mode uses the 16-bits counter as a free running counter. The counter clock, CNT_CK, is the CPU clock, CK,
divided by a pre-defined number, TIMx_DIV, being 1, 16 or 256. The counter is incremented on the CNT_CK rising
edge.
Assuming bit TIMx_START is high,
 the 16-bits counter is reset when its value reaches the maximum counting value 0xFFFF.
 An interrupt, Tx_INT1=INT_CMPA, is generated when the counter value TIMx_CNT is equal to the
pre-defined comparator value TIMx_CMPA.
 The programmed time for this interrupt signal, T INT_CMPA, is given by the following equation:
TIMx_ DIV
 TIMx_ CMPA  1
Fck
Where: Fck is the frequency of the CPU clock, and
TIMx_DIV = 1, 16, or 256.
Equation 17
REVISION 1.7 – 27. Apr 2020
TINT_CMPA 
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As long as the bit TIMx_START is not set to 0, the counting sequence is repeated indefinitely; and the frequency
at which the interrupt signals is generated is given by Equation 18:
FOUT 
Equation 18
Fck
1

TIMx_ DIV 65536
Capture Channel B
The input signal, IN_CAPB, is sampled by CK, and when an event is detected on channel input B:
 The content of the free-running counter is saved into the 16-bits IO port TREGB_x,
 An interrupt, Tx_INT5=INT_CAPB, is generated.
The edge selector can be programmed with the control bit TIMx_EDGB[1:0] to detect the following events: rising,
falling, or rising and falling edges.
An interrupt, Tx_INT3=INT_OVF, is activated when the counter overflows. The counter length can be extended by
software using this interrupt.
The interrupt signal, Tx_INT4=OVRB, is generated if two consecutive capture actions occur without CPU reading
operation in between. The first value TIMx_CAPB, memorized in port TREGB_x, is not overwritten.
The interrupts signals Tx_INT2=INT_CMPA, INT_CAPB, INT_OVF must be connected to rising-edge sensitive
interrupt inputs.
9.3.6.6.2 Output signals
The functionality of the Timer unit in Compare/Capture mode is summarized Table 9.30.
TIMx INT_CMPA
STAR
T
1
INT_CAPB / OVRB
TINT_CMPA
NOTES
-
FOUT
INT_CMPA
FOUT
0
1
TIMx_CMPA
65535
-
DIV
 TIMx _ CMPA  1
Fck
Fck
1


TIMx_ DIV 65536
TINT_CMPA 
event
detected (2)
event
CPU
detected (2) read
TIMx_CAPB
updated
TIMx_CAPB
not updated
(2) According to the programming
of the edge selector EDGB.
INT_CAPB
OVRB
0
INT_CAPB
INT_CMPA
stay endlessly to '0'
0
CMPA
OVRB
0
stay endlessly to '0'
0
65535
stay endlessly to '0'
- Timer Compare/Capture mode
disabled
- 16-bits counter reset to 0000h.
0
Table 9.30: Timer Compare/Capture output signals.
9.3.6.7 Pulse accumulator mode
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9.3.6.7.1 Functional block diagram
EN_DIV
IN_ACC
CK
Tx_INT1
TCNT_x
Edge Setector
(TxEDGA)
Tx_INT2
Tx_INT3
Tx_INT4
Tx_INT5
CNT_CK
INT_OVF
RST
16-bit up counter
Interrupts
block
2
control register
TIMx_EDGA1
TIMx_EDGA0
unused
INT_OVF
unused
TIMx_START
TCTRL_x
Figure 9-27: 16-bits pulse accumulator block diagram.
Note: The symbol ‘x’ should be replaced by 1 or 2 depending on the Timer.
This mode uses the 16-bits counter as an event counter. The clock of the counter CNT_CK is the CPU clock, CK,
controlled by EN_DIV.
The input signal, IN_ACC, is sampled by CK when input EN_DIV is high, and when an event is detected the counter
is incremented by 1. The edge selector can be programmed to detect the following events on IN_ACC: rising,
falling, or rising and falling edges.
If the control bit TIMx_START is low the Pulse accumulator mode is disabled and output INT_OVF is frozen to 0.
An interrupt, Tx_INT3=INT_OVF, is generated when the counter overflows, i.e. value 65535 is reached. Using this
interrupt the counter length can be extended by software. This interrupt signal must be connected to a risingedge sensitive interrupt inputs.
9.3.6.7.2 Output signals
The input to monitor, IN_ACC, passes through an edge selector block that can be programmed to detect the
following events:
 Rising edges
 Falling edges
 Rising and falling edges
The active edge is selected with the control bits TIMx_EDGA1 and TIMx_EDGA0.
TIMx_EDGA1
TIMx_EDGA0
TIMx_CNT = TIMx_CNT + 1
0
0
on no edge.
0
1
on IN_ACC falling edge.
1
0
on IN_ACC rising edge.
1
1
on IN_ACC rising and falling edge.
Table 9.31: Control bit for edge selector.
9.3.6.7.3 Usage and example
Typical usage: Event counting (integrator, frequency measure, etc…)
9.3.6.8 Debouncer mode
9.3.6.8.1 Functional block diagram
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TCNT_x
EN_DIV
CNT_CK
Pre-divider
CK
RST
IN_DEB
Edge selector
(TxEDGB)
16-bit up counter
R/S
Greater or Equal
comparator (TxGE)
TIMx_OUT_GE
Tx_INT1
16
Tx_INT2
Interrupts
block
TIMx_CMPB
control register
TREGB_x
TCTRL_x
TIMx_START
TIMx_DIN1
TIMx_DIN0
unused
INT_EDGF
INT_EDGR
INT_EDG
FREEZE
2
Tx_INT3
Tx_INT4
Tx_INT5
Output Block
Tx_OUT_DEB
Figure 9-28: Debouncer block diagram.
Note: The symbol ‘x’ should be replaced by 1 or 2 depending on the Timer.
The IO port associated to the Compare value TIMx_CMPB is the port TREGB_x.
This mode uses the 16-bits counter as delay counter. The counter clock, CNT_CK, is the CPU clock, CK, divided by
a pre-defined number, TIMx_DIV, being 1, 16 or 256. The counter is incremented on the CNT_CK rising edge.
A pre-defined comparator value, TIMx_CMPB, is loaded in the 16-bits IO port TREGB_x and defines the debounce
delay. The equality comparator output, TIMx_OUT_GE, is set to 1 when the counter reaches this value; and an
R/S block manages the freeze control of the debounced output, Tx_OUT_DEB.
This edge selector is programmed to detect rising and falling edges. By using the two control bits, TIMx_DIN1 and
TIMx_DIN0, the debounce method can be changed. The bits TIMx_DIN select the time at which the falling and/or
rising edge detection are displayed on output INT_EDGF and INT_EDGR (i.e. immediately or delayed by the
debounce delay counter).
So when a rising edge is detected on Tx_OUT_DEB
 An interrupt, Tx_INT4= INT_EDGR, can be generated immediately or after the debounce delay
counter
And when a falling edge is detected on Tx_OUT_DEB
 An interrupt,Tx_INT5 INT_EDGF, can be generated immediately or after the debounce delay counter
If the control bit TIMx_START is low, the Debouncer mode is disabled and outputs INT_EDGR, INT_EDGF and
Tx_OUT_DEB are frozen to 0.
Note: The case where the debounce delay TIMx_CMPB=0000h is to be avoided. If TIMx_CMPB=0000h the
following two cases are defined:
 if TIMx_DIN1 = TIMx_DIN0 = 1, then Tx_OUT_DEB is equal to IN_DEB delayed by one period of CK,
and
 if TIMx_DIN1 = TIMx_DIN0 = 0 then Tx_OUT_DEB is equal to IN_DEB delayed by two periods of CK.
9.3.6.8.2 Output signals
The pre-divider is controlled with bits TIMx_DIV1 and TIMx_DIV0.
REVISION 1.7 – 27. Apr 2020
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Assuming the bit TIMx_START is high, the functionality of the two bits, TIMx_DIN1 and TIMx_DIN0, in the control
port TCTRL_x is described Table 9.32.
The input signal, IN_DEB, is sampled by CK, and when a rising or falling edge is detected the output value,
Tx_OUT_DEB, is freeze to 0 or 1, until the programmed delay is reached.
An interrupt signal is generated each time Tx_OUT_DEB toggle.
Particular case, If the denounce delay is shorter than the bouncing period: The output signal Tx_OUT_DEB will
change according to the bits TIMx_DIN and to the state of the input IN_DEB after the debounce delay counter.
The rules are the same than for the standard case, see Table 9.32.
TIMx_DIN1
TIMx_DIN0
0
0
IN_DEB / Tx_OUT_DEB / INT_EDGR / INT_EDGF
DELAY
DELAY
DELAY
DELAY
DELAY
DELAY
DELAY
DELAY
IN_DEB
Tx_OUT_DEB
INT_EDGR
INT_EDGF
0
1
IN_DEB
Tx_OUT_DEB
INT_EDGR
INT_EDGF
1
0
IN_DEB
Tx_OUT_DEB
INT_EDGR
INT_EDGF
1
1
IN_DEB
Tx_OUT_DEB
INT_EDGR
INT_EDGF
Table 9.32: Debounce method selection.
9.3.6.8.3 Usage and example
Typical usage: Switch debounce
9.3.6.9 PWM mode
9.3.6.9.1 Functional block diagram
REVISION 1.7 – 27. Apr 2020
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Be care that Timer in PWM mode differs from the PWM module itself. The Timer in PWM mode does not include
all the functionalities of a PWM module (no double buffer register) and the IO ports update must follows some
rules. Please read all the sub-paragraphs before any use.
Channel A
TREGA_x
TIMx_CMPA
16
INT_PWMA
Equality comparator
(TxEQ)
OUT_EQ
Tx_INT1
EN_DIV
CK
INT_PWMA
Pre-divider
TIMx_CNT
16
TCNT_x
INT_PWMB
CNT_CK
RST
TIMx_DIN1
TIMx_DIN0
unused
INT_PWMB
unused
OUT_GE
Greater or Equal
comparator (Tx_GE)
TCTRL_x
TIMx_START
Tx_INT4
unused
INT_PWMA
16
16
control register
Tx_INT2
Tx_INT3
Tx_INT5
16-bit up counter
TIMx_CNT
TIMx_OUT_GE
Interrupts
block
TIMx_CMPB
TREGB_x
Channel B
INT_PWMB
OUT_EQ
OUT_GE
TIMx_DIN1,
TIMx_DIN0
Tx_OUT_PWM
Output block
Figure 9-29: 16-bits PWM block diagram.
Note: The symbol ‘x’ should be replaced by 1 or 2 depending on the Timer.
The IO ports associated to the comparator values TIMx_CMPA and TIMx_CMPB are the ports TREGA_x and
TREGB_x.
This mode allows creating a 16 bits high resolution PWM output.
The counter clock, CNT_CK, is the CPU clock, CK, divided by a pre-defined number, TIMx_DIV, being 1, 16 or 256.
The counter is incremented on the PCK rising edge.
Two pre-defined comparator values, TIMx_CMPA and TIMx_CMPB are loaded in the 16-bits IO ports TREGA_x
and TREGB_x. The comparator output signals, OUT_GE and OUT_EQ, associated with the two control bits
TIMx_DIN1 and TIMx_DIN0, control the outputs waveform as described below:
 OUT_GE, is set to 1 if the counter value TIMx_CNT is greater than or equal to TIMx_CMPB.
 OUT_EQ, is set to 1 when the counter value TIMx_CNT is equal to TIMx_CMPA.
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And:

When OUT_GE is high, TIMx_DIN0 is put on Tx_OUT_PWM, and an interrupt is generated on the
output INT_PWMB.
When OUT_EQ is high, TIMx_DIN1 is put on Tx_OUT_PWM and an interrupt is generated on the
output INT_PWMA.

This method allows creating shapes as described in Table 9.33.
The interrupt signals, INT_PWMA and INT_PWMB, are connected to MLX81325 rising-edge sensitive interrupt
inputs.
Warning: The IO ports values TIMx_CMPA and TIMx_CMPB are not buffered: when updated, the new values
have an immediate effect on the output state.
Assuming input EN_DIV input is asserted high, TIMx_CMPB > 0x0000 and TIMx_CMPA < TIMx_CMPB the PWM
output period, TTx_OUT_PWM, and the duty cycle, DCTx_OUT_PWM, are given by the equations:
Equation 19
TTx_OUT_PWM 
TIMx_DIV
 TIMx_CMPB  1
Fck
Equation 20
FTx_OUT_PWM 
1
Fck
1


TTx_OUT_PWM TIMx_ DIV TIMx_CMPB 1
Equation 21


Fck
1
TIMx_CMPB 

 1
 TIMx_ DIV FTx _ OUT _ PWM 
Equation 22
DC Tx_OUT_PWM 
TIMx_ CMPB TIMX_ CMPA
TTx_OUT_PWM
 TIMx_ CMPB TIMx_ CMPA 

Fck
DC Ttx_OUT_PWM  



TIMx_ CMPB 1

  TIMx_ DIV 
Equation 23
Where: Fck is the frequency of the CPU clock, and
TIMx_DIV = 1, 16, or 256.
9.3.6.9.2 Output signals
The functionality of the Timer unit in PWM mode is summarized Table 9.33.
TIMx_START TIMx_DIN Tx_OUT_PWM
NOTES
[1:0]
1
10
TTx_OUT_PWM
TX_OUT_PWM
TIMx_DIN0
Ttx_out_pwm 
TIMx_DIN1
(1)
- (1) Stays high during one period of CK.
INT_PWMA
(1)
(1)
INT_PWMB
0
REVISION 1.7 – 27. Apr 2020
TIMx_DIV
 TIMx_ CMPB  1
Fck
TIMx_CMPA
TIMx_CMPB
- If TIMx_CMPA>TIMx_CMPB,
Tx_OUT_PWM stays at TIMx_DIN0, and
INT_PMWA is never raised.
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TIMx_START TIMx_DIN Tx_OUT_PWM
[1:0]
NOTES
- If TIMx_CMPB=0000h, INT_PWMB is
never raised.
1
01
- (1) Stays high during one period of CK.
TTx_OUT_PWM
TX_OUT_PWM
TIMx_DIN0
TIMx_DIN1
(1)
INT_PWMA
(1)
(1)
INT_PWMB
0
TIMx_CMPA
- If TIMx_CMPA>TIMx_CMPB,
Tx_OUT_PWM stays at TIMx_DIN0, and
INT_PMWA is never raised.
TIMx_CMPB
- If TIMx_CMPB=0000h, INT_PWMB is
never raised.
1
11
- (1) Stays high during one period of CK.
TTx_OUT_PWM
stay endlessly to '1'
Tx_OUT_PWM
TIMx_DIN0
TIMx_DIN1
(1)
INT_PWMA
(1)
(1)
INT_PWMB
0
1
TIMx_CMPA
TIMx_CMPB
- If TIMx_CMPB=0000h, INT_PWMB is
never raised.
00
- (1) Stays high during one period of CK.
TTX_OUT_PWM
Tx_OUT_PWM
TIMx_DIN0
(1)
TIMx_DIN1
stay endlessly to '0'
INT_PWMA
(1)
(1)
INT_PWMB
0
0
--
Tx_OUT_PWM
TIMx_CMPA
TIMx_CMPB
stay endlessly to D0
INT_PWMA
stay endlessly to '0'
INT_PWMB
stay endlessly to '0'
0
- If TIMx_CMPA>TIMx_CMPB,
Tx_OUT_PWM stays at TIMx_DIN0, and
INT_PMWA is never raised.
TIMx_CMPA
- If TIMx_CMPA>TIMx_CMPB,
Tx_OUT_PWM stays at TIMx_DIN0, and
INT_PMWA is never raised.
- If TIMx_CMPB=0000h, INT_PWMB is
never raised.
- PWM mode disabled
- 16-bits counter reset to 0000h.
TIMx_CMPB
Table 9.33: PWM output signal.
9.3.6.9.3 Usage and example
Generating a PWM signal at 10 kHz and 25 % duty cycle with a 16 MHz oscillator (1/Tck).
With a pre-divider TIMx_DIV = 1,
And so IO port value TIMx_CMPB is set to
The duty cycle is defined by equation
So IO port TIMx_CMPA is set with
REVISION 1.7 – 27. Apr 2020
TTx_OUT_PWM = 16E6 / 10E3 = 1600
TIMx_CMPB = 1600 - 1 = 159910 = 063F8
DCTx_OUT_PWM = (TIMx_CMPB – TIMx_CMPA) / TTx_OUT_PWM = 0.25
TIMx_CMPA = 159910 - (160010 x 0.25) = 119910 = 04AF8
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TIMx_CMPA
Tx_OUT_PWM
TIMx_CMPB
0
TTx_OUT_PWM
OSC
Tosc
Time
Figure 9-30: Example of PWM signals.
9.3.6.10
Timers IO ports
The update of the IO ports must be done when the control bit TIMx_START is low.
All the IO ports involved in a single timer module (TIMER_x) programming are resumed in Table 9.34 to Table
9.37:
The Data ports TREGA_x and TREGB_x,
 The Control port TCTRL_x, and
 The Counter port TCNT_x.
According to the selected Timer mode –see previous paragraphs-, the data saved in the port
 TREGA_x is refered as the compare value TIMx_CMPA, or as the capture value TIMx_CAPA.
 TREGB_x is refered as the compare value TIMx_CMPB, or as the capture value TIMx_CAPB.
IO port: TREGA_x
Bit[7]
Access mode: Word – Read and Write
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
TIMA_REGA[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
TIMA_REGA[15:8]
Table 9.34: Timer_x ports – data port for channel A.
TIMx_REGA[15:0]:
Data for the channel A of Timer A; only accessible in Word
IO port: TREGB_x
Bit[7]
Access mode: Word– Read and Write
Bit[6]
Bit[5]
Bit[4]
Bit[3]
TIMx_REGB[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
TIMx_REGB[15:8]
Table 9.35: Timer_x ports – data port for channel B.
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TIMx_REGB[15:0]:
Data for the channel B of Timer_x; only accessible in Word
IO port: TCTRL_x
Access mode: Word, Byte, Bit – Read and Write
Bit[7]
Bit[6]
TIMx_DIN[1:0]
Bit[15]
Bit[5]
Bit[4]
TIMx_EDG2[1:0]
Bit[14]
TIMx_DIV[1:0]
Bit[13]
Bit[12]
TIMx_MODE[2:0]
Bit[3]
Bit[2]
TIMx_EDG1[1:0]
Bit[11]
Bit[10]
Bit[1]
Bit[0]
TIMx_START
TIMx_EBLK
Bit[9]
Bit[8]
TIMx_ENCMP TIMx_OVRB
TIMx_OVRA
Table 9.36: Timer_x ports – control port.
TIMx_DIV[1:0]:
Predivider ratio between CPU clock and Timer counter clock. This selector is use in all Timer
modes except in the Pulse accumulator mode.
00 = div by 1 01 = div by 16 1- = div by 256
TIMx_MODE[2:0]:
Mode selector.
000 = Timer mode
100 = Pulse accumulator mode
001 = Dual timer compare
101 = Debouncer mode
010 = Dual timer capture
110 = PWM mode
011 = Timer capture/compare 111 = reserved
TIMx_ENCMP:
Enable comparison to reset timer value. This enable bit is use in Dual timer compare /
capture modes only.
0 = counter is reset when ‘FFFFh’ is reached
1 = counter reset when the value TIMx_REGB is reached
TIMx_OVRB:
Overrun flag for the channel B; indicates to consecutive capture action on channel B,
without CPU reading operation between. This flag is use in Dual timer capture or in
capture/compare mode.
0 = a capture action set TIMx_REGB with current counter value.
1 = all future capture action masked until reading capture value
TIMx_OVRA:
Overrun flag for the channel A. Indicates to consecutive capture action on channel A,
without CPU reading operation between. This flag is use in Dual timer capture mode.
0 = a capture action set TIMx_REGA with current counter value.
1 = all future capture action masked until reading capture value
TIMx_DIN[1:0]:
Control bit to fix the debounce method or the output waveform. This selector is use in
Debounce and PWM.
TIMx_EDG2[1:0]:
Edge selector for channel B, to generate a capture event ; This selector is use in Dual
capture and capture/compare mode.
00 = no capture event
11 = capture event on rising and falling edge
01 = capture event on falling edge
10 = capture event on rising edge
TIMx_EDG1[1:0]:
Edge selector for channel A, to generate a capture event; This selector is use in Dual
capture and Pulse accumulator mode.
00 = no capture event
11 = capture event on rising and falling edge
01 = capture event on falling edge
10 = capture event on rising edge
TIMx_START:
Enable bit for the selected mode.
1 = mode enabled; Timer is working in the selected mode.
forced to 0
REVISION 1.7 – 27. Apr 2020
0 = mode disabled; output
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TIMx_EBLK:
Enable Timer block
1 = Timer module enable
IO port: TCNT_x
Bit[7]
0 = Timer module disabled
Access mode: Word – Read only
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
TIMx_CNT[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
TIMx_CNT[15:8]
Table 9.37: Timer_x ports – counter value.
TIMx_CNT[15:0]:
Current counter value of Timer_x; only accessible in Word and Read.
9.3.6.11
Interrupt connections
The following table summarises the possible interrupt sources of one timer module in the different modes of
operation.
Mode
Interrupt name
/ output
Interrupt description
Timer
INT_TIMER
/ Tx_INT4 Greater than or equality compartor. (TIMx_CNT > TIMx_REGB)
Dual
Compare
INT_CMPA
/ Tx_INT2
Equality comparator. (TIMx_CNT = TIMx_REGA)
INT_CMPB
/ Tx_INT4
Greater than or equal (TIMx_CNT > TIMx_REGB). Reset
TIMx_CNT if contol bit TIMx_ENCMP is high.
Dual
Capture
INT_CAPA
/ Tx_INT1 Capture signal for channel A. Active edge programmed with the
control bit TIMx_EDG1.
INT_CAPB
/ Tx_NT5 Capture signal for channel B. Active edge programmed with the
control bit TIMx_EDG2.
INT_OVRA
/ Tx_INT2
Overrun on Channel A. Previous interrupt INT_CAPA not
executed.
INT_OVRB
/ Tx_INT4
Overrun on Channel B. Previous interrupt INT_CAPB not
executed.
INT_OVF
/ Tx_INT3
Counter overflow. (TIMx_CNT > FFFFh)
INT_CMPA
/ Tx_INT2
Equality comparator. (TIMx_CNT = TIMx_REGA)
INT_OVF
/ Tx_INT3
Counter overflow. (TIMx_CNT > FFFFh)
INT_OVRB
/ Tx_INT4
Overrun on Channel B. Previous interrupt INT_CAPB not
executed.
INT_CAPB
/ Tx_NT5
Capture signal for channel B. Active edge programmed with
TIMx_EDG2.
Pulse
Accumulator
INT_OVF
/ Tx_INT3
Counter overflow. (TIMx_CNT > FFFFh)
Debouncer
INT_EDGF
/ Tx_INT4
Falling edge detected on Tx_OUT_DEB
INT_EDGR
/ Tx_INT5
Rising edge detected on Tx_OUT_DEB
INT_PWMA
/ Tx_INT2
Indicates when Tx_OUT_PWM is set to TIMx_DIN1.
Capture
Compare
PWM
REVISION 1.7 – 27. Apr 2020
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Mode
Interrupt name
INT_PWMB
/ output
Interrupt description
/ Tx_INT4
Indicates when Tx_OUT_PWM is set to TIMx_DIN0.
Table 9.38: Interrupts functions.
The Timer interrupts are connected into MULAN3 external interrupts block.
9.3.7 SPI Interface
9.3.7.1 Features
The MLX81325 comprises one Serial Peripheral Interface block, SPI, with the following characteristics:
 supports word or byte transmission/reception
 full-duplex operation
 double-buffered architecture for queued transmission and continuous reception
 master and slave mode
 programmable baudrate up to 4MBit/s possible (depending on PLL frequency)
 wide range of programmability
 SPI receiver and transmitter interrupt sources
The SPI can work in one of the following main modes:
 Master mode, or
 Slave mode
9.3.7.2 Applications
The Serial Peripheral Interface block is used in association with the MLX16. The following parameters of the
device are programmable by software:
 Enable or disable module.
 Master or Slave mode of the module.
 Period of synchro signal (in Master mode).
 Polarity of synchro signal (in Master and Slave mode).
 Phase shift of synchro signal (in Master and Slave mode).
 Word or Byte mode (in Master and Slave mode).
 Master Transmit Only (in Master mode).
 Interrupts masks (enable or disable Interrupts) and etc.
According to the selected mode, the block manages different signals:
 In Master mode: the SPI generates a synchro signal to Slave(s).
 In Slave mode: the SPI is synchronized to the Master’s SPI synchro signal. An IO port, the Baud Rate,
is used to program the period of the Master’s synchro signal.
9.3.7.3 Block diagram and description
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CPU bus
12
16
16
SPI_RR
Transmit
Register
(SPTR)
SPI_TR
16
BAUD CLOCK
SPI_EN
SPI_MSTR
SPI_CPOL
SPI_CPHA
SPI_BYTEMOD
SPI_MSTRONLY
Shift Register
(SPSHR)
SPI_SR
16
Receive
Register
(SPRR)
SHIFT_OUT
Baud Rate
Generator
(SPBG)
SHIFT_IN
CK
RB
SHIFT
1 / Tosc
SPI_TF
Clock
Logic
(SPCL)
SPI_RF
SPI_OVRF
SPI_MODF
SPI_TI
Interrupt Unit
(SPIU)
SPI_RI
SPI_ERRIE
SPI_RI_IE
SPI_TI_IE
MASTER
SLAVE
SPISIB
INOUT
LOGIC
(SPIO)
1 / Tosc
MISO
MOSI
SPSCK
SSOB
SPI_MODFEN
Figure 9-31: Functional diagram of the SPI block
The SPI module allows full-duplex, synchronous, serial communication between the MLX81325 and external
devices. The Software can poll the SPI status flags and drive the SPI operations using specific interrupts signals.
According to the control bits SPI_MSTR and SPI_MSTRONLY, The SPI can operates in Master and/or in Slave
mode. In master mode the input pin SPISIB of the SPI master must be asserted low.
The SPI uses the outputs MOSI (Master-Out-Slave-In) and MISO (Master-In-Slave-Out) for transferring data from
Master to Slave or otherwise. The full duplex, double buffered architecture allows data streams to be transferred
the same time in both directions.
The SPI is designed with a system Clock enable. This enable function is done by the SPI control bit SPI_EN.
A double-buffered Transmit Data register allows a data byte/word to be queued and transmitted. For an SPI
configured as a master, a queued data byte/word is transmitted immediately after the previous transmission has
completed. The receiver-full SPI_RF and transmitter-full SPI_TF flags handle the transfer
from the Transit Data register into the Shifter, and
from the Shifter into the Receive Data register.
The IO port associated to the Baud Rate Generator block SPBG is the port SBRR.
The IO port associated to the Transmit block SPTR and the Receive block SPRR is the port SPDR.
The SPI Baud Rate port SBRR is used to initialize the SPI transmission frequency, Fspck. FSPCk is given by the
following equation:
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Fspck 
Equation 24
Where:
FCK
SPI_BRR10
Fck
SPI _ BRR10  1
: SPI input frequency; equal to the PLL clock or the oscillator clock OSC.
: Programmed Baud Rate. Value of the SPI baud rate port SBRR and converted in decimal base.
Master IC
Slave IC
SPI
IO[0]
MOSI
MISO_IN
IO[1]
MISO
SPSCK_OUT
IO[2]
SPSCK
IO[2]
IO[3]
SS
IO[3]
MOSI_OUT
Shift Register
Baud Rate
Generator
SPI
SSOB
IO[0]
IO[1]
MOSI_IN
Shift Register
MISO_OUT
SPSCK_IN
SSIB
Figure 9-32: Full-Duplex Master-Slave connections scheme.
9.3.7.4 Notes about IO ports usage
To enable the SPI module it is necessary to
 set the bit SPI_CKEN to 1, then
 set the other control bits to the desired value: SPI_BYTEMOD, SPI_MSTRONLY, SPI_CPOL, SPI_CPHA,
SPI_MSTR, then
 Set the SPI module enable bit SPI_EN to 1
After this sequence, the first word/byte data can be written in the SPI Data port, SPDR.
To disable the SPI module the bit SPI_CKEN should be set to 0 after the SPI module enable bit SPI_EN.
A transmission starts:
On the first edge of SPSCK, if the clock phase bit, SPI_CPHA, is set to 1
On the falling edge of SSIB, if SPI_CPHA is set to 0.
The modification of the Baud Rate code, CODESPI_BRR, must be effected only when SPI is disabled, i.e. SPI_EN=0.


The baud rate only controls the speed to the SPSCK generated by an SPI configured as a master.
In case the CODESPI_BRR is less than 3, the value for baud rate generator will be 3, because the
minimum SPI baud rate frequency must be a MULAN3 frequency divided by 4 for the realization of
an edge detection mechanism.
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
In case the CODESPI_BRR is an even number (so system frequency division factor is odd), the duration
of the high level of SPSCK signal will be longer than the duration of then low level by one.
To prevent SPSCK from appearing as a clock edge, SPSCK must be in the proper idle state before the slave mode
is enabled.
IMPORTANT:
The master SPI must always be enabled before the slaves SPI. And the slave SPI must always be disabled before
the master SPI.
9.3.7.5 Master mode
The SPI operates in master mode when the SPI master bit SPI_MSTR is set to 1 (see IO port SPSCR).
In master mode the SSIB pin of this SPI master must be asserted low.
Only a master SPI module can initiate transmissions.
Software begins the transmission from a master SPI module by writing to the IO port SPDR:
 The SPI transmitter full bit SPI_TF is automatically set to 1, and
 The SSOB output signal becomes low during each Master’s transmission and is high when the Master
SPI is in the idling state.
If the Shift Register is empty, the transmissible data immediately transfers to the shift register, resetting the SPI
transmitter full bit SPI_TF. The data begins shifting out on the MOSI pin under the control of the serial clock.
The transmission ends when the Receiver Full Flag, then bit SPI_RF signals the end of the transmission:
 Bit SPI_RF is set to 1,and
 the byte/word from the slave are transferred to the Receive Data port, SPDR.
The bit SPI_RF is cleared automatically when software reads SPDR.
The IO port SBRR controls the baud rate generator and:
 determines the speed of the shift register.
 controls the Shift Register of the slave device through the pin SPSCK
As the transmissible data shifts out on the MOSI pin of the master, another data shifts in from the slave on the
master's MISO pin.
Interrupts allow detecting and preventing errors during the transmission sequence
SPI_TI indicates the beginning of a transmission. It is generated when:
If the interrupt enable bit SPI_TFIE is high, by a falling edge on the transmit full flag bit SPI_TF
9.3.7.6 Slave mode
The SPI operates in slave mode when bit SPI_MSTR is set to 0 (see IO port SPSCR).
In slave mode, the pin SPSCK is the input for the serial clock from the master MCU.
Before a data transmission occurs, and assuming the module is enabled:
 the input pin SSIB of the slave must be set to 0 by the master, and
 SSIB must remain low until the transmission is complete. See error bit SPI_MODF.
In case Slave SPI will transmit data to Master SPI, this data must be written into port SPDR before the SPI module
is configured as slave, i.e. in master configuration.
In a slave SPI module:
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The data inputs and outputs the Shift Register under the control of the serial clock from the master SPI module.
Then after a byte/word enters the Shift Register of a slave SPI it is transferred to the Receive Data Register,
And the bit SPI_RF is set. To prevent an overflow condition, slave software must read the SPI Data port before
another byte/word enters the shift register.
When the master SPI starts a transmission,
The data in the slave Shift Register begins shifting out on the MISO pin.
The slave can load its Shift Register with a new byte/word for the next transmission by writing to its Transmit
Data Register. The slave must write to its Transmit Data Register at least one bus cycle before the master starts
the next transmission (flag SPI_TF is set to1).
The flag bit SPI_MODF is set to 1 if the input pin SSIB goes high during a transmission.
Note: If the writing to the Data port is late, the SPI already transmits the data into the Shift Register from the
previous transmission.
Interrupts allow detecting and preventing errors during the receive sequence
SPI_RI indicates the end of the transmission. It is generated when:
 If the interrupt enable bit SPI_RFIE is high, by a rising edge on the receive full Flag SPI_RF,
 if the error interrupt enable bits SPI_ERRIE and SPI_MODFEN are high, by a rising edge on the mode
fault bit SPI_MODF,
 if the error interrupt enable bits SPI_ERRIE is high, by a rising edge on SPI_OVRF
The Figure 9-33 Full duplex transfer with default setting (default clock polarity and word transmission) illustrates
the data waveforms during a typical transfer. This example assumes that SPI_CPHA = 1, SPI_CPOL = 0, and
SPI_FRSSOEN=1.
...
SPSCK
Master’s MOSI_OUT
Slave’s MOSI_IN
Master’s MISO_IN
Slave’s MISO_OUT
MSB
BIT14
BIT13
...
BIT3
BIT2
BIT1
LSB
MSB
BIT14
BIT13
...
BIT3
BIT2
BIT1
LSB
SSOB to Slave
...
Capture Strobe
Figure 9-33 Full duplex transfer with default setting (default clock polarity and word transmission)
9.3.7.7 SPI IO ports
All the IO ports involved in SPI programming are defined in the following tables:
 The Baud Rate port SBRR,
 The Status and Control ports SPSCR_L, and SPSCR_H
 The Data port SPDR.
 The IO ports involved in SPI interrupts are defined in Table 9.43
 The reset state and reset command of the SPI ports are defined in Table 9.44
9.3.7.7.1 Control and command ports
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IO port: SBRR Address: 0x289Ch
Bit[7]
Bit[6]
Access mode: Word, Byte – Read and Write
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
SPI_BRR[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
-
-
-
-
Bit[11]
SPI_BRR[11:8]
Table 9.39: SPI- Control and command ports
SPI_BRR[15:0]:
Baud Rate value. The SPI input cock frequency divided by
‘SPI_BRR[15:0]+1’
Some bits of the status and control port SPSCR are detailed hereafter:
 The SPI transmitter full flag, SPI_TF, indicates when the transmit data buffer is ready to accept new
data. Write to the SPI Data port only when the SPI_TF bit is low.
 SPI work mode is depending on the bit SPI_BYTEMOD:
 If SPI_BYTEMOD is set to 1, i.e. byte transceiving mode selected
 When the firmware writes word into IO port SPDR, a transmission starts (8 bits data).
 When the firmware writes byte into SPI_DR[7:0], a transmission starts, a transmit
starts (8 bits data).
 When the firmware writes byte into SPI_DR[15:0], it is a wrong access type, so no
transmission will start.
 If SPI_BYTEMOD is set to 0, i.e. word transceiving mode selected
 When the firmware writes word into IO port SPDR, a transmit starts
 When the firmware writes byte into SPI_DR[7:0], the CPU data will be saved in
SPI_DR[7:0], and a transmission starts (16 bits data).
 When the firmware writes byte into SPI_DR[15:8], the CPU data will be saved in
SPI_DR[7:0], and a transmission starts (16 bits data).
 About SPI_MODF and SPI_MODFEN bits:
 MODF does not occur since a transmission was never begun.
 MODF flag does not clear the SPE bit or reset the SPI in any way
 SPI_MODF flag can be set to 1 only if bit SPI_MODFEN bas been previously set to 1.
 SPI_MODF flag is set to 0 if SPI_MODFEN bit is set to 0.
 A raising edge on SPI_MODF generates a receiver/error CPU interrupt request SPI_RI.
 The SPI_RF, SPI_MODF, and SPI_OVRF interrupts share the same CPU interrupt vector.
 SPI_MODF and SPI_OVRF can generate a receiver/error CPU interrupt request.
 The interrupt enable bit SPI_ERRIE controls the interrupt source SPI_MODF and SPI_OVRF
 It is not possible to enable only SPI_MODF and SPI_OVRF, but if SPI_MODFEN is low, the bit
SPI_MODF is asserted low.
 The Software can abort the SPI transmission by toggling the enable bit SPI_EN bit of the slave.
IO port: SPSCR_L (low byte of IO port SPSCR)
Address: 0x289Ah
Access mode: Word, Byte, Bit – Read and Write
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
SPI_RFIE
SPI_TFIE
SPI_BYTEMOD
SPI_MSTR
SPI_CPOL
SPI_CPHA
SPI_EN
SPI_CKEN
Table 9.40: SPI ports – Status and Control bits 1
SPI_RFIE:
Enable bit for the interrupt request SPI_RF.
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SPI_RF is a source of interrupt for SPI_RI.
1 = SPI_RF interrupt enabled
0 = SPI_RF interrupt disabled
SPI_TFIE:
Enable bit for the interrupt rrequest SPI_TF.
SPI_TF is the source of interrupt for SPI_TI.
1 = SPI_TF interrupt enabled
0 = SPI_TF interrupt disabled
SPI_BYTEMOD:
Frame length selector.
1 = receive/transmit an 8 bits frame
SPI_MSTR:
Master bit mode.
1= Master mode selected
0 = receive/transmit an 16 bits frame
0 = Slave mode selected
SPI_CPOL:
Clock polarity selector. Logic state of SPI clock output.
1 = SPSCK _OUT is high during transmission
0 = SPSCK _OUT is low during transmission
SPI_CPHA:
Clock phase selector; defines the timing relationship between output clock
and output data
0 = transmission starts on falling edge of SPISIB
1 = transmission starts on first SPSCK edge
SPI_EN:
Enable SPI module.
1 = SPI module enabled
SPI_CKEN:
0 = SPI module disabled
Enable bit for SPI clock.
1 = SPI clock in normal mode
IO port: SPSCR_H (high byte of IO port SPSCR) (0x289Bh)
Bit[15]
Bit[14]
Bit[13]
Bit[12]
SPI_RF
SPI_TF
SPI_OVRF
SPI_MODF
0 = SPI clock froze.
Access mode: Word, Byte, Bit – Read and Write
Bit[11]
Bit[10]
Bit[9]
SPI_FRSSON SPI_MODFEN SPI_MSTRONLY
Bit[8]
SPI_ERRIE
Table 9.41: SPI ports – Status and Control bits 2
SPI_RF:
SPI_TF:
Receiver Full.
1 = Receive port SPI_DR is full
0 = Receive port SPIR_DR is empty
Transmit Full.
1 = Transmit port SPI_DR is full
0 = Transmit port SPIR_DR is empty
SPI_OVRF:
Overflow flag. SPI_OVRF is a source of interrupt for SPI_RI.
1 = Receive port full, receive data are lost
0 = data are read before next transmission
SPI_MODF:
Mode Fault bit; used in master mode only to detect the status of
input SPISIB during a transmission.
1 = SPISIB switch high during transmission
0 = SPISIB stays at low level
SPI_FRSSOEN:
Frame Slave Select Output Enable Bit; used in Master mode only to drive
SSOB signal is drives to the active state (to low) every time when frame is being
transmitted or when Master is selected and enabled.
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1 = SSOB low when frame is being transmitted
0 = SSOB low when Master is configured and enabled
SPI_MODFEN:
Mode Fault enable bit.
Should be combined with SPI_ERRIE to enable interrupt on SPI_MODF.
1 = SPI_MODF update enabled
0 = SPI_MODF forced to 0
SPI_MSTRONLY:
Master transmit mode; only valid in master mode.
1 = Transmit mode selected
0 = Full-duplex mode selected
SPI_ERRIE:
Error Interrupt Enable Bit.
1 = SPI_MODF and SPI_OVRF interrupt enabled 0 = Interrupt disabled
To enable the SPI_MODF interrupt, bit should be combined with SPI_MODFEN.
The SPI Data port, SPDR, is the read/write buffer for the Receive Data register, SPRR, and the Transmit Data
register, SPTR. SPRR and SPTR registers are separate buffers that can contain different values.
Writing to SPDR writes data into the Transmit Data register SPTR.
Reading SPDR reads data from the Receive Data register SPRR.
IO port: SPDR Address: 0x289Eh
Bit[7]
Bit[6]
Access mode: Word, Byte – Read and Write
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[10]
Bit[9]
Bit[8]
SPI_DR[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
SPI_DR[15:8]
Table 9.42: SPI ports – Data values
SPI_DR[15:0]:
SPI Data port.
9.3.7.7.2 Interrupts connections
To manage the SPI interrupts, the MULAN3 includes IO ports named XI3MASK, PRIO, and XI3PEND.
XI3MASK is the interrupt enable port. This IO port is defined at address 0x2030. Each interrupt can be disabled or
enable independently;
PRIO is the priority port. This IO port is defined at address 0x2004. The priority bits defined the software priority
of the interrupt source.
The software priority of each interrupt can be programmed between 3 and 6.
The hardware priority is not modifiable and fixed as follow: SPI_RI is the more priority interrupts, and SPI_TI is
the less priority interrupts.
XI3PEND is the pending interrupt port. This IO port is defined at 0x203A. This bit is set to 1 by the interrupt
source.
The pending bit is cleared automatically by the interrupt controller when the corresponding interrupt is served.
The software can also clear the pending bit at any time by writing in the pending interrupt IO port.
Name
Address
Priority
Notes
SPI_RI
XI3MASK[15]
XI3PEND[15]
3-6
Receive
interrupt
SPI_TI
XI3MASK[14]
XI3PEND[14]
3-6
Transmit
interrupt
Table 9.43: SPI interrupts - addresses and priority table
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Reset state
During a Power On Reset the SPI input RB is asserted low.
After a Power On Reset the SPI module is disabled and the IO ports are reset as resumed in Table 9.44.
By default the Watchdog reset interrupt does the same initialization that a Power On Reset interrupt.
IO ports
Name
Reset
commands
Reset
values
SBRR
POR
0x0000
SPSCR_L
POR
0x00
SPSCR_H
POR
0x00
SPI_RF is a reset after read SPDR.
SPI_TF is a reset when data
transferred into shifter.
SPI_OVRF is a Read and Clear bit.
SPI_MODF is reset,
if MLX_MODFEN=0.
SPDR
POR
0x0000
Not reset; value needs to be set before
using SPI.
PEND
POR
0x0000
PRIO
POR
0x0000
MASK
POR
0x0000
Address
Notes
Table 9.44: Reset table for SPI module
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9.4 Analogue- and Mixed Signal Part
All ports and their function are described in detail in the ports map description. Below a few blocks are described
more in detail, in case one or more functions are not seen clearly in the ports map.
9.4.1 Oscillator concept
ADC
ADC_CLK
1-4MHz
Clock unit
ADCFREQ[15:14]
F1MHz_Reset
1MHz
EXT_CE_SELB
DIVIDER






PLL_FBDIV[7:0]
CKTRIM
F1MHz
DIVIDER
simple 15bit timer
MULAN2 internal
FLASH
NVRAM
Digital WD
Timer
CKTRIM[5:0]
Force Fallback to SLOWCLK;
signal a CM error
CTLCK[3:0]
PLL_EN
TR_PLL[7:0]
1MHz
TR_RCO[6:0]
div 4
feedback divider
PLL_LOCKED
FASTCLK
SLOWCLK
RC-OSC
PLL_CM
Lock Detect
Clock Monitor
PLL Analog
to EXT4 interrupt
ANA_INA[12]
System
Clock
Selector
System clock




CPU
Timer
PWM
SPI
PLL_FBDIV[7:0]
SLOWCLK
Figure 9-34 – Oscillators and clock concept
The digital part of MLX81325 can be supplied by a low speed, RC oscillator clock, or a high speed clock generated
by a phase locked loop frequency multiplier (PLL).
The RC oscillator clock is referred further as SLOWCLK, the PLL clock as FASTCLK.
After power on or watchdog reset the chip always starts at the SLOWCLK as system clock.
The selection of the system clock is fully controlled by application software, it will activate the FASTCLK and
determine it’s source (RC or crystal oscillator) and the frequency (by PLL configuration).
The normal working clock has to be the FASTCLK; if there is writing to an NV memory (Flash, NVRAM) planned,
the FASTCLK has to be selected before; otherwise the writing takes much longer times and this can have
influence to the reliability/data retention/endurance of the NV Memory.
The clock system initialization
runs in principle as follows:
 transfer trimming values for RC oscillator and PLL
 configure PLL frequency
 activate PLL
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9.4.1.1 RC-Oscillator
The main oscillator is a 1 MHz RC oscillator which is trimmed via software according to the ports map description
and NVRAM allocation table.
After Reset the RC oscillator is calibrated with the default reset value 7’b0000000 of the TRIMRC port which will
results in the lowest frequency.
In the Melexis test program the RC oscillator will be calibrated to 1 MHz +/-5%. The final calibration value will be
stored in the NV memory. The initial software routine transfers this value into the TRIMRC port after start up.
The RC oscillator starts with power on at VDDA.
The RC oscillator is switched off in SLEEP MODE
9.4.1.2 Phase locked loop (PLL) configuration
The high frequency internal clock is generated by a phase locked loop (PLL) clock multiplier circuit.
The PLL can be activated by the MULAN3 CPU, after the power-up sequence.
The hardware itself takes care that the PLL has locked and therefore reached its final stable frequency before
enabling its use.
Trimming values for the PLL are written through the port PLLTRIM, software transfers the value similarly to the
RC Oscillator trim-values during system initialization.
The IO port associated to the Feedback Divider value (FBDIV) is PLLDIV.
The IO port associated to the control and status bits is the port PLLCTRL.
The frequency of the high speed clock results from multiplication of FBDIV with the RC oscillator frequency:
FRC _ OSC
 INT FBDIV / 2  1 * 2
4
Where FCK is the PLL output clock frequency and (FRC_OSC/4) is the PLL input clock frequency.
FCK 
Equation 25
The PLL will operate in a output frequency range of nominal 28MHz. FBDIV values resulting in lower or higher
frequency will prevent the PLL from locking, the system clock will remain on SLOWCLK.
Notice that the IO ports PLLCTRL and PLLDIV are writable in MULAN3 protected mode only and when running at
low speed.
The following sequence is recommended to run the system from PLL clock:
 transfer RC trimming into RCTRIM port
 transfer PLL trimming to PLLTRIM port
 define the PLL output frequency by writing FBDIV
 set bit PLLEN to start the PLL
 hardware will switch system to PLL clock after PLL has locked, clock monitor will be started
 the system now runs at FASTCLK
9.4.1.3
Lock detection and clock monitor
The lock detection unit of PLL circuitry has 2 tasks:
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It observes the phase shift of divided PLL clock in relation to input clock coming from RC oscillator. It adds a delay
time (a digital filter constant) before allowing to use the PLL clock output as system clock, assuming the PLL will
enter a stable operating point before. Both filters are realized by configurable debouncing units:
SLOWCLK
to analog PLL
FASTCLK
divided by FBDIV
from analog PLL
UNLOCK
SLOWCLK
PLL_CTLCK[1:0]
UNLOCK
FASTCLK
PLL_EN
LOCK Detect
VDD
D
CK
Debounce max 32
SLOWCLK
RB
D
CK
Debounce max 10
RB
PLL_CTLCK[3:2]
CTLCK[1:0]
SELECTOR
SELECTOR
PLL_LOCKED
check phase shift
observe locking stability
Figure 9-35 – LOCK detection principle – 2 stage debounce
The PLL locks after following conditions are fulfilled:
Condition 1)
The phase shift between the oscillator clock (SLOWCLK) and the PLL clock (FASTCLK) divided by the PLL factor
(FBDIV) must be less than Tphase = 4...32 consecutive periods of the fast PLL clock.
The time Tphase is configured by bit PLL_CTLCK[3:2].
Condition 2)
Condition 1 must be valid for Tsample = 4..10 consecutive periods of 1MHz oscillator clock.
The time Tsample is configured by bit PLL_CTLCK[1:0].
The value for Tsample changes after having locked. Reason for that is to keep the same level of severity.
Possible Configurations:
Control bits
PLL_CTLCK[3:2]
Periods of FASTCLK
Remark
11
10
01
00
32
16
4
8
most relaxed setting for frequency and phase shift
medium setting
most strict setting for freq. and phase shift
default setting after reset
Table 45 – PLL Configurations part I
PLL_CTLCK[1:0]
11
10
01
00
Periods of SLOWCLK for
achieving LOCK
10
8
4
6
Periods of SLOWCLK for
loosing LOCK
4
4
8
6
Remark
most strict setting for frequency stability
medium setting
most relaxed setting
default after reset
Table 46 – PLL Configurations part II
After reset Tphase= 8 periods of FASTCLK and TSample= 6 periods of SLOWCLK are configured.
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9.4.1.4 Clock Monitor
When the PLL is activated, the FASTCLOCK is observed by the clock monitor. This unit ensures, that the system
clock does not stuck e.g. by loss of external resonators connection or does not fail in case of too high frequency
by external distortion etc.
The clock monitor is started after the PLL had been locked successfully.
In case of error the clock monitor will switch back the system to low clock by resetting the PLLEN bit, set the CM
bit and issue the PLL interrupt. All other PLL ports keep their state.
The sensitivity of the PLL locking and the clock monitor can be controlled by bits CTLCK[7:0] in the PLL control
port.
9.4.1.5 1MHz and ADC Clock generation
The clock system provides a 1MHz clock only depending on the system clock fCK (assumed to be the fast PLL clock)
, which is used in several blocks where a constant frequency is needed. Examples are the ADC(9.4.5), the CPU
integrated 15bit timer (9.3.1.7) and watchdog (9.3.1.8) or the NVRAM interface.
After Reset this clock is created automatically from the PLL timing using the FBDIV value from port PLLCTRL.
The reset frequency f1MHz_Reset can be calculated by the formula
fCK
4 * ( FBDIV  4)
The frequency deviation compared to the target frequency of 1MHz is up to +20% depending on the PLL
feedback divider setting.
For higher accuracy, a separate divider can be activated by setting the bit EXT_CE_SELB from port ANA_OUTC
(bit15, refer to chapter 9.4.5).
The divider is controlled by the port CKTRIM[5:0] and divides the system clock (fCK) by the value of (64-CKTRIM).
Equation 26
f1MHz_Reset 
Equation 27
f1MHz 
fCK
64 - CKTRIM
The boot loader software delivered by Melexis already contains the activation and trimming of the 1MHz clock.
The ADC clock frequency is controlled by the ADC_FREQ[1:0] bits (ANA_OUTE[15:14]) to be between 1MHz and 4
MHz. The frequencies are not exact, they are calculated following the formulas given in Table 9.47
ADC_FREQ[1:0]
EXT_CE_SELB
ADC frequency / MHz
exact calculation formula
00
0
1 ( from PLL)
00
1
1 ( from CKTRIM )
01
dont care
2
f1MHz=fCK / (2* (FBDIV >> 4) )
10
dont care
3
f1MHz=fCK / ( ((3*FBDIV) >>5 ) -1 )
11
dont care
4
f1MHz=fCK / (FBDIV >> 4)
f1MHz=fCK / (4* (FBDIV >> 4) )
f1MHz=fCK / (64 - CKTRIM)
Table 9.47: ADC frequency calculation
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Firmware provided by Melexis will pre-select the 1 MHz clock derived from CKTRIM port.
9.4.1.6 Clock system ports
IO port: PLLSTAT Address: 0x2040h
Access mode: Word – Read
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
-
-
-
-
-
-
CM
LOCKED
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
-
-
-
-
-
-
-
-
Table 9.48: PLL status bits
LOCKED
read only status bit : PLL has locked, the system clock is at high frequency when LOCKED=1
CM
read only status bit : clock monitor error bit
bits [15:2]
unused
IO port: PLLTRIM Address: 0x201Ch
Bit[7]
Bit[6]
Bit[5]
Access mode: Word – Read and Write
Bit[4]
TRIMRC6
Bit[3]
Bit[2]
Bit[1]
...
Bit[15]
Bit[14]
Bit[13]
-
-
PLLTRIM5
Bit[12]
Bit[11]
Bit[0]
TRIMRC0
Bit[10]
Bit[9]
...
Bit[8]
PLLTRIM0
Table 9.49: RC oscillator and PLL trimming register
TRIMRC [6:0]
trimming info for RC oscillator, to be transferred from flash/NV memory during startup
PLLTRIM [5:0]
trimming info for the PLL, to be transferred from flash/NV memory during startup
IO port: PLLCTRL Address: 0x203Eh
Bit[7]
Bit[6]
Bit[5]
CTLCK3
Bit[15]
Bit[14]
Access mode: Word – Read and Write
Bit[13]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
CTLCK0
SELXTAL
XTALON
CMEN
PLLEN
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
FBDIV7
...
FBDIV0
Table 9.50: PLL control bits and feedback divider
PLLEN
activate PLL, hardware will be switched to fast clock after PLL has locked
CMEN
clock monitor error interrupt enable, if=0, the CM error does not trigger an interrupt. The SLOW
clock will be activated in any case
XTALON
start crystal oscillator
This bit is without function , when no crystal oscillator is available
SELXTAL
select crystal oscillator as PLL source
This bit is without function , when no crystal oscillator is available
CTLCK[3:0]
pll unlock detection configuration, detailed configuration see 9.4.1.3
FBDIV[7:0]
feedback divider setting for PLL
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9.4.1.7 Interrupts connections
The clock monitor interrupt is connected into MULAN3 external interrupts block.
9.4.2 Supply sensor
9.4.2.1 Block Diagram
Vmeas_IN
Vmeas_ADC
Low-Pass
Filter
Vmeas_LP_ADC
IO:EN_Vmeas_ADC
SBY
Figure 9-36: block-diagram: supply sensor
The supply voltage of the IC can be measured by the ADC using the supply sensor. The gain and offset of this
sensor are calibrated during test in Melexis.
9.4.2.2 Supply voltage sensor filter
In order to avoid that this supply sensor reacts on noise on the supply voltage to measure, a first-order low-pass
filter is implemented on the output of the sensor. Both signals before and after the filter can be used for ADC
measurement.
9.4.3 Temperature Sensor
2 functions are implemented:
9.4.3.1 Temperature measurement:
Measurement of the on chip temperature with the ADC (see also “AD Converter System” paragraph)
The temperature measurement can be used for watching temperature drifts in system. The gain and offset of this
sensor are calibrated during test in Melexis. For temperature measurement two calibration points are used.
During wafer test the values for 150 °C and 35 °C are saved into NVRAM. These values are used as reference
points for the temperature sensor.
From the two saved values in the Non-volatile Memory the recent temperature can be computed by linear
interpolation.
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The built-in temperature sensor is linear by construction. It is directly connected to one of the ADC input
channels. On final wafer test this ADC channel is checked to be inside a given range.
Please also refer to package Rth data if approximation of ambient temperature is needed.
9.4.3.2 Over-Temperature detection
Detection of a temperature above the defined threshold for longer than the defined filter time.
In the case of thermal shutdown the Driver Part of the IC can be switched off to reduce power dissipation as
much as possible to prevent a thermal overheating of the IC and to get additional security for external
components (see paragraph “Drivers protection”).
9.4.4 Multi-purpose IO pins
9.4.4.1 Features
8 multiple purpose bi-directional IO pins (IO[7:0]) are available in MLX81325. Following table shows the
functional possibilities of the IO pins
IO function
VDDA tolerant
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
x
x
x
x
x
x
x
x
VS tolerant
x
Wake-up function
x
SPI Interface (Bidirectional)
x
x
x
x
Firmware controllable input: via debounce block
(note that debounce can be set to 0)
x
x
x
x
x
x
x
x
IRQ on debounced input
(rising / falling programmable)
x
x
x
x
x
x
x
x
Firmware controllable output
x
x
x
x
x
x
x
x
x
x
2
x2
x
x
Timer / PWM output
x
x
x
x
Access LIN Rx signal
x
Drive LIN TX signal
x
x
x
x
x
x
x
x
Timer capture inputs
x
x
x
x
x
x
x
x
Has its own ADC channel for measurement of
external voltage source
x
x
x
x
x
x
x
x
x
x
x
Test interface functionality
Table 9.51: IO functions
2
IO[7:6] support timer output only
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Every IO pin has an enable signal (EN), a digital output signal (OUT) and a disable PMOS signal (DIS_PMOS). The
combination of these 3 signals defines the state on the pin.
Every IO pin has an input IN_EXTIO.
VDD
DIS_PMOS_EXTIO[7:0]
IN_EXTIO[7:0]
IO[7:0]
ENABLE_EXTIO[7:0]
OUT_EXTIO[7:0]
Figure 9-37: IO port description
ENABLE_EXTIO
OUT_EXTIO
DIS_PMOS_EXTIO
OUTPUT function
0
X
X
Tri-state
1
0
X
Pull down (NMOS active)
1
1
0
Pull up (PMOS active)
1
1
1
Tri-state
Table 9.52: IO port logic function
IO3 is high voltage tolerant and has and extra wake-up input.
9.4.4.2 Digital IO output configuration
By default external IO[7:0] functions are connected as in following table:
IO functionality
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
when used as soft-IOs from ports ( IO{3:0}_OUTCFG[2:0]=111, IO{7:4}_OUTCFG[1:0]=11 )
ENABLE_EXTIO
ANA_OUTF
[0]
ANA_OUTF
[1]
ANA_OUTF
[2]
ANA_OUTF
[3]
ANA_OUTF
[4]
ANA_OUTF
[5]
ANA_OUTF
[6]
ANA_OUTF
[7]
DIS_PMOS_EXTI
O
ANA_OUTF
[8]
ANA_OUTF
[9]
ANA_OUTF
[10]
ANA_OUTF
[11]
ANA_OUTF
[12]
ANA_OUTF
[13]
ANA_OUTF
[14]
ANA_OUTF
[15]
OUT_EXTIO (=
SOFT_IO[7:0])
ANA_OUTN
[0]
ANA_OUTN
[1]
ANA_OUTN
[2]
ANA_OUTN
[3]
ANA_OUTN
[4]
ANA_OUTN
[5]
ANA_OUTN
[6]
ANA_OUTN
[7]
IN_EXTIO
IOIN[0]
IOIN[1]
IOIN[2]
IOIN[3]
IOIN[4]
IOIN[5]
IOIN[6]
IOIN[7]
IO1
IO2
IO3
Table 9.53 IO configuration
IO
IO0
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IO
IO0
IO1
IO2
IO3
IO[3:0] configuration for SPI in MASTER mode (IOx_OUTCFG[2:0]=000)
SPI Function
MOSI
_OUT
MISO_IN
SPSCK
SSOB
direction
output
input
output
output
ENABLE_EXTIO
1
0
1
1
= ANA_OUTF[3:0]
IO[3:0] configuration for SPI in SLAVE mode (IOx_OUTCFG[2:0]=000)
SPI Function
MOSI_IN
MISO
_OUT
SPSCK_IN SSIB
direction
input
output
input
input
ENABLE_EXTIO
0
1
0
0
= ANA_OUTF[3:0]
Table 9.54: IO[3:0] configuration for SPI
Note: When using IO[3:0] in SPI mode, IO[3:0]_OUTCFG (Table 9.55) must be 0. IN_EXTIO[3:0] and
OUT_EXT_IO[3:0] are not considered in SPI mode. DIS_PMOS_EXTIO can be set depending on external pull-up
use.
Connection of IO pin output is defined by IO_OUTCFG registers in port ANA_OUTM and ANA_OUTN.
IO port: ANA_OUTM (IO_OUTCFG) ( 0x28D6- 0x28D7h )
Bit[15]
Bit[14]
IO5_OUTCFG[1:0]
Bit[7]
Bit[6]
IO2_OUTCFG[1:0]
Bit[13]
Bit[12]
Access mode: Word, Byte– Read and Write
Bit[11]
IO4_OUTCFG[1:0]
Bit[5]
Bit[4]
Bit[10]
Bit[9]
IO3_OUTCFG[2:0]
Bit[3]
Bit[2]
IO1_OUTCFG[2:0]
Bit[8]
IO2_OUTCFG[2]
Bit[1]
Bit[0]
IO0_OUTCFG[2:0]
Table 9.55: ANA_OUTM / IO output configuration port
IOx_OUTCFG[2:0], x=0…3
IO output configuration:
000 - SPI output function as in pre-defined mode
001 - TIMER1_OUT
010 – TIMER2_OUT
011 – PWM2
100 – PWM3
101 – PWM4
110 – PWM1
111 - IO:SOFT_IO[x]
IOy_OUTCFG[2:0], y=4, 5
IO output configuration:
00 – 0
01 - TIMER1_OUT
10 – TIMER2_OUT
11 - IO:SOFT_IO[y]
IO port: ANA_OUTN(SOFT_IO) Address: 0x28D8 – 0x28D9
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Access mode: Word, – Read and Write
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IO port: ANA_OUTN(SOFT_IO) Address: 0x28D8 – 0x28D9
Bit[15]
Bit[14]
Bit[13]
IO7_OUTCFG[1:0]
Bit[7]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
x
x
x
SOFT_TX[0]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
SOFT_IO[4]
SOFT_IO[3]
SOFT_IO[2]
SOFT_IO[1]
SOFT_IO[0]
IO6_OUTCFG[1:0]
Bit[6]
Bit[5]
SOFT_IO[7] SOFT_IO[6] SOFT_IO[5]
Access mode: Word, – Read and Write
Table 9.56 : ANA_OUTN / SOFT IO configuration port
IOx_OUTCFG[1:0], x=6, 7
IO output configuration:
00 – 0
01 - TIMER1_OUT
10 – TIMER2_OUT
11 - IO:SOFT_IO[x]
SOFT_TX[0]
TX-pin software output
SOFT_IO[7:0]
Software output signal “OUT_EXTIO” for external IO[7:0]
9.4.4.3 Digital IO input description
IN_EXTIO[7:0]
debounce
Edge detector
IO:IO_DEB[7:0]
IO:IOINT[7:0]
IRQ controller
IFRB=0 => rising edge
IFRB=1 => falling edge
IO:DEB[15:0]
IO:IFRB[7:0]
Figure 9-38: debounce and interrupt connection of external IO port
IO port: IODEB Address: 0x28C0- 0x28C1
Bit[15]
Bit[14]
Bit[13]
Access mode: Word, Byte– Read and Write
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
Bit[2]
Bit[1]
Bit[0]
DEB[15:0]
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
DEB[7:0]
Table 9.57: IO port: External IO[5:0] debounce configuration
DEB[15:14]
Debounce time configuration for external IO7
DEB[13:12]
Debounce time configuration for external IO6
DEB[11:10]
Debounce time configuration for external IO5
REVISION 1.7 – 27. Apr 2020
00 – debounce off
01 – 1 ms (IO[7:6] : 100us)
10 – 4 ms (IO[7:6] : 200us)
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DEB[9:8]
Debounce time configuration for external IO4
DEB[7:6]
Debounce time configuration for external IO3
DEB[5:4]
Debounce time configuration for external IO2
DEB[3:2]
Debounce time configuration for external IO1
DEB[1:0]
Debounce time configuration for external IO0
11 – 8 ms (IO[7:6] : 400us)
IO port: ANA_INA Address: 0x281C – 0x281D
Access mode: Word, Byte– Read
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
OVT
UV_VS
OV_VS
PLL_INT
OC_DRV
VDS_MON
LIN_RX
LIN_RX_INT
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
IO_INT[7:0]
Table 9.58: IO port: interrupt sources
OVT
Over temperature
UV_VS
Under voltage VS
OV_VS
Over voltage VS
OC_DRV
Diagnostics Over Current Driver state
VDS_MON
Diagnostics - drain source voltage monitor for extern HS driver
LIN_RX
LIN-pin state read back
LIN_RX_INT
LIN RX interrupt flag
IO_INT[7:0]
Edge detector input from external IO[7:0]
IO port: IOIN ( 0x28CA )
Access mode: Word– Read
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
-
-
-
-
-
-
-
-
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
IO_DEB[7:0]
Table 9.59: IO port: external IO input
IO_DEB[7:0]
7 bit input port from debounced external IO pins
The pin IO3 can be driven with high voltage. The voltage on this pin can also be measured with the internal
implemented ADC using either direct voltage measurement (for low-voltage < 2.5 V) or internal divider (for highvoltage < 24 V).
The IO[5:4] pins are used to access the LIN internal signals Rx and Tx. Access to these signals allows using the IC in
various LIN modes which are described in paragraph 0
9.4.4.4 Test interface description
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The IO[7:5] can be used for emulation and test mode access, where IO[7:6]=TI[1:0], IO5=TO. It is recommended
to foresee an access possibility to those IOs independent of its application function. The test mode entry is
secured by a sequence to be applied immediately after power up.
9.4.5 AD converter system
The MLX81325 contains a 10 bit Analogue to Digital Converter (ADC).
This ADC is controlled via its registers to select desired ADC channel, starting with Start of conversion bit (SOC)
and detecting conversion’s end with End of conversion bit (EOC) to read conversion result when finished. The
ADC reference voltage can be selected in 3 different levels to get best possible resolution depending on the
measured channel. Each time a new VRH is selected by changing the selection bits in ADC_SBASE register – the
corresponding trimming value must be copied from Flash / ROM address location to trim register ADCTRIM. This
operation adjusts the reference voltage of ADC system to its best possible centered value. The values stored in
those flash / ROM addresses had been saved during chip test and it is recommended to copy them to the trim
register. If this copy is not performed, the reference will drift by mismatches in dividers, but will still stay useable,
if an additional mismatching of 5% is accepted.
The AD converter uses the successive approximation principle. After changing ADC channel selection, the current
AD result must be discarded, because it is invalid and not the result of conversion of the new selected channel.
Sampling a channel’s selected voltage is done as long the SOC bit is not written, which causes stop sampling and
start conversion for the actual addressed ADC channel.
In front of the ADC an analogue multiplexer allows the selection of one of 16 possible channels for ADC
conversion. The ADC runs correctly only if the PLL switched on.
9.4.5.1 Architecture
The architecture of the ADC interface is shown on the picture below:
Channel
select
Channel[0]
Channel[1]
OUT
…
ADC
EOC
Trigger
(SOC)
IN
Timer1_INT[3:0]
Timer2_INT[3:0]
ADC_EOC_SYNC
Ref
VS
TEMP
PWM1_INT[1:0]
TRIG_SRC
VRH3
VRH2
VRH1
Trigger
select
PWM3_INT[1:0]
PWM4_INT[1:0]
PWM5_INT[1:0]
SOFT_TRIG
Ref
select
PWM2_INT[1:0]
Channel[27]
IO7
to ADC Interrupt
RAM
RAM
Config 0
Transfer0
Read
Config 1
Write
SIN[4:0]
SREF[7:2]
ADC control unit
DMA request
SBASE counter
DBASE counter
Address
DMA channel
ADC_SBASE[15:0]
ADC_DBASE[15:0]
...
...
N
DMA channel
Config N
Sample 1
DMA request
N
Address
Sample 0
Transfer0
fer
ns
a
Tr
...
r
fe
ns
Write
a
Tr
...
Read
SREF[1:0]
Sample N
16bits
16bits
LOOP
START
SIN[4:0]
Input
channel
SREF[7:2]
Hardware
trigger
BIT[15]
REVISION 1.7 – 27. Apr 2020
SREF
[1:0]
ADC[9:0]
reference
voltage
ADC result
BIT[0]
BIT[15]
BIT[0]
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Figure 9-39 ADC interface architecture
For each channel, the selection of the analog input is made by a 5 bits register SIN and the selection of the ADC
trigger source and reference by an 8 bits register SREF. Both are regrouped in a 16 bit word in memory.
A register named SBASE is used to point to memory location for SREF:SIN for each channel and a register named
DBASE is used to point to memory location where ADC data will be stored.
9.4.5.2 Principle
The ADC hardware runs autonomously through DMA (Direct Memory Access) in the CPU memories. Before
starting the conversion(s), the software must fill a specific area in memory to describe the expected operations.
To start the ADC, The ADC_START bit in the control register has to be set, and then conversions are triggered by
events. The events can be software events (ADC_SOFT_TRIG), or hardware events (pulses on the HARD_TRIG
input). The choice is done with the ADC_TRIG_SRC bit in the control register.
The first conversion uses SIN0 and SREF0, and automatically stores the result of the conversion in ADC0, the
second conversion SIN1 and SREF1, and automatically stores the result of the conversion in ADC1, etc...
Once the last conversion is done, (i.e. the next SINi: SREFi = 0xFFFF), the interface can do the following:
 Trigger an interrupt for the CPU and stop
 Trigger an interrupt and restart from SIN0:SREF0 if the loop bit (ADC_LOOP) is set in the control
register.
Examples:
A) A single shot conversion triggered by the software.
With a RAM organized like shown on Figure 9-41
 Program the control register: ADC_START = 1, ADC_TRIG_SRC = 0 (to select the software trigger). This
will open the sample and hold switch.
 The conversion will be started upon software request: ADC_SOFT_TRIG = 1. This also close the
sample and hold switch.
 When the conversion is completed, the result is stored in ADC0.
 An interrupt is generated and the interface is ready to resume.
B) A four channel conversion triggered by an external event and stopped at the fourth channel.
With a RAM organized like shown on Figure 9-42:
 Program the control register: ADC_START = 1, ADC_TRIG_SRC = 1 (to select the external trigger).
 SIN and SREF are put on the ADC input multiplexers, The sample and hold switch is opened (sample
position)
 When HARD_TRIG is set, the sample and hold switch is closed (hold position) and the conversion
starts
 When the conversion is completed, the result is stored in RAM, the values for the next SIN and SREF
are read, and the interface waits for another trigger (note that if HARD_TRIG is still high, the next
conversion will start immediately).
 When SIN = SREF = 0xFF (after 4 conversions), an interrupt is generated and the interface is ready to
resume.
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C) A four channel conversion, permanently running, triggered by an external event.
With a RAM organized like shown on Figure 9-42:
 Program the control register: ADC_START = 1, ADC_TRIG_SRC = 1 (to select the external trigger),
ADC_LOOP = 1.
 SIN and SREF are put on the ADC input multiplexers, The sample and hold switch is opened (sample
position)
 When HARD_TRIG is set, the sample and hold switch is closed (hold position) and the conve rsion
starts
 When the conversion is completed, the result is stored in RAM, the values for the next SIN and SREF
are read, and the interface waits for another trigger (note that if HARD_TRIG is still high, the next
conversion will start immediately).
 When SIN = SREF = 0xFF (after 4 conversions), an interrupt is generated. The first couple of values for
SIN and SREF are read again and the conversions restart from the beginning.
9.4.5.3 ADC trigger selection
ADC_SREF[7:2]
ADC trigger from
Description
111100
TMR2_CAPA_IT
Capture Interrupt channel A
111000
TMR2_CAPB_IT
Capture Interrupt channel B
110100
TMR2_CMPA_IT
Compare Interrupt channel A
110000
TMR2_CMPB_IT
Compare Interrupt channel B
101100
TMR1_CAPA_IT
Capture Interrupt channel A
101000
TMR1_CAPB_IT
Capture Interrupt channel B
100100
TMR1_CMPA_IT
Compare Interrupt channel A
100000
TMR1_CMPB_IT
Compare Interrupt channel B
011100
PWM4_CMPI
enable PWM4 compare interrupt as ADC trigger
011000
PWM3_CMPI
enable PWM3 compare interrupt as ADC trigger
010100
PWM2_CMPI
enable PWM2 compare interrupt as ADC trigger
010000
PWM1_CMPI
enable PWM1 compare interrupt as ADC trigger
001100
PWM4_CNTI
enable PWM4 counter interrupt as ADC trigger
001000
PWM3_CNTI
enable PWM3 counter interrupt as ADC trigger
000100
PWM2_CNTI
enable PWM2 counter interrupt as ADC trigger
000000
PWM1_CNTI
enable PWM1 counter interrupt as ADC trigger
010110
PWM5_CMPI
enable PWM5 compare interrupt as ADC trigger
000110
PWM5_CNTI
enable PWM5 counter interrupt as ADC trigger
Table 9.60 ADC trigger selection
9.4.5.4 Memory needs
For n channels, (4n + 2 ) bytes of memory must be reserved. ( 2n + 2 ) bytes can be either in ROM or RAM as they
are read only while 2n bytes have to be reserved in RAM.
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Note: n can be any value > 0.
Memory
DBase+n
ADCn
ADCn
ADC controller action
Write
RAM
DBase+1
ADC1
Write
DBase
ADC0
Write
0xFFFF
Read
SINn:SREFn
Read
SBase+n
ROM or RAM
SBase+1
SBase
SIN1:SREF1
SIN0:SREF0
Read
Read
16 bits
Figure 9-40: ADC conversionmemory organisation
A extra word (ADC_LAST_CHANNEL=0xFFFF) is used to mark the end of the ADC input data (Remind that only 255
channels are possible).
Examples of memories:
A) A single channel conversion:
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Memory
DBase
SBase+1
SBase
ADC controller action
ADC0
Write
0xFFFF
Read
SIN0:SREF0
Read
16 bits
Figure 9-41: Single channel ADC conversion
Note: Sin0:Ref0 = 0x0000 (dummy value as there is no MUX and a single ADC ref).
B) A four channels conversion
Memory
ADC controller action
ADC3
ADC2
Write
Write
ADC1
ADC0
Write
Write
0xFFFF
Read
SBase+3
SIN3:SREF3
Read
SBase+2
SIN2:SREF2
Read
SBase+1
SBase
SIN1:SREF1
SIN0:SREF0
Read
Read
DBase+3
DBase+2
DBase+1
DBase
16 bits
Figure 9-42: Four channels ADC conversion
Entries of the channel table are organized as 16 bit words:
SINx:SREFx
Bit 15
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Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
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Bit 15
Name
Name
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reserved
Reserved
Reserved
SIN[4]
SIN[3]
SIN[2]
SIN[1]
SIN[0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SREF[7]
SREF[6]
SREF[5]
SREF[4]
SREF[3]
SREF[2]
SREF[1]
SREF[0]
Table 9.61 : ADC conversion table entries
SIN[4:0]: ADC channel selection, see Table 9.64
SREF[7:2]: Trigger selection, see Table 9.60
SREF[1:0]: ADC reference selection, 00 – off, 01 – 0.75 V, 10 – 1.5 V, 11 – 2.5 V
9.4.5.5 Timings
An example of conversion timing is given on the picture below:
Sofwareactions
SetupRAM
Start
ADC_START
SIN0
SIN1
SIN0
SREF0
SREF1
SREF0
S/H
SOC
EOC
DATA
DATA0
DATA1
DATA0
INT
Event
Event
Event
Select first input
Save DATA0 in RAM
Save DATA1 in RAM
Wait for event
Chech for last channel
Chech for last channel
Save DATA0 in RAM
Chech for last channel
Selectnextinputs
Wait for event
Selectnextinputs
Wait for event
Selectnextinputs
Wait for event
Figure 9-43 ADC conversion timing example
In this example, two channels have been defined, with event triggered start and permanent mode. CPU is
solicited every two conversions by an interrupt.
In order to stop the permanent conversion process, ADC_START can be asserted low and conversion(s) will stop
after the conversion of the last channel.
The time between 2 events is minimum equal to the sum of Sampling time (Tsamp) and Conversion time (Tconv).
9.4.5.6 ADC interface ports
CPU drives ADC interface via three 16 bits ports:
 ADC_SBASE
Pointer of bottom area for SIN:SREF
 ADC_DBASE Pointer of bottom area for ADC data
 ADC_CONTROL Configuration register
ADC_CTRL
0x2811
Bit 15
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Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
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0x2811
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
ADC_EOC
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADC_SOFT
_TRIG
Access
R-O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0x2810
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
ADC_SYNC
_SOC
Reserved
Reserved
Reserved
Reserved
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
ADC_LOOP ADC_TRIG
_SRC
ADC_
START
Table 9.62 : ADC control port
ADC_START: 0b0 = ADC Stopped, 0b1 = ADC start
ADC_TRIG_SRC: 0b0 = Software trigger mode, 0b1 = Hardware trigger mode
ADC_LOOP: 0b0 = Single conversion cycle, though all channels (table-entries); 0b1 = Permanent conversion
ADC_SYNC_SOC: 0b0 = Do not discard first conversion; 0b1 = Discard first conversion
ADC_SOFT_TRIG: 0b1 = Start next channel conversion (cleared when conversion is started)
ADC_EOC: End-of-conversion.
Detailed remarks:
ADC_START (bit 0): Start a conversion cycle when set. If reset before the end of conversion, the cycle is
interrupted after the current conversion is finished (the result of the current conversion will be written in
memory). Once a conversion cycle is finished, this bit is cleared, unless the loop mode is enabled.
ADC_TRIG_SRC (bit 1): Selects the source of the start of conversion. If cleared, the conversion is triggered by
software (see ADC_SOFT_TRIG below). If set, the conversion is triggered by external input HARD_TRIG set
for at least one OSC period
ADC_LOOP (bit 2): If cleared, a single cycle of conversion is done (i.e. all channels converted one time). If
set, the conversion cycle is restarted endlessly (an interrupt is generated at the end of each conversion
cycle).
ADC_SOFT_TRIG (bit 8): When ADC_TRIG_SRC=0, setting this bit starts a conversion. It is automatica lly
cleared when the conversion is started. Only ONE conversion is done.
ADC_EOC (bit 15): Flags an ongoing conversion (when set). Can be used for polling in case of software
triggered conversions.
All other bits have no function and are read to zero.
ADC_SBASE
0x2812
Bit 15-0
Name
ADC_SBASE
Access
R/W
POR
xxxx
ADC_SBASE: ADC Source base (pointer); A table with channel, trigger and ADC reference. See 9.4.5.7.
ADC_DBASE
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0x2814
Bit 15-0
Name
ADC_DBASE
Access
R/W
POR
xxxx
ADC_DBASE: ADC Data base (pointer); Pointer to RAM to store sampled ADC channel
Table 9.63 : ADC pointer ports for channel selection and result
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9.4.5.7 ADC Channel selection
The ADC can select one of the 24 channels described below with the ADC_SIN[4:0] bits:
ADC_SIN[4:0]
4 3 2 1
CH
HV / LV
Source
0
Input voltage Remark
range
0
0
0
0
0
0
HV
VS
0-16*fsrx
divided by 16
0
0
0
0
1
1
LV
TEMP
internal
Internal temperature sensor 1
0
0
0
1
0
2
LV
VDDD
internal
Digital supply voltage
0
0
0
1
1
3
LV
VDDA
internal
Analogue supply voltage divided by 2.
0
0
1
0
0
4
HV
VSM_FILT
0-16*fsrx
Output of the VSM Supply Sensor
(=VSM/16) after filtering
0
0
1
0
1
5
LV
IO0
0-fsrx
IO0 voltage
0
0
1
1
0
6
LV
IO1
0-fsrx
IO1 voltage
0
0
1
1
1
7
LV
IO2
0-fsrx
IO2 voltage
0
1
0
0
0
8
LV
IO3
0-fsrx
IO3 voltage
0
1
0
0
1
9
HV
U
0-16*fsrx
Voltage on U Driver output divided by 16
0
1
0
1
0
10
HV
V
0-16*fsrx
Voltage on V Driver output divided by 16
0
1
0
1
1
11
HV
W
0-16*fsrx
Voltage on W Driver output divided by 16
0
1
1
0
0
12
LV
LINAA_OUT
0
1
1
0
1
13
LV
SENSE
0-fsrx/10
Voltage on ILS mult. by 10
0
1
1
1
0
14
HV
VSM
0-16*fsrx
divided by 16
0
1
1
1
1
15
LV
LINAA_CMO
internal
LIN AA input common mode
HV
VREF
0-16*fsrx
LS driver voltage divided by 16
LIN SHUNT Current
16
1
0
0
0
1
17
1
0
0
1
0
18
reserved
1
0
0
1
1
19
reserved
1
0
1
0
0
20
reserved
1
0
1
0
1
21
LV
IO4
0-fsrx
IO4 voltage
1
0
1
1
0
22
LV
IO5
0-fsrx
IO5 voltage
23
reserved
1
1
0
0
0
24
HV
IO3_DIV16
0-16*fsrx
IO3 voltage divided by 16
1
1
0
0
1
25
HV
T
0-16*fsrx
Voltage on T Driver output divided by 16
1
1
0
1
0
26
LV
IO6
0-fsrx
IO6 voltage
1
1
0
1
1
27
LV
IO7
0-fsrx
IO7 voltage
28
to 31
reserved
Table 9.64 ADC channels selection
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9.4.6 Watching the API by Analogue Watchdog (AWD)
In the IC an Analogue Watch Dog is implemented. This watchdog it has no pin and saves so the usage of an
external capacitor.
The watchdog uses a completely separate 10kHz oscillator. Its nominal period tAWD_PER is measured and stored
during production test. Details will be defined in a future specification revision.
The watchdog starts always with maximum timeout delay immediately after releasing the Master reset, so it has
the same behavior after POR or WAKE UP from SLEEP MODE.
The application has no possibility to stop this watchdog.
After half of the timeout (tAWD_TIMEOUT/2) the analogue watchdog generates an info signal AWD_ATT, that is
connected to watchdog attention interrupt.
When the timer reaches the AWD_TIMEOUT, a reset is issued. The reset feeds directly into the system reset
(INT0).
The watchdog delay is programmable by application through the port AWD containing 8 bits for AWD_TIME and
2 bit for the clock prescaler AWD_CKDIV (division ratios are 1-4-16-64).
The delay can be updated via the AWD port at any time. A write to the AWD port resets the watchdog counter
and therefore acknowledges the watchdog.
The watchdog timeout can be calculated by:
t AWD_TIMEOUT  t AWD_PER * AWD_CKDIV* AWD_TIME
Equation 28
The maximum programmable watchdog time is ~0.1ms * 64 * 256 = 1.6s typ.
9.4.6.1 AWD Ports
IO port: AWD ()
Access mode: Word – Read and Write
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Bit[9]
Bit[8]
AWD_TIME[7:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
AWD_RST
AWD_ATT
AWD_
WRITE_FAIL
AWD_TF
-
-
AWD_CKDIV[1:0]
Table 9.65 AWD Port
AWD_TIME [7:0]
timeout divider register
0x00 = 0xFF = max delay, reset to 0x00 by POR or WAKE UP, write to this register
restarts the internal AWD timer
AWD_CKDIV[1:0]
AWD clock prescaler : 00=by 64 ; 01=by 16; 10=by 4; 11=by 1
AWD_TF
This flag shows, that the data transfer to the AWD_CK clock domain is still ongoing;
could be used for polling before next write; read only
AWD_
WRITE_FAIL
this flag is set, when the data written from the CPU could not be transferred to the
AWD_CK clock domain properly
Read/Write , cleared by POR or WAKE UP or write with 0
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AWD_ATT
Watchdog info flag, memorizes a watchdog attention interrupt
Read/Write , cleared by POR or WAKE UP or write with 0 twice (time between the two
writes must be at least two periods of AWD_CK or use flag AWD_TF)
AWD_RST
Watchdog reset flag, memorizes an analogue watchdog reset
Cleared by POR or WAKE UP or write 0
9.4.6.2 Interrupt connections
The analogue watchdog shares its 2 interrupt sources with the digital watchdog included in MULAN3. The
AWD_ATT and AWD_RST flags can be read to determine, that the watchdog reset was caused from analogue
watchdog.
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9.4.7 Output drivers
9.4.7.1 Features
Four pairs of push-pull output drivers are implemented for the external high- and low-side driver FETs.
These drivers should be driven with PWM 10…50kHz and duty-cycle from 5% to 95%.
In order to avoid EMC emission problems, resistors should be inserted between the predriver outputs of the IC
and the gates of the driver FETs. To protect the driver FETs from overheating, several protections sensors are
implemented (see Figure 9-44):
1. A ground based current sensor for the motor current,
2. A VDS monitor for the high-side driver FETs,
3. Overvoltage monitor from VSM and undervoltage monitor of the supply voltage VS,
4. Overtemperature protection.
MLX81325
Driver NFets
VSUP
from digital
PROT_SENSORS
VSM
X
ILS
GNDM
OV_VS
UV_VS
OC_DRV
OVT
VDS
MOTOR_DRV
PWM
DRV_CFG[1:0]
OV_VS
DIS_OV HSX
OVPM
UV_VS
DIS_UV
UVPM
OC_DRV
X
DIS_OC
OCPM
OVT
DIS_OT
OVTPM LSX
VDS
DIS_VDS
VDSPM
VSM
HSX
X
to Motor
LSX
DIS_DRV
DIS_SHOA
X = T, U, V, W
ILS
GNDM
GND
Figure 9-44: Motor driver block schematic.
9.4.7.2 Driver switching
The top-side pre-drivers (HSHS and HSLS, see Figure 9-45, only one phase shown) will switch on one of the topside NFET transistors (HS_DRV) and switch off another top-side NFET transistor at each change of state of the
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motor.
To switch on the high-side NFET (HS_DRV), the gate of the NFET is pulled to a voltage VBOOST, generated by the
charge pump. Switching off is done by pulling the gate of the NFET to the corresponding phase voltage. The
switching is done with a relatively low impedance to avoid parasitic activation of the NFET.
The design of the pre-driver is made such that there can never be a current flow through the switching on
transistor and the switching off transistor at the same time.
Top- and bottom-side Nfets are controlled by a PWM signal with variable duty cycle.
MLX81325
Driver FETs
VBOOST
VSUP
HSHS
HSx
HS_DRV
HSLS
X
to motor
phase
VREF
LSHS
LSx
LS_DRV
LSLS
X = T, U, V, W
Figure 9-45: Pre-driver circuit.
9.4.7.3 Block Diagram
The driver state is defined by the commands coming from the digital part (controlled by software) as well as by
internal sensors which detect fault condition which could require change of drivers’ state to protect the IC. These
signals are processed by digital motor control logic to generate non-overlapping clocks for the pre-drivers (see
Figure 9-46, only one phase shown, the driver circuits of all phases are the same).
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Digital Control Logic
MOTOR_CTRL
PWM
DRV_CFG[1:0]
Predriver Fets
Levelshifters
VBOOST
HSON
OV_VS
Lev.
Shift
HSHS
DIS_OV
OVPM
UV_VS
DIS_UV
UVPM
HSOFF
Lev.
Shift
HSLS
OC_DRV
LSON
Lev.
Shift
DIS_OT
OVTPM
VDS
DIS_VDS
VDSPM
X
VREF
DIS_OC
OCPM
OVT
HSX
LSOFF
Lev.
Shift
LSHS
LSLS
LSX
X = T, U, V, W
DIS_DRV
Figure 9-46: Block schematic of the driver stage MOTOR_DRV.
9.4.7.4 Motor control logic
The motor control logic processes the commands from the PWM, the CPU and the motor protection sensors to
generate the switching signals for the predriver FETs. The FET drivers are primarily controlled by the PWM and
the driver configuration bits DRV_CFG. In case of motor protection events (over- or undervoltage, overcurrent,
over temperature or drain-source overvoltage) the control logic can be configured to switch the motor to a safe
state.
The motor control logic consists of two parts, the motor protection logic MOTOR_PROT and the interlock delay
control ILD_CTRL. The motor control logic computes the correct reaction to the sensor inputs. The interlock
control combines the outputs of the protection logic, the PWM output. The interlock control outputs the predriver control signals to drive the external NFETs into the correct state without internal or external cross currents
(see Figure 9-47).
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ILD_CTRL
PWM
DRV_CFG[1:0]
PWM
DRV_CFG[1:0]
MOTOR_PROT
OV_VS
DIS_OV
OVPM
UV_VS
DIS_UV
UVPM
OC_DRV
DIS_OC
OCPM
OVT
DIS_OT
OVTPM
VDS
DIS_VDS
VDSPM
OV_VS
DIS_OV
OVPM
UV_VS
DIS_UV
OVPM
OC_DRV
DIS_OC
OCPM
OVT
DIS_OT
OVTPM
VDS
DIS_VDS
VDSPM
DIS_DRV
DIS_DRV
OFF
OFF
TRI
TRI
HSON
HSON
HSOFF
HSOFF
LSON
LSON
LSOFF
LSOFF
Figure 9-47: Block schematic of the motor control logic MOTOR_CTRL.
The interlock delay control (see Figure 9-48) arbitrates between the inputs from the PWM, the driver control bits
DRV_CTRL and the inputs from the motor protection logic. The motor protection overrides the inputs from the
PWM and the control bits. In case of conflicting motor protection states (TRI = 1 and OFF = 1) tristate takes
precedence over switching the motor phase to ground. Furthermore, the needed interlock delays are respected
also in the case of motor protection events.
iIDL
HSON
OFF
eIDL
PWM
DRV_CFG[0]
iIDL
0
iIDL
HSOFF
1
DRV_CFG[1]
eIDL
iIDL
iIDL
LSON
iIDL
TRI
LSOFF
Figure 9-48: Interlock delay control ILD_CTRL.
The block also defines the correct timing among the pre-driver signals HSON, HSOFF, LSON and LSOFF. The delay
blocks delay the rising edges of the input by the external or internal interlock delay eIDL and iIDL respectively.
The external interlock delay eIDL ensures that there is no cross current between the external high- and low side
driver NFETs (HS_DRV and LS_DRV in Figure 9-45). The internal interlock delay iIDL ensures that there is cross
current between the MLX81325 pre-driver FETs (between HSHS and HSLS and between LSHS and LSLS
respectively). The resulting waveform is a non-overlapping clock for the pre-driver control signals (see Figure
9-49).
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PWM
eIDL
eIDL
iIDL
iIDL
HSON
HSOFF
LSON
LSOFF
iIDL
iIDL
Figure 9-49: Interlock delay timing.
There are two possible reactions to motor protection events, switch the motor phase to ground (OFF = 1,
external low-side NFET conducting) or tristate (TRI = 1, both external NFETs high-impedant) for the overcurrent,
overtemperature and VDS monitor sensors. The over- and undervoltage sensors always switch the driver to
tristate. Each protection sensor can be disabled. If disabled the sensor output does not influence the motor
driver (interrupts can still be generated), see Figure 9-50.
OV_VS
DIS_OV
OVPM
UV_VS
DIS_UV
UVPM
OFF
OC_DRV
DIS_OC
OCPM
OVT
DIS_OT
TRI
OVTPM
VDS
DIS_VDS
VDSPM
DIS_DRV
Figure 9-50: Motor protection logic MOTOR_PROT.
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9.4.7.5 Motor Protection Sensors
The sensor inputs for the motor protection logic are derived from the external supply and phase voltages and
from the voltage drop across external shunt in the motor ground line (see Figure 9-51). In addition there is an
internal temperature sensor. In total five motor protection signals are observed:
1. Overvoltage monitor of the supply voltage VS,
2. Undervoltage monitor of the supply voltage VS,
3. Overtemperature protection.
4. VDS monitor for the high-side driver FETs (voltage difference between VS and phase),
5. Ground based current sensor for the motor current,
VSM
V_UV
COMP
OV_VS
COMP
UV_VS
V_OV
T
COMP
OVT
V_OVT
OPA
X
COMP
VDS
V_VDS
ILS
OPA
GNDM
COMP
OC_DRV
V_OC
Figure 9-51: Motor protection sensors PROT_SENSORS.
To verify that the external FET driver transistors are working in a safe operating range, the drain-source voltage
drop of the top-side NFETs is measured and compared to a threshold voltage. When the voltage exceeds the
value Vds then all motor driver transistors are switched off and an interrupt is generated.
To avoid false protection events because of voltage and current spikes due switching of the driver NFETs, the
over current comparator output is digitally debounced by the adjustable time Toc.
The VDS output only generates protection events when the respective driver NFET is switched on and after an
adjustable blank time Tvds after the switch on event has expired (see Figure 9-52).
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PWM
HSON
HSOFF
VDS on
Tvds
Figure 9-52: Blank time for VDS monitor.
9.4.7.6 Output driver ports
IO port: DRVCFG ( 28C6)
Bit[7]
Access mode: Word – Read and Write
Bit[6]
Bit[5]
DRV_CFG_W[1:0]
Bit[4]
DRV_CFG_T[1:0]
Bit[3]
Bit[2]
DRV_ CTRL _U[1:0]
Bit[1]
Bit[0]
DRV_ CTRL _V[1:0]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
DIS_OVT
DIS_OC
DIS_UV
DIS_OV
OVTPM
DIS_SHOA
OCPM
DIS_DRV
Table 9.66 - DRVCFG port
DRV_CFG_X[1:0]- Driver configuration for T,U,V,W phases: 0b00 = Tri-state; 0b01 = PWM; 0b10 = Low; 0b11
= High
DIS_OVT - disable over temperature protection, active high, default state low.
DIS_OC - disable over over current protection, active high, default state low.
DIS_UV - disable over under voltage protection, active high, default state low.
DIS_OV - disable over over voltage protection, active high, default state low.
DIS_SHOA - disable OpAmp for ADC measurement of shunt current, default state low.
OCPM - driver configuration at over-current(OC): 0 = To Ground; 1 = Tri-state
DIS_DRV- set driver outputs to tristate, default state low.
OVTPM: - driver configuration at over-temperature (OVT): 0 = To Ground; 1 = Tri-state
IO port: DRVCFG_EXT (0x 28C2)
Access mode: Word – Read and Write
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
reserved
reserved
reserved
reserved
reserved
CPDRV
CS_CAL
DIS_VDS
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
reserved
reserved
reserved
reserved
reserved
OVPM
UVPM
VDSPM
Table 9.67 - DRVCFG_EXT port
CPDRV - level of CPDRV if TRIMCPOSC = 3'b100 (in ANA_OUTA[4:2])
CS_CAL - if set to 1 the current sensor is in offset calibration mode (offset can be measured at ADC)
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DIS_VDS - disable VDS monitor :
1 – VDS monitor has no effect on phase pins,
0 – VDS monitor switches phase pins to ground or tristate (depending on VDSPM bit)
OVPM - driver configuration at over-voltage (OV): 0 = To Ground; 1 = Tri-state
UVPM - driver configuration at under-voltage (UV): 0 = To Ground; 1 = Tri-state
VDSPM - driver configuration at VDS error: 0 = To Ground; 1 = Tri-state
If DIS_DRV is set to “1” analogue driver outputs T, U, V, W are in tristate and analogue driver itself is OFF to
reduce current consumption.
9.4.7.7 Phase to PWM alignment
The phases and PWMs are aligned as follows:
Phase
PWM
W
PWM5
V
PWM4
U
PWM3
T
PWM2
9.4.7.8 Protection signals routing to ports and interrupts
The motor protection sensor outputs are used to trigger interrupts and feed into the motor control logic.
All the protection signals are inputs for external interrupt 5, for the detailed positions please refer to 9.3.3.7.
External Interrupt 5 - Motor Protection Interrupt Inputs
Interrupt Source
Description
PORT
PEND
ANA_INA[15]
OVT – over temperature event
XI4PEND[15]
ANA_INA[14]
UV_VS – under voltage event
XI5PEND[14]
ANA_INA[13]
OV_VS – over voltage event
XI4PEND[13]
ANA_INA[12]
PLL INT - pll interrupt
XI4PEND[12]
ANA_INA[11]
OC_DRV - over currents sense detection
XI4PEND[11]
ANA_INA[10]
VDS - drain source voltage monitor for extern HS driver
XI4PEND[10]
Table 9.68 motor protection interrupts mapping, see also to 9.3.3.7
The sensor output signals OVT, UV_VS, OV_VS, OC_DRV are sampled into the ANA_INA port and feed into the
interrupt detection logic for extern interrupt 5.
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All interrupts are edge-sensitive, means the rising edge of the input signal (in ANA_INA) will trigger the interrupt
(for 1 clock pulse) and set the belonging pending register (XI4PEND[xx]).
The output of the pending registers are in fact the control signals used in the motor control logic (refer 9.4.7.4),
i.e. the input OV_VS in Figure 9-47 or Figure 9-50n is driven from XI4PEND[13] )
The VDS differs from the other sensor inputs, as it is a decoded signal form VDS inputs form all 4 phases. A
dedicated logic will select the appropriate VDS of the active driver, apply the blank times needed and provide the
VDS input for the ANA_INA port and the interrupt controller (see Figure 9-52)
OC
from sensor
from sensor
D
Edge Detect
Q
ANA_INAx
clear
rising edge
detection
Q
ANA_INAx
clear
rising edge
detection
Q
ANA_INAx
clear
rising edge
detection
Q
ANA_INAx
clear
rising edge
detection
Q
ANA_INAx
clear
rising edge
detection
OV_VS
Analog
filter
UV_VS
Analog
filter
Analog
filter
from HS driver
monitors
D
OVT
VDS[3:0]
D
Extern Interrupt Controller
set
set
set
D
Q
XIPENDx
clear
D
Q
XIPENDx
clear
D
Q
XIPENDx
clear
D
Decode
active driver
D
set
set
Q
XIPENDx
clear
D
Q
XIPENDx
clear
MOTOR_CTRL
Levelshifters
VBOOST
Lev.
Shift
HSON[3:0]
HSON
PWM
DRV_CFG[1:0]
Lev.
Shift
X = T, U, V, W
HSOFF
LSLS
write ‘1’ to
MULAN3
CPU
core
read from
write ‘1’ to
read from
write ‘1’ to
Lev.
Shift
Lev.
Shift
PWM
blocks
UV_VS
DIS_UV
UVPM
OC_DRV
LSHS
read from
DIS_OV
OVPM
HSOFF[3:0]
HSLS
VREF
LSX
write ‘1’ to
OV_VS
HSHS
X
read from
XI4PEND port
Predriver Fets
HSX
write ‘1’ to
XIPEND
ANA_INA port
D
uC core
read from
XIPEND
ANALOG PART
from sensor
Digital
debounce
(DEB_OC)
Boundary Scan Register
from sensor
Sample
DIS_OC
OCPM
LSON[3:0]
LSON
OVT
configu
ration
ports
DIS_OT
OVTPM
LSON[3:0]
LSOFF
VDS
DIS_VDS
VDSPM
DIS_DRV
Figure 9-53 signal routing of motor protection signals to ports and interrupts
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9.4.8 Driver current sensing
The current sensing is done over an external sense resistor in the ground path of the drivers, as shown in Figure
9-54.
Drivers
debounce
COMP
OC threshold
OC interrupt
ILS
Sense resistor
ADC
OPA
GNDM
Board
Vcs0
MLX81325
Figure 9-54: current sensing and overcurrent detection
There are two ways to monitor the motor current
1. A comparator compares the voltage V(ILS) with a fixed threshold. Overcurrent can generate an interrupt
and/or switch off the motor by the overcurrent condition.
2. An op-amp amplifies the voltage V(ILS) before passing it to the ADC. The current sense signal is averaged
by a low pass filter. The voltage VADC at the ADC input is
VADC = Vcs0 + V(ILS) * Acs
where VCS0 is the reference voltage of the current sensor and ACS is its gain. The input of the op-amp can
be shorted internally to calibrate the offset of the amplifier.
The current sensor must be enabled by software. This cell can be disabled in holding mode to reduce the current
consumption of the IC.
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9.5 LIN interface
9.5.1 Introduction
The LIN protocol is implemented on a MULAN3 core on the MLX4 part. The complete MLX16 part is free for the
application. With this dual core architecture the bus communication is decoupled from the application. The
complete LIN driver running on the MLX4 is part of the software development system and will be supported by
Melexis. The communication between both CPUs is done via an API. This API uses the common RAM area for data
exchange. The application task (running on MLX16) transmits all necessary LIN configuration data via the API to
the LIN task (running on MLX4) during the initialization process. Further information can be found in the
document [7].
9.5.2 LIN Physical Layer
The LIN physical interface consists of two main blocks:
 the LIN standard interface for master-slave communication and
 an autoconfig block to detect the position of the slave on the bus with a special protocol.
Standard interface
Autoconfig block
Ipu
Iacfg
LINOUT
LININ
+
To ADC
slope
TxD
transmitter
RxD
Rx
Figure 9-55: LIN physical layer block schematic.
This interface is compliant to LIN 2.0 and LIN2.1 standards.
It also supports COOLING 2.3 and its updated version for autoaddressing.
The autoconfig block consists of:
 an extra pull-up current source,
 a differential switched capacitor current sense amplifier with auto-zero.
Melexis is providing the whole protocol + API interface for the LIN. All calibration settings for the current sources
will be defined during Melexis test and saved in the flash memory. The customer only needs to communicate to
the API interface.
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Documentation is available, that is valid as well and part of the SW tools and libraries.
9.5.3 Application Recommendations for the pins LIN_IN and LIN_OUT
In case the slave node position detection via the bus shunt method (BSM) is not used in the application Melexis
recommend making a direct electrical connection between the LIN_IN and LIN_OUT pin. This will increase the
EMC performance.
9.5.4 LIN special application modes
Additionally to the normal integrated LIN functionality there are 4 special application modes available. The
default configuration is shown in
external
LIN BUS
MLX81325
analog
LIN
LINPHY
digital
RX_IN
Communication
CPU MLX4
TX_OUT
Figure 9-56 LIN routing in default configuration
9.5.4.1 Special application mode 1 - external physical layer
In this mode the internal protocol layer for LIN is used and the physical LIN layer is external.
The mode is activated by the ports map bit LIN_EN_XPHY and by writing the value 0x5F0A to port LIN_XKEY
The access to the internal layer is through the pins
 IO4 (RX direction)
 IO5 (TX direction)
external
MLX81325
analog
RX_IN
LIN
LINPHY
Not used in
application
digital
TX_OUT
IO4
RX
LIN BUS
LIN_XIN
LINPHY
1
TX
Communication
CPU MLX4
LIN_XOUT
IO5
MLX81325
IO pins
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LIN_EN_XPHY =1
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Figure 9-57 LIN routing in external physical layer mode
9.5.4.2 Special application mode 2 - external protocol layer
In this mode the internal physical layer of LIN is used and the protocol layer is provided externally, e.g. by an
external CPU
To activate by the ports map bit LIN_EN_XPRO and by writing the value 0x5F0A to port LIN_XKEY
The access to the internal layer is through the pins
 IO4 (TX direction)
 IO5 (RX direction)
external
MLX81325
analog
LIN_EN_XPRO =1
RX
LIN
LIN BUS
digital
LINPHY
IO4
RX_IN
0
TX_OUT
1
TX
Communication
CPU MLX4
LIN_XIN
TX
External
CPU
RX
LIN_XOUT
IO5
MLX81325
IO pins
Figure 9-58 LIN routing in extern protocol mode
9.5.4.3 Special application mode 3 - direct access from application CPU
In this mode the application CPU (MLX16) has full access to the LIN physical layer. The communication CPU is
disconnected completely.
For activation the following ports have to be set:
LIN_XKEY=0x0
LIN_KEY = ANA_OUTL[15:8] = 0x43
The output direction can be configured according Table 9.69.
external
MLX81325
analog
(LIN_KEY=0x43) =1
RX
LIN
LIN BUS
digital
LINPHY
RX_IN
0
TX
TX_OUT
1
RX
TX
Communication
CPU MLX4
Application
CPU MLX16
Figure 9-59 LIN routing in direct access mode
The output channel can be configured by the SEL_TXOUT bits from port ANA_OUTK.
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The input (RX_IN) is available as interrupt source in ANA_INA[8] <=> XI4PEND[8] (refer to 9.3.3.7) or as static read
only flag in ANA_INA[9].
The physical layer inputs DISTERM, SLEEPB_LIN, LSM, HSM and BYPASS are driven from the port ANA_OUTK[4:0].
SEL_TX_ OUT[3:0]
TXOUT
0000
PWM2
0001
PWM3
0010
PWM4
0011
PWM1
0100
TIMER1_OUT
0101
TIMER2_OUT
0110
SOFT_TX(*)
0111
IO[0]
1000
IO[1]
1001
IO[2]
1010
IO[3]
1011
IO[4]
1100
IO[5]
1101
IO[6]
1110
IO[7]
1111
PWM5
Table 9.69 LIN output source configuration in direct access mode
Notes:
(*) SOFT_TX = ANA_OUTN[8]
9.5.4.4 LIN special modes port configuration
IO port: LIN_XCFG ( 0x2820)
Access mode: Word – Read and Write
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
SLEEPB_LIN
LSM
HSM
BYPASS
LIN_XOUTINV
-
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
-
-
-
-
-
-
Bit[1]
LIN_EN_XPHY LIN_EN_XPRO
Bit[9]
Bit[8]
LIN_XPHY_ACT LIN_XPRO_ACT
Table 9.70: LIN Configuration Port 1
LIN_EN_XPRO
Enable external protocol layer for LIN (if LIN_XKEY is valid)
LIN_EN_XPHY
Enable external physical layer for LIN (if LIN_XKEY is valid)
LIN_XOUTINV
Invert LIN_XOUT signal (for driving the IO5): 0: non-inverted, 1: inverted
BYPASS
HSM
control bits used in LIN_XPRO mode for internal physical layer
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LSM
SLEEPB_LIN
LIN_XPRO_ACT
READ: 1: LIN external protocol layer is activated, 0: external protocol layer not activated
LIN_XPHY_ACT
READ: 1: LIN external physical layer is activated, 0: external physical layer not activated
IO port: LIN_XKEY (0x2042)
Bit[7]
Bit[6]
Access mode: Word – Read and Write, system bit protected
Bit[5]
LIN_XKEY7
Bit[15]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
...
Bit[14]
Bit[13]
LIN_XKEY15
Bit[0]
LIN_XKEY0
Bit[12]
Bit[11]
Bit[10]
Bit[9]
...
Bit[8]
LIN_XKEY8
Table 9.71: LIN_XKEY Configuration Port
LIN_XKEY[15:0]
16 bit key to enable special LIN application modes 1 (LIN_XPHY) and 2 (LIN_XPRO)
Predefined value (0x5F0A) has to be entered to enable LIN_XCFG port *
LIN_XKEY[0]
- to read LIN_XKEY_VALID: 1=LIN_XKEY was written correctly, 0=else
IO port: ANA_OUTK (0x28D2) Access mode: Word – Read and Write
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
-
-
-
_DISTERM
_SLEEPB_LIN
_LSM
_HSM
_BYPASS
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
-
-
-
-
SEL_TX_OUT3
...
SEL_TX_OUT0
Table 9.72: IO port ANA_OUTK
SEL_TX_OUT[3:0]
output selector for LIN direct access mode, refer to Table 9.69
_BYPASS
_HSM
_LSM
_SLEEPB_LIN
_DISTERM
physical layer control bits used in LIN direct access mode
IO port: ANA_OUTL (0x28D4)
Access mode: Word – Read and Write
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
-
-
-
-
-
-
-
-
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
LIN_KEY7
...
LIN_KEY0
Table 9.73: IO port ANA_OUTL
LIN_KEY[7:0]
enter predefined value ANA_OUTL[15:8] = 0x43 to enable LIN direct access mode *
*LIN_XKEY and ANA_OUTL are to be used exclusively only.
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9.5.5 LIN Slave Node Position Detection (auto-configuration)
The physical layer implemented supports LIN Slave node position detection (Auto-configuration) according to the
bus shunt method 'BSM' (refer to [4]) by providing a dedicated offset-compensated instrumentation amplifier
and special ADC channel. Furthermore different free-configurable pull up currents can be applied in accordance
to the chosen specification.
Melexis provides a software library which supports the LIN Auto-Addressing feature of the controller. The library
is part of the Melexis Software Platform.
Figure 9-60 – Principle architecture of a LIN-network supporting auto-configuration measurements
The network consists of a master node and up to 16 slave nodes. The slave nodes supporting the autoconfiguration are wired in a kind of daisy chain via the 2 pins LIN_IN and LIN_OUT. The incoming current on pin
LIN_OUT forced by the chain members behind has to be measured in order to assess the position in the network.
The network can be mixed containing standard LIN-slaves as well.
9.5.5.1 LIN BSM global timing
The measurement procedure for the LIN auto-configuration will happen only during the initial 1st communication
of the complete network to assign all slave nodes a dedicated address. In dependence of the number of slaves as
well as the resolution of the implemented amplifier concept, a couple of cycles will be required in order to assign
all slave-node addresses. The procedure will restart either a new slave is added to the network or a slave with
already assigned address has to be substituted by a new one.
Figure 9-61 – LIN frame - auto-configuration happens in the Break field
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If the auto-configuration feature is enabled, the auto-configuration procedure happens in the Break field, were
either bit phase signals or bit interrupts are needed.
9.5.5.2 LIN BSM local timing
The BREAK field length is minimal 13 nominal bit time low + 1 bit time high. Within this minimum time frame
(defined by the maximum baud rate of 20kbaud) the following measurement phases are defined.
Figure 9-62 – General timing diagram of node position measurement
Step
Action
Start of action (TBIT)
1
Switching off all Pull-Ups and all current sources
0 (Falling edge of break field)
2
Start offset measurement (I_shunt_1)
1
3
Switching on LIN Pull up
4
4
Start the measurement 1 (I_shunt_2)
5
5
All not pre-selected (first action A) nodes switching off their pull
up with the falling edge of Terr signal.
All pre-selected SNPD (second action B) nodes are switching on
their current source with the rising edge of TBIT signal
8
6
Start the measurement 2 (I_shunt_3)
9
7
Switching off all current sources and switching on the pull-up
13
Table 9.74 - BSM timing sequence explanation
The valid specifications describing a BSM system allow the detection of one 'last' BSM-node per measurement
cycle.
The measurement concept used in the controller allows a detection of up to 5 BSM-nodes per cycle. As a result
the number of cycles as well as the error probability (wrong address assignment) can be decreased significantly.
9.5.6 LIN auto-configuration block description
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The LIN auto-configuration block consists of 3 major parts that needs to be controlled or calibrated:



Current generator
2-stage continuous time SC-amplifier
Shunt resistor between LIN_IN & LIN_OUT
To make the software handling easier example code for the LIN Auto-configuration support will be provided by
Melexis.
If the application uses LINAA, Bit EN_LINAA should always be set to 1 (LIN auto-config block enabled) after IC
is started.
# control signals
A
D
C
MCU
M
U
X
10bit
DAC
SAR ADC
LIN AA block
LIN_OUT
LIN_IN
Figure 9-63: LIN auto-configuration block diagram.
9.5.6.1 Current generator
The current generator principle is based on the re-use of the 10-bit DAC of the implemented SAR ADC. The
DAC voltage can be stored in a sample & hold circuitry and represents the input value of a voltage-tocurrent converter delivering an output current of maximum 2 mA. This current is applied to the LIN_IN pin
via a reverse polarity protected, high voltage current mirror with a ratio of 2. This allows LIN_IN output
currents of up to 4 mA.
Because of the high accuracy requirements for the LIN auto-configuration, the current generator has to be
calibrated in this operating mode. The calibration data for a certain current at 2 temperatures are stored in
the assigned NVM registers and can be used for the calculation of the required DAC-code.
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During the sample & hold phase (30 µs) the access to the ADC is denied. The sampled value delivers a stable
output current for maximum 500 µs referred to < 1 % current deviation over time.
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9.5.6.2 Current generator port interface
Table 9.75 shows the control signals of the current generator and the assigned port bits:
Signal description
signal name
Port name/bit
remark
Enable signal for DAC access EN_LIN_AA_DAC
in normal mode
ANA_OUTH[15]
- no input signal of current
generator
- allows access to the DAC via
ANA_OUTP[9:0]
DAC input register
ANA_OUTP[9:0]
- no input signal of current
generator
Enable signal to access on
DAC output
SWI_DAC_OUT
ANA_OUTI[5]
- no input signal of current
generator
Applies output current via
current mirror on pin
LIN_IN
CDOUTEN
ANA_OUTH[7]
- H required for LIN autoconfiguration
Enables the current
generator
CDEN
ANA_OUTH[8]
- Should be set to 1
Sample & hold clocks
SH1-SH4
ANA_OUTH[9:12]
- see timing diagram Figure 9-64
Table 9.75: Signal overview and mapping of the current generator.
The prior condition to start any current generator test activity is
 ADC reference already calibrated and values stored in NVRAM
 ADC test already done
To access the current generator in application mode (as well as for calibration during a certain test mode is
applied) the following signal sequence is required:
Step
Description
Condition
1.
enable the ADC-reference voltage of 2.5V (see 9.3.1.9 )
ADC_REF[1:0] == 11
2.
enable the access to the DAC input by the assigned registers
ANA_OUTH[15] == 1
3.
switch the DAC output to the current generator input
ANA_OUTI[5] == 1
4.
load the calculated DAC code
ANA_OUTP[9:0]
5.
in case using auto-configuration (current output LIN_IN) and
calibration of the current
ANA_OUTH[7] == 1
6.
respectively to step 4. , after 10us settling time of the DAC output
voltage, start the Sample & Hold sequence, see Figure 9-64
ANA_OUTH[9:12]
7.
enable the current generator block (recommended after S&H to
prevent output current spike)
ANA_OUTH[8] == 1
Table 9.76 auto configuration current generation sequence
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EN_LIN_AA_DAC
ó ANA_OUTH[15]
SWI_DAC_OUT
ó ANA_OUTI[5]
24us
DAC input
ó ANA_OUTP[9:0]
10us
SH1
ó ANA_OUTH[9]
10us
1us
SH2
ó ANA_OUTH[10]
1us
SH3
ó ANA_OUTH[11]
1us
SH4
ó ANA_OUTH[12]
1us
CDEN
ó ANA_OUTH[8]
Max.
500us
50us
Figure 9-64: Sequence & timing to control the current generator.
Following the sequence shown above, a stable current is available 50µs after applying the calculated DAC code.
9.5.6.3 Current generator calibration
The current generator needs to be calibrated to reach the accuracy levels required for LIN auto-configuration.
The overall accuracy has to be < +/- 10 %, where the following tolerances are included
 supply voltage dependency (Vs=8 V..18 V)
 output voltage swing (V_LIN= -1 V…4 V)
 temperature dependency (limited to TA= 0 … 50 °C for the auto-configuration)
 aging effects
The temperature dependency can be removed by software (linear approximation of the TC by using
calibration data for at least 2 temperatures).
The reserved registers in the NVRAM allow the EOL - calibration depending on pull up current value used.
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10 ESD and EMC
In order to minimize EMC influences, the PCB has to be designed according to EMC guidelines. The MLX81325 is
an ESD sensitive device and has to be handled according to the rules in IEC61340-5-2. MLX81325 will apply the
requirements in the application according to the specification and to ISO7637-2, -3.
Prototype samples of MLX81325 will be evaluated according AEC-Q100. The result will be published after
qualification. After ESD stress single parameters may be shifted out of their limit, but IC function will still be
correctly.
10.1 Automotive Qualification Test Pulses according to ISO7637-2/3
and ISO16750-2
Automotive test pulses are applied to the module in the application environment and not to the single IC.
Therefore attention must be taken, that only protected pins (protection by means of the IC itself or by means of
external components) are wired to a module connector. In the recommended application diagrams, the reverse
polarity diode together with the capacitors on supply pins and the load dump protected IC itself will help to
protect the module against the below listed automotive test pulses. The exact value of the capacitors for the
application has to be figured out during design-in of the product according to the automotive requirements.
For the LIN pin the specification “LIN Physical Layer Spec 2.1 (Nov. 24, 2006)” is valid.
Supply Pin VS is protected via the reverse polarity diode and the supply capacitors. No damage will occur for
defined test pulses. A deviation of characteristics is allowed during pulse 1 and 2; but the module will recover to
the normal function after the pulse without any additional action. During test pulse 3a, 3b, 5 the module will
work within characteristic limits.
10.1.1
Parameter
Test Pulses on Supply Lines (directly connected to Car Battery)
Symbol
Min
Max
Dim
Coupling
test condition,
functional status
Transient test pulses according to ISO7637-2 (supply lines) , VS=13.5V, TA=(23 5)°C
& (Document: “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications”;
Audi, BMW, Daimler, Porsche, VW; 2009-12-02)
Test pulse #1
vpulse1
Test pulse #2
vpulse2
Test pulse #3a
vpulse3a
Test pulse #3b
vpulse3b
-100
75
-150
100
V
Direct
5000 pulses,
functional state C
V
Direct
5000 pulses,
functional state A
V
Direct
1h,functional state A
V
Direct
1h,functional state A
Transient test pulses in according to ISO16750-2 , VS=13.5V, TA=(23 5)°C
Test pulse #5b
vpulse5b
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65
87
V
Direct
1 pulse clamped to 27V (+13V
(VS)),
(32V (+13V (VS))for applications
for north America),
functional state C
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Datasheet
10.1.2
Test Pulses on LINin and LINout Lines
Parameter
Symbol
Min
Max
Dim
Coupling
test condition,
functional status
Transient test pulses in accordance to ISO7637-3, VS=13.5V, TA=(23 5)°C
& (Document: “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications”;
Audi, BMW, Daimler, Porsche, VW; 2009-12-02)
V
Test pulse ‘DCC slow –‘
Vpulse_
slow+
Test pulse ‘DCC slow +‘
Vpulse_
slow-
Test pulse ‘DCC fast a’
Vpulse_
fast_a
Test pulse ‘DCC fast b’
Vpulse_
fast_b
-100
V
75
V
-150
V
10.1.3
100
Direct
capacitive
coupled:
1nF
1000 pulses,
functional state D
Direct
capacitive
coupled:
1nF
1000 pulses,
functional state D
Direct
capacitive
coupled:
1nF
10 min,
functional state D
Direct
capacitive
coupled:
1nF
10 min,
functional state D
Test pulses on signal lines, incl. LININ, LINOUT
Parameter
Symbol
Min
Max
Dim
Coupling
test condition,
functional status
Transient test pulses in accordance to ISO7637-3 (signal lines). VS=13.5V, TA=(23  5)°C
-30
Test pulse ‘DCC slow –‘
Vpulse_
slow-
Test pulse ‘DCC slow +‘
Vpulse_
slow+
Test pulse ‘DCC fast a’
Vpulse_
fast_a
Test pulse ‘DCC fast b’
Vpulse_
fast_b
+8
-60
10
REVISION 1.7 – 27. Apr 2020
-8
+30
-10
40
V
V
V
V
Direct
capacitive
coupled:
100nF
1000 pulses,
functional state C
Direct
capacitive
coupled:
100nF
1000 pulses,
functional state A
Direct
capacitive
coupled:
100pF
10 min,
functional state A
Direct
capacitive
coupled:
100pF
10 min,
functional state A
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Datasheet
Description of functional status
A:
B:
C:
D:
All functions of the device are performed as designed during and after the disturbance occurs.
All functions of the device are performed as designed during the disturbance occurs. One or more
functions can violate the specified tolerances. All functions return automatically within their normal
limits after the disturbance is removed.
A function of a device does not perform as designed during the disturbance occurs but returns
automatically to the normal operation after the disturbances is removed
A function of a device does not perform as designed during the disturbance occurs and does not return
automatically to the normal operation after the disturbances is removed. The device needs to be reset by
a simple operation/action to return to the specified limits/function.
10.1.4
EMC Test pulse definition
EMC Test Pulse shapes (ISO7637-2 (supply lines))
Test Pulse 1
Ri = 10 Ohm
Test pulse 2
Ri = 2 Ohm
200 ms
V
0.5...5s
< 100 µs
50 µs
V
12 V
0V
10%
t
1 µs
90%
vpulse1
vpulse2
90%
10%
12V
1 µs
2 ms
0V
t
200 ms
0.5...5s
Test Pulse 3a
Ri = 50 Ohm
Test Pulse 3b
Ri = 50 Ohm
100 ns
5 ns
V
90%
V
12V
vpulse3b
10%
0V
t
vpulse3b
vpulse3a
vpulse3a
10%
12V
0V
100 µs
10 ms
90 ms
100 µs
90%
10 ms
t
90 ms
5 ns
100 ns
Test Pulse 5b (Load Dump)
Ri = 0.5 Ohm (clamped to 45V during test)
V
Pulse 5
90%
Pulse 5 at
device
vpulse5
40V
10%
12V
t
tr = 0.1...10ms
td = 40...400ms
REVISION 1.7 – 27. Apr 2020
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Datasheet
EMC Test Pulse shapes (ISO7637-3 (non-supply lines))
Test Pulse ‘DCC slow -’
Ri = 2 Ohm
Test pulse ‘DCC slow +’
Ri = 2 Ohm
Test Pulse ‘Fast a, DCC’
Ri = 50 Ohm
Test Pulse ‘Fast b, DCC’
Ri = 50 Ohm
REVISION 1.7 – 27. Apr 2020
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Datasheet
10.1.5
Typical Application Circuitry
In order to minimize EMC influences, the external application circuitry shall be designed as followed:
D12)
VS
C22) +
Connector
C11)
C32)
VS
R12)
R22)
LIN
LIN
C41)
C52)
C61)
Actuators
Product
Signalline
Signal
-line
C71)
D21)
D31)
GND
GND
optional implemented
2) mandatory implemented
1)
10.1.5.1
External Circuitry on Supply Lines
In order to minimize EMC influences, the external application circuitry shall be designed as followed:
Name
Mounting
Min
Recommended
Max
Dim
Comment
C1
recommended
-
100
-
nF
Ceramic SMD: 10%, 0805, ≥50V;
close to the connector
D1
mandatory
C2
mandatory
1
22
100
μF
Tantal SMD: 10%, 7343, 35V
C3
mandatory
-
100
-
nF
Ceramic SMD: 10%, 0805, ≥50V;
close to the pin
REVISION 1.7 – 27. Apr 2020
Inverse-polarity protection diode
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Datasheet
10.1.5.2
External Circuitry on LIN Lines
In order to minimize EMC influences, the external application circuitry shall be designed as followed:
Name
D2
Mounting
no
Min
-
Recommended
PESD1LIN
Max
Dim
Comment
-
ESD protection Diode: SOD323
close to the connector;
optional part
C4
no
-
-
-
pF
Ceramic SMD: 10%, 0805, ≥50V;
CSlave≤ CD2+C4+C5+C6+CIC
CSlave≤250pF;
optional part
R1
mandatory
-
0
-
Ω
Serial resistor: 0805;
or optional Ferrite
C5
mandatory
-
220
-
pF
Ceramic SMD: 10%, 0805, ≥50V;
CSlave≤ CD2+C4+C5+C6+CIC
CSlave≤250pF
pF
Ceramic SMD: 10%, 0805, ≥50V;
CSlave≤ CD2+C4+C5+C6+CIC
CSlave≤250pF;
optional part
C6
10.1.5.3
no
-
-
-
External Circuitry on Signal Lines
In order to minimize EMC influences, the external application circuitry shall be designed as followed:
Name
Mounting
Min
C7
no
0.1
R2
mandatory
D3
no
REVISION 1.7 – 27. Apr 2020
Recommended
Max
Dim
Comment
1
10
0
nF
Ceramic SMD: 10%, 0805, ≥50V;
optional part
0
560
10
00
Ω
Serial resistor: 0805;
or optional Ferrite
-
PESD1LIN
-
ESD protection Diode: SOD323
close to the connector;
optional part
Page 153 of 182
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Datasheet
11 Debugging Facilities
Hardware and software debugging tools are available for the MULAN3 based products.
The description of the available tool set is not a part of this document.
12 Assembly Information
Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity
level according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)


IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
(reflow profiles according to table 2)
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)


EN60749-20
Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat
EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Iron Soldering THD’s (Through Hole Devices)

EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)

EIA/JEDEC JESD22-B102 and EN60749-21
Solderability
For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature,
temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed
upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
Melexis recommends reviewing on our web site the General Guidelines soldering recommendation
(http://www.melexis.com/Quality_soldering.aspx) as well as trim&form recommendations
(http://www.melexis.com/Assets/Trim-and-form-recommendations-5565.aspx).
REVISION 1.7 – 27. Apr 2020
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more
information on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the
use of certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality.aspx
REVISION 1.7 – 27. Apr 2020
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Datasheet
13 Contact
For the latest version of this document, go to our website at www.melexis.com.
For additional information, please contact our Direct Sales team and get help for your specific needs:
Europe, Africa
Telephone: +32 13 67 04 95
Email : sales_europe@melexis.com
Americas
Telephone: +1 603 223 2362
Email : sales_usa@melexis.com
Asia
Email : sales_asia@melexis.com
14 Disclaimer
The information furnished by Melexis herein (“Information”) is believed to be correct and accurate. Melexis disclaims (i) any and all liability
in connection with or arising out of the furnishing, performance or use of the technical data or use of the product(s) as described herein
(“Product”) (ii) any and all liability, including without limitation, special, consequential or incidental damages, and (iii) any and all
warranties, express, statutory, implied, or by description, including warranties of fitness for particular purpose, non-infringement and
merchantability. No obligation or liability shall arise or flow out of Melexis’ rendering of technical or other services.
The Information is provided "as is” and Melexis reserves the right to change the Information at any time and without notice. Therefore,
before placing orders and/or prior to designing the Product into a system, users or any third party should obtain the latest version of the
relevant information to verify that the information being relied upon is current.
Users or any third party must further determine the suitability of the Product for its application, including the level of reliability required
and determine whether it is fit for a particular purpose.
The Information is proprietary and/or confidential information of Melexis and the use thereof or anything described by the Information
does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights.
This document as well as the Product(s) may be subject to export control regulations. Please be aware that export might require a prior
authorization from competent authorities.
The Product(s) are intended for use in normal commercial applications. Unless otherwise agreed upon in writing, the Product(s) are not
designed, authorized or warranted to be suitable in applications requiring extended temperature range and/or unusual environmental
requirements. High reliability applications, such as medical life-support or life-sustaining equipment are specifically not recommended by
Melexis.
The Product(s) may not be used for the following applications subject to export control regulations: the development, production,
processing, operation, maintenance, storage, recognition or proliferation of 1) chemical, biological or nuclear weapons, or for the
development, production, maintenance or storage of missiles for such weapons: 2) civil firearms, including spare parts or ammunition for
such arms; 3) defense related products, or other material for military use or for law enforcement; 4) any applications that, alone or in
combination with other goods, substances or organisms could cause serious harm to persons or goods and that can be used as a means of
violence in an armed conflict or any similar violent situation.
The Products sold by Melexis are subject to the terms and conditions as specified in the Terms of Sale, which can be found
at https://www.melexis.com/en/legal/terms-and-conditions.
This document supersedes and replaces all prior information regarding the Product(s) and/or previous versions of this document.
Melexis NV © - No part of this document may be reproduced without the prior written consent of Melexis. (2016)
ISO/TS 16949 and ISO14001 Certified
REVISION 1.7 – 27. Apr 2020
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Datasheet
15 Appendix
15.1 Detailed Ports Map
CONTROL
0x2000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
WD_BOOT
EE_WE
OUTC_WE
OUTB_WE
OUTA_WE
MUTEX_SHE
HALT
M4_RB
Access
R-O
R/W
R/W
R/W
R/W
R/W
W-O
R/W
POR
0
0
0
0
0
0
0
0
Bit 1
Bit 0
M4_RB: 0b0 = Reset MLX4, 0b1 = Start MLX4
HALT: 0b0 = MLX16 active, 0b1 = MLX16 is Halted (only if M4_RB = ‘1’) or chip enters deep-sleep (only if M4_RB = ‘0’)
MUTEX_SHE
OUTA_WE: 0b0 = ANA_OUTA is protected against write-access, 0b1 = ANA_OUTA can be written.
OUTA_WE: 0b0 = ANA_OUTB is protected against write-access, 0b1 = ANA_OUTB can be written.
OUTA_WE: 0b0 = ANA_OUTC is protected against write-access, 0b1 = ANA_OUTC can be written.
EE_WE: 0b0 = NVRAM is protected against write access, 0b1 = NVRAM can be written
WD_BOOT: 0b0 = Chip not reset due to (Digital) Watchdog reset, 0b1 = Chip reset due to (Digital) Watchdog reset
EEPROM
0x2001
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Name
EE_BUSY
EE_CPTEST
EE_VEE1
EE_VEE0
EE_TEST
EE_DMA
Access
R-O
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
EE_CTL
R/W
0
0
EE_CTL : 0b00 = Write, 0b01 = Erase, 0b10 = Block-Write, 0b11 = Block-Erase
SHRAM
0x2002
Bit 15-8
Bit 7-0
Name
SHRAM_H
SHRAM_L
Access
R/W
R/W
POR
0
0
SHRAM_L: MLX4 shared + MLX4 private RAM size
SHRAM_H: (RAM-size – MLX4 private RAM size)/16
PRIO
0x2004
Bit 15-14
Bit 13-12
Bit 11-10
Bit 9-8
Bit 7-6
Bit 5-4
Bit 3-2
Bit 1-0
Name
EXT4
EXT3
EXT2
EXT1
EXT0
EE
ADC
TIMER
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
xx
xx
xx
xx
xx
xx
xx
xx
Bit 1
Bit 0
TIMER: IRQ priority of CoreTimer 0b00 (Prio 3) thru 0b11 (Prio 6)
ADC: IRQ priority of ADC-end-of-conversion 0b00 (Prio 3) thru 0b11 (Prio 6)
EE: IRQ priority of NVRAM Erase/Write finish 0b00 (Prio 3) thru 0b11 (Prio 6)
EXT0-EXT4: IRQ priority of EXT0 thru EXT4 (Timer #1, Timer #2, PWM, SPI, Diagnostics and I/O) 0b00 (Prio 3) thru 0b11 (Prio 6)
MASK
0x2006
Bit 7
REVISION 1.7 – 27. Apr 2020
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
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0x2006
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
EN_EE_IT
EN_ADC_IT
EN_TIMER _IT
EN_M4_ SHE_IT
EN_M4_
MUTEX_IT
EN_WD_ ATT_IT
EN_TASK
_RST_IT
EN_EXCH
ANGE_IT
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0x2007
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
Reserved
Reserved
EN_SOFT _IT
EX_EXT4 _IT
EN_EXT3 _IT
EN_EXT2 _IT
EN_EXT1 _IT
EN_EXT0 _IT
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Each bit: If cleared, the (first level) peripheral interrupt is disabled, if set, the (first level) peripheral interrupt is enabled
PEND
0x2008
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CLR_EE _IT
CLR_ADC _IT
CLR_TIMER _IT
CLR_M4
_SHE_IT
CLR_M4_
MUTEX_IT
CLR_WD
_ATT_IT
CLR_TASK
_RST_IT
CLR_EXCH
ANGE_IT
Access
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
POR
0
0
0
0
0
0
0
0
0x2009
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
Reserved
Reserved
CLR_SOFT _IT
CLR_EXT4 _IT
CLR_EXT3 _IT
CLR_EXT2 _IT
CLR_EXT1 _IT
CLR_EXT0 _IT
Access
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
POR
0
0
0
0
0
0
0
0
Each bit when set, clears the (first level) pending interrupt of the peripheral.
M4IF
0x200A
Bit 15-8
Bit 7-0
Name
SLVIT
SLVCMD
Access
R/W
R/W
POR
0x00
xx
SLVCMD:
SLVIT:
PATCH0_I
0x200C
Bit 15-0
Name
PATCH0_I
Access
R/W
POR
xxxx
PATCH0_I: A 16-bit instruction to be executed when PATCH0 is enabled and MLX16 address is equal to PATCH0-address specified in PATCH0_A
PATCH1_I
0x200E
Bit 15-0
Name
PATCH1_I
Access
R/W
POR
xxxx
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Datasheet
PATCH1_I: A 16-bit instruction to be executed when PATCH1 is enabled and MLX16 address is equal to PATCH1-address specified in PATCH1_A
PATCH2_I
0x2010
Bit 15-0
Name
PATCH2_I
Access
R/W
POR
xxxx
PATCH2_I: A 16-bit instruction to be executed when PATCH2 is enabled and MLX16 address is equal to PATCH2-address specified in PATCH2_A
PATCH3_I
0x2012
Bit 15-0
Name
PATCH3_I
Access
R/W
POR
xxxx
PATCH3_I: A 16-bit instruction to be executed when PATCH3 is enabled and MLX16 address is equal to PATCH3-address specified in PATCH3_A
PATCH0_A
0x2014
Bit 15-1
Bit 0
Name
PATCH0_A
P0_ENA
Access
R/W
R/W
POR
xxxx
0
P0_ENA: 0b0 = Patch #0 is disabled, 0b1 = Patch #0 is enabled
PATCH0_A = Patch #0 (ROM) address, subtracted by (ROM) begin-address.
PATCH1_A
0x2016
Bit 15-1
Bit 0
Name
PATCH1_A
P1_ENA
Access
R/W
R/W
POR
xxxx
0
P1_ENA: 0b0 = Patch #1 is disabled, 0b1 = Patch #1 is enabled
PATCH1_A = Patch #1 (ROM) address, subtracted by (ROM) begin-address.
PATCH2_A
0x2018
Bit 15-1
Bit 0
Name
PATCH2_A
P2_ENA
Access
R/W
R/W
POR
xxxx
0
0x201A
Bit 15-1
Bit 0
Name
PATCH3_A
P3_ENA
P2_ENA: 0b0 = Patch #2 is disabled, 0b1 = Patch #2 is enabled
PATCH2_A = Patch #2 (ROM) address, subtracted by (ROM) begin-address.
PATCH3_A
REVISION 1.7 – 27. Apr 2020
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Datasheet
0x201A
Bit 15-1
Bit 0
Access
R/W
R/W
POR
xxxx
0
P3_ENA: 0b0 = Patch #3 is disabled, 0b1 = Patch #3 is enabled
PATCH3_A = Patch #3 (ROM) address, subtracted by (ROM) begin-address.
ANA_OUTA
0x201C
Bit 7
Bit 6
Name
Access
Bit 5
Bit 4
Bit 3
TRIMCPHS[2:0]
R/W
Bit 2
Bit 1
TRIMCPOSC[2:0]
Bit 0
TRIMCURS[1:0]
R/W
POR
0
0
0
0
0
0
0
0
0x201D
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
TRIM_RCF
Access
R/W
POR
0
Reserved
TRIMCPHS[3]
R/W
0
0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
TRIM_RCF: Trim bit for VS RC filter cut off frequency
TRIMCPHS[3:0]
HS charge pump trimming
TRIMCURS[1:0]
current sensor comparator trimming
TRIMCPOSC[1:0]
charge pump oscillator trimming
ANA_OUTB
0x201E
Bit 7
Bit 6
Bit 5
Name
TR_BIAS[1:0]
TR_1V8V[2:0]
TR_VDDA[2:0]
Access
R/W
R/W
R/W
Bit 0
POR
0
0
0
0
0
0
0
0
0x201F
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
Name
TR_BG[3:0]
TR_BIAS[5:2]
Access
R/W
R/W
POR
0
0
0
0
0
0
ANA_OUTB: Chip initialization register. Should be written during power-on sequence with stored value from NVRAM, before PLL start-up.
TR_VDDA[2:0]: Trim bits for 3.3V supply
TR_V1V8[2:0]: Trim bits for 1.8V supply
TR_BIAS[5:0]: Trim bits for bias
TR_BG[3:0]: Trim bits for band-gap
ANA_OUTC
0x2020
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Name
TR_PLL[7:0]
Access
R/W
Bit 2
Bit 1
Bit 0
POR
0
0
0
0
0
0
0
0
0x2021
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
Name
EXT_CE_SELB
TR_RCO[6:0]
Access
R/W
R/W
POR
0
REVISION 1.7 – 27. Apr 2020
0
0
0
0
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Datasheet
ANA_OUTB: Chip initialization register. Should be written during power-on sequence with stored value from NVRAM, before PLL start-up.
TR_PLL[7:0]: trim bits for PLL
TR_RCO[6:0]: trim bits for 1MHz RC oscillator
EXT_CE_SELB: select MULAN intern clock divider for 1MHz clock (set port CKTRIM[5:0] before use!!); MUST BE SET TO ‘1’.
CKTRIM
0x2029
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Name
Reserved
Reserved
CKTRIM
Access
R/W
R/W
R/W
POR
x
x
0
Bit 1
Bit 0
CKTRIM: Trim value for 1MHz clock (64 – fPLL[MHz])
XI0_MASK
0x202A
Bit 15-10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4-0
Name
Reserved
EN_T1 _INT1
EN_T1 _INT5
EN_T1 _INT2
EN_T1 _INT4
EN_T1 _INT3
Reserved
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
EN_T1_INT1: Timer 1 Capture A interrupt
EN_T1_INT2: Timer 1 Compare A interrupt
EN_T1_INT3: Timer 1 Overflow interrupt
EN_T1_INT4: Timer 1 Compare B interrupt
EN_T1_INT5: Timer 1 Capture B interrupt
XI1_MASK
0x202C
Bit 15-10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4-0
Name
Reserved
EN_T2 _INT1
EN_T2 _INT5
EN_T2 _INT2
EN_T2 _INT4
EN_T2 _INT3
Reserved
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
EN_T2_INT1: Timer 2 Capture A interrupt
EN_T2_INT2: Timer 2 Compare A interrupt
EN_T2_INT3: Timer 2 Overflow interrupt
EN_T2_INT4: Timer 2 Compare B interrupt
EN_T2_INT5: Timer 2 Capture B interrupt
XI2_MASK
0x202F
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
PWM1 _CPMI
PWM1 _CNTI
PWM2 _CMPI
PWM2 _CNTI
PWM3 _CPMI
PWM3 _CNTI
PWM4 _CMPI
PWM4 _CNTI
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0x202E
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PWM5 _CPMI
PWM5 _CNTI
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
PWM[1:5]_CMPI: PWMn compare interrupt mask
PWM[1:5]_CNTI: PWMn counter interrupt mask
REVISION 1.7 – 27. Apr 2020
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
XI3_MASK
0x2030
Bit 15
Bit 14
Bit 13-0
Name
SPI1_RI
SPI1_TI
Reserved
Access
R/W
R/W
R/W
POR
0
0
0
SPI1_TI: SPI 1 transmit interrupt
SPI1_RI: SPI 1 receive interrupt
XI4_MASK
0x2033
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
XI4_OVT
XI4_UV
XI4_OV
XI4_PLL_INT
XI4_OC_DRV
XI4_VDS_MON
Reserved
XI4_LIN_RX_INT
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0x2032
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
XI4_IO7
XI4_IO6
XI4_IO5
XI4_IO4
XI4_IO3
XI4_IO2
XI4_IO1
XI4_IO0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
XI4_OVT: Diagnostics Over-temperature interrupt mask bit
XI4_UV: Diagnostics Under-voltage interrupt mask bit
XI4_OV: Diagnostics Over-voltage interrupt mask bit
XI4_PLL_INT: Diagnostics PLL interrupt (Enabled PLL-clock: Change from locked to un-locked state) mask bit
XI4_OC_DRV: Diagnostics Over-current driver interrupt mask bit
XI4_VDS_MON: Diagnostics HS D-S-Voltage monitor interrupt mask bit
XI4_LIN_RX_INT: LIN RX interrupt mask bit
XI4_IO[7:0: IO[7..0] interrupt mask bit
XI0_PEND
0x2034
Bit 15-10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4-0
Name
Reserved
CLR_T1 _INT1
CLR_T1 _INT5
CLR_T1 _INT2
CLR_T1 _INT4
CLR_T1 _INT3
Reserved
Access
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
POR
0
0
0
0
0
0
0
CLR_T1_INT1: Clear pending Timer 1 Capture A interrupt
CLR_T1_INT2: Clear pending Timer 1 Compare A interrupt
CLR_T1_INT3: Clear pending Timer 1 Overflow interrupt
CLR_T1_INT4: Clear pending Timer 1 Compare B interrupt
CLR_T1_INT5: Clear pending Timer 1 Capture B interrupt
XI1_PEND
0x2036
Bit 15-10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4-0
Name
Reserved
CLR_T2 _INT1
CLR_T2 _INT5
CLR_T2 _INT2
CLR_T2 _INT4
CLR_T2 _INT3
Reserved
Access
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
POR
0
0
0
0
0
0
0
REVISION 1.7 – 27. Apr 2020
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
CLR_T2_INT1: Clear pending Timer 2 Capture A interrupt
CLR_T2_INT2: Clear pending Timer 2 Compare A interrupt
CLR_T2_INT3: Clear pending Timer 2 Overflow interrupt
CLR_T2_INT4: Clear pending Timer 2 Compare B interrupt
CLR_T2_INT5: Clear pending Timer 2 Capture B interrupt
XI2_PEND
0x2039
Name
Access
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
C_PWM1 _CPMI C_PWM1 _CNTI C_PWM2 _CMPI C_PWM2 _CNTI C_PWM3 _CPMI C_PWM3 _CNTI C_PWM4 _CMPI C_PWM4 _CNTI
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
POR
0
0
0
0
0
0
0
0
0x2038
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Access
Name
C_PWM5 _CPMI C_PWM5 _CNTI
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
POR
0
0
0
0
0
0
0
0
C_PWM1_CMPI, C_PWM2_CMPI, C_PWM3_CMPI, C_PWM4_CMPI, C_PWM5_CMPI: Clear pending PWMn compare interrupt
C_PWM1_CNTI, C_PWM2_CNTI, C_PWM3_CNTI, C_PWM4_CNTI, C_PWM5_CNTI: Clear pending PWMn counter interrupt
XI3_PEND
0x203A
Bit 15
Bit 14
Bit 13-0
Name
C_SPI1_RI
C_SPI1_TI
Reserved
Access
R/W-C
R/W-C
R/W-C
POR
0
0
0
C_SPI1_TI: Clear pending SPI 1 transmit interrupt
C_SPI1_RI: Clear pending SPI 1 receive interrupt
XI4_PEND
0x203D
Bit 15
Bit 14
Bit 13
Bit 12
Name
C_XI4_OVT
C_XI4_UV
C_XI4_OV
C_XI4_PLL_INT
Bit 11
Access
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
POR
0
0
0
0
0
Bit 10
Bit 9
Bit 8
Reserved
C_XI4_LIN_RX_INT
R/W-C
R/W-C
R/W-C
0
0
0
C_XI4_OC_DRV C_XI4_VDS_MON
0x203C
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
C_XI4_IO7
C_XI4_IO6
C_XI4_IO5
C_XI4_IO4
C_XI4_IO3
C_XI4_IO2
C_XI4_IO1
C_XI4_IO0
Access
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
R/W-C
POR
0
0
0
0
0
0
0
0
C_XI4_OVT: Clear pending Diagnostics Over-temperature interrupt
C_XI4_UV: Clear pending Diagnostics Under-voltage interrupt
C_XI4_OV: Clear pending Diagnostics Over-voltage interrupt
C_XI4_PLL_INT: Clear pending Diagnostics PLL interrupt
C_XI4_OC_DRV: Clear pending Diagnostics Over-current driver interrupt
C_XI4_VDS_MON: Clear pending Diagnostics HS D-S-Voltage monitor interrupt
C_XI4_LIN_RX_INT: Clear pending LIN RX interrupt
C_XI4_IO[7:0: Clear pending IO[7..0] interrupt
REVISION 1.7 – 27. Apr 2020
Page 163 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
PLL_CTRL
0x203F
Bit 15-8
Name
PLL_FBDIV
Access
R/W
POR
00
0x203E
Bit 7-4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PLL_CTLCK
PLL_ SELXTAL
PLL_ XTALON
Reserved
PLL_EN
Access
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
PLL_EN: Enable PLL
PLL_XTALON: Start Crystal oscillator (reserved)
PLL_SELXTAL: Select crystal oscillator as PLL source (reserved)
PLL_CTLCK: Lock control bits, default locking 0b0000
PLL_FBDIV: PLL Feedback divider setting as: PLL-Frequency = 250kHz * (PLL_FBDIV + 1)
PLL_STAT
0x2040
Bit 15-2
Bit 1
Bit 0
Name
Reserved
PLL_CM
PLL_LOCKED
R/W-C
R-O
0
0
Access
POR
0
PLL_LOCKED: PLL has locked at high frequency (1)
PLL_CM: Clock monitor error bit. Write 1 to clear the clock monitor error flag
LIN_XKEY
0x2042
Bit 15-1
Bit 0
Name
LIN_XKEY
LIN_XKEY _VALID
Access
R-O
POR
0
0
LIN_XKEY_VALID: LIN_XKEY is valid (1)
LIN_XKEY: Enable LIN_XCFG port (0x5F0A)
ANA_OUTD
0x204A
Bit 15
Name
Reserved
Bit 14
Bit 13
Bit 12
Access
R/W
R/W
R/W
R/W
POR
0
0
0
0
0x202E
Bit 7
Bit 6
Bit 5
Bit 4
Name
Reserved
Access
R/W
R/W
R/W
R/W
POR
0
0
0
0
Bit 11
Bit 10
Bit 9
Bit 8
R/W
R/W
R/W
R/W
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
0
0
0
0
TR_ADCREF2
TR_ADCREF1
ANA_OUTD: Chip initialization register. Should be written during power-on sequence with stored value from NVRAM
ANA_OUTE
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
0x204C
Bit 15
Name
Access
Bit 14
Bit 13
Bit 12
Bit 11
R/W
R/W
R/W
R/W
ADCFREQ
R/W
Bit 10
Bit 9
Bit 8
R/W
R/W
R/W
Reserved
POR
0
0
0
0
0
0
0
0
0x202E
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Access
R/W
R/W
R/W
R/W
TR_ADCREF3
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 10
Bit 9
Bit 8
R/W
R/W
R/W
ANA_OUTE: Chip initialization register. Should be written during power-on sequence with stored value from NVRAM
ANA_OUTF
0x204F
Bit 15
Bit 14
Bit 13
R/W
R/W
R/W
Bit 12
Name
Access
Bit 11
DIS _PMOS_EXTIO[7:0]
R/W
R/W
POR
0
0
0
0
0
0
0
0
0x204E
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Name
ENABLE_EXTIO[7:0]
ENABLE_EXTIO[&:0]: Enable IO7…0
DIS_PMOS_EXTIO[7:0] : Disable PMOS of IO7 … 0
VARIOUS
0x2800
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
WKUP
PHI STAT1
PHI STAT0
EXTMEM
Reserved
SWI
Access
R-O
R-O
R-O
R-O
R-O
R-O
POR
-
-
-
-
-
-
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
W-O
SWI: Software interrupt request (automatically cleared)
PHISTAT0: LIN physical status (bit 0)
PHISTAT1: LIN physical status (bit 1)
WKUP: LIN wake-up
WDCTRL low byte
0x2802
Bit 7
Bit 6
Name
WD_T
Access
W/R
POR
0x00
WD_T: (Digital) Watchdog Time-out value.
WDCTRL high byte
0x2803
Bit 7
Bit 6
Bit 5
Bit 4
Name
WD_ERR
WD_WND
WD_MODE
Access
R-O
R-O
R/W
POR
0
0
00
REVISION 1.7 – 27. Apr 2020
WD_DIV
R/W
0
0
00
Page 165 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
WD_DIV: Watchdog (1MHz) timer divider: 0b00 = Division by 8, 0b01 = Division by 32, 0b10 = Division by 128, b0b11 = Division by 512
WD_MODE: 0b00 = Disabled, 0b01 = Timer watchdog, 0b10 = Window watchdog, 0b11 = Intelligent watchdog timer. The watchdog-mode can only be set
once after power-on/reset of the chip.
WD_WND: Acknowledge window is open (only in: Window watchdog mode)
WD_ERR: Watchdog access error (read and clear)
WTG
0x2804
Bit 7
Bit 6
Bit 5
Bit 4
Name
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
WD_TG
Access
W/R
POR
0x00
WD_TG: Watchdog Tag register, only valid in intelligent watchdog mode
XIN
0x2805
Bit 7
Bit 6
Bit 5
Bit 4
Name
XIN
Access
R-O
POR
xx
XIN: External input; Bit 0 = IO[0], Bit 1 = IO[1], Bit 2 = IO[2], etc.
TIMER
0x2806
Bit 15
Bit 14-0
Name
T_EN
T_VAL
Access
R/W
R/W
POR
0
0
T_EN: 0b0 = Timer disabled, 0b1 = Timer enabled
T_VAL = (W) Timer periodic period, based on 1MHz clock; (R) = Timer period left
ADC_CTRL
0x2811
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
ADC_EOC
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADC_SOFT
_TRIG
Access
R-O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0x2810
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
ADC_SYNC
_SOC
Reserved
ADC_ OVFM
ADC_OVF
Reserved
ADC_LOOP
ADC_TRIG _SRC
ADC_ START
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
REVISION 1.7 – 27. Apr 2020
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
ADC_START: 0b0 = ADC Stopped, 0b1 = ADC start
ADC_TRIG_SRC: 0b0 = Software trigger mode, 0b1 = Hardware trigger mode
ADC_LOOP: 0b0 = Single conversion cycle, though all channels (table-entries); 0b1 = Permanent conversion
ADC_OVF: ADC overflow of last converted channel
ADC_OVFM: ADC overflow memorized
ADC_SYNC_SOC: 0b0 = Do not discard first conversion; 0b1 = Discard first conversion
ADC_SOFT_TRIG: 0b1 = Start next channel conversion (cleared when conversion is started)
ADC_EOC: End-of-conversion.
ADC_SBASE
0x2812
Bit 15-0
Name
ADC_SBASE
Access
R/W
POR
xxxx
ADC_SBASE: ADC Source base (pointer); A table with channel, trigger and ADC reference. See ADC chapter.
ADC_DBASE
0x2814
Bit 15-0
Name
ADC_DBASE
Access
R/W
POR
xxxx
ADC_DBASE: ADC Data base (pointer); Pointer to RAM to store sampled ADC channel
AWD_CTRL
0x281B
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Name
AWD_RST
AWD_ATT
AWD_
WRITE_FAIL
AWD_TF
Reserved
Reserved
AWD_CKDIV
Access
R-O
R/W-C
R/W-C
R
R/W
R/W
R/W
POR
0
0
0
0
X
X
00
0x281A
Bit 7-0
Name
AWD_TIMER
Access
R/W
POR
0x00
Bit 9
Bit 8
AWD_TIMER: Analogue Watchdog Timer value
AWD_CKDIV: Analogue Watchdog divider: 0b00 = Div-64; 0b01 = Div-16; 0b10 = Div-4; 0b00 = Div-1
AWD_TF: This flag shows, that the data transfer to the AWD_CK clock domain is still ongoing; could be used for polling before next write; read only
AWD_WRITE_FAIL: this flag is set, when the data written from the CPU could not be transferred to the AWD_CK clock domain properly
Read/Write , cleared by POR or WAKE UP or write with 0
AWD_ATT: Watchdog info flag, memorizes a watchdog attention interrupt Read/Write , cleared by POR or WAKE UP or write with 0 twice (time between the
two writes must be at least two periods of AWD_CK or use flag AWD_TF)
AWD_RST: Watchdog reset flag, memorizes an analogue watchdog reset. Cleared by POR or WAKE UP or write 0
REVISION 1.7 – 27. Apr 2020
Page 167 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
ANA_INA
0x281D
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
OVT
UV_VS
OV_VS
PLL_INT
OC_DRV
VDS_MON
LIN_RX
LIN_RX_INT
Access
R-O
R-O
R-O
R-O
R-O
R-O
R-O
R-O
POR
x
x
x
x
x
x
x
x
0x281C
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
IOINT7
IOINT6
IOINT_5
IOINT_4
IOINT_3
IOINT_2
IOINT_1
IOINT_0
Access
R-O
R-O
R-O
R-O
R-O
R-O
R-O
R-O
POR
x
x
x
x
x
x
x
x
IOINT0, IOINT1, IOINT_2, IOINT_3, IOINT_4, IOINT_5: I/O[0] … IO[5] interrupt flag (read the according XI4PEND bit for pin status)
IOINT[7:6]: I/O[7:6] interrupt flag ((read the according XI4PEND bit for pin status)
LIN_RX: LIN-pin state read back
LIN_RX_INT : LIN RX interrupt flag
VDS_MON : Diagnostics - drain source voltage monitor for extern HS driver
OC_DRV: Diagnostics Over Current Driver state
OV_VS: Diagnostics Over Voltage Vs state
UV_VS: Diagnostics Under Voltage Vs state
OVT: Diagnostics Chip Over Temperature state
ANA_INB
0x281F
Bit 15
Bit 14
Bit 13
Bit 12
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 11
INTERNAL _WU
Bit 10
LOCAL _WU
Bit 9
LIN_WU
Bit 8
Access
R-O
R-O
R-O
R-O
R-O
R-O
R-O
R-O
POR
x
x
x
x
x
x
x
x
0x281E
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Access
R-O
R-O
R-O
R-O
R-O
R-O
R-O
R-O
POR
x
x
x
x
x
x
x
x
INTERNAL_WU : wake up from internal wake up counter
LOCAL_WU : wake up from IO3
LIN_WU : wake up from LIN bus activity
LIN_XCFG
0x2821
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LIN_XPHY
_ACTIVE
LIN_XPRO
_ACTIVE
Access
R/W
R/W
R/W
R/W
R/W
R/W
R-O
R-O
POR
x
x
x
x
x
x
x
x
0x2820
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SLEEPB _LIN
LSM
HSM
BYPASS
LIN_ XOUTINV
DISTERM
LIN_EN _XPHY
LIN_EN _XPRO
Access
R/W
R/W
R/W
R/W
R/W
R/W
W-O
W-O
POR
0
0
0
0
0
0
0
0
REVISION 1.7 – 27. Apr 2020
Page 168 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
LIN_EN_XPRO: Enable extern protocol layer for LIN
LIN_EN_XPHY: Enable extern physical layer for LIN
DISTERM: Disable LIN pull-up resistor (1)
LIN_XOUTINV: Invert LIN output
BYPASS, HSM, LSM, SLEEPB_LIN: used in XPRO mode
LIN_XPRO_ACTIVE: LIN extern protocol activated (LIN_XKEY is ok)
LIN_XPHY_ACTIVE: LIN extern physical layer activated (LIN_XKEY is ok) IO4 = Rx, IO5 = Tx
but I’m asking, why we need to do the
TMR1_CTRL
0x282B
Bit 10
Bit 9
Bit 8
Name
TMRx_DIV
TMRx_MODE
TRMx_ ENCMP
TMRx_ OVRB
TMRx_ OVRA
Access
R/W
R/W
R/W
R/W
R/W
POR
00
000
0
0
0
0x282A
Bit 15
Bit 14
Bit 7
Bit 6
Bit 13
Bit 12
Bit 5
Bit 11
Bit 1
Bit 0
Name
TMRx_DIN
TMRx_EDG2
Bit 4
Bit 3
TMRx_EDG1
Bit 2
TMRx_ START
TMRx_ T_EBLK
Access
R/W
R/W
R/W
R/W
R/W
POR
00
00
00
0
0
TMRx_T_EBLK: Enable timer block/module
TMRx_START: Start timer
TMRx_EDG1: Edge selector for channel A: 0b00 = None; 0b01 = Falling; 0b10 = Rising; 0b11: Falling & Rising edge
TMRx_EDG2: Edge selector for channel B: 0b00 = None; 0b01 = Falling; 0b10 = Rising; 0b11: Falling & Rising edge
TMRx_DIN: De-bounce method
TMRx_OVRA: Over-run register A
TMRx_OVRB: Over-run register B
TMRx_ENCMP: Enable comparison for auto-reset of timer in dual timer compare / capture modes
TMRx_MODE: Timer mode: 0b000 = Timer mode; 0b001 = Dual timer compare; 0b010 = Dual timer capture; 0b011 = Timer capture/compare; 0b100 = Pulse
accumulator mode; 0b101 = De-bounce mode, 0b110 = PWM-mode, 0b111 = reserved
TMRx_DIV: Timer divider: 0b00 = Div-1, 0b01 = Div-16; 0b1x = Div-256
TMR1_REGB
0x282C
Bit 15-0
Name
TMR1_REGB
Access
R/W
POR
xxxx
TMR1_REGB: Timer 1 register B
TMR1_REGA
0x282E
Bit 15-0
Name
TMR1_REGA
Access
R/W
POR
xxxx
TMR1_REGA: Timer 1 register A
TMR1_CNT
0x2830
Bit 15-0
Name
TMR1_CNT
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Datasheet
0x2830
Bit 15-0
Access
R-O
POR
0x0000
TMR1_CNT: Timer 1 counter
TMR2_CTRL
0x2833
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
TMRx_DIV
TMRx_MODE
TRMx_ ENCMP
TMRx_ OVRB
TMRx_ OVRA
Access
R/W
R/W
R/W
R/W
R/W
POR
0x2832
0
Bit 7
000
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
Bit 2
Bit 1
Bit 0
Name
TMRx_DIN
TMRx_EDG2
TMRx_EDG1
TMRx_ START
TMRx_ T_EBLK
Access
R/W
R/W
R/W
R/W
R/W
POR
00
00
00
0
0
TMRx_T_EBLK: Enable timer block/module
TMRx_START: Start timer
TMRx_EDG1: Edge selector for channel A: 0b00 = None; 0b01 = Falling; 0b10 = Rising; 0b11: Falling & Rising edge
TMRx_EDG2: Edge selector for channel B: 0b00 = None; 0b01 = Falling; 0b10 = Rising; 0b11: Falling & Rising edge
TMRx_DIN: De-bounce method
TMRx_OVRA: Over-run register A
TMRx_OVRB: Over-run register B
TMRx_ENCMP: Enable comparison for auto-reset of timer in dual timer compare / capture modes
TMRx_MODE: Timer mode: 0b000 = Timer mode; 0b001 = Dual timer compare; 0b010 = Dual timer capture; 0b011 = Timer capture/compare; 0b100 = Pulse
accumulator mode; 0b101 = De-bounce mode, 0b110 = PWM-mode, 0b111 = reserved
TMRx_DIV: Timer divider: 0b00 = Div-1, 0b01 = Div-16; 0b1x = Div-256
TMR2_REGB
0x2834
Bit 15-0
Name
TMR2_REGB
Access
R/W
POR
xxxx
TMR2_REGB: Timer 2 register B
TMR2_REGA
0x2836
Bit 15-0
Name
TMR2_REGA
Access
R/W
POR
xxxx
TMR2_REGA: Timer 2 register A
TMR2_CNT
0x2838
Bit 15-0
Name
TMR2_CNT
Access
R-O
POR
0x0000
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Datasheet
TMR2_CNT: Timer 2 counter
PWM1_CTRL
0x284A
Bit 7
Bit 6
Bit 5
Name
Reserved
Reserved
Reserved
Access
POR
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ECI
EPI
MODE
EXT
EBLK
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
EBLK: Enable PWM module
EXT: Select the internal (0) or external (1) counter
MODE: Select the PWM mode independent (0) or mirror (1)
EPI: Enable the PWM counter interrupt signal
ECI: Enable the PWM comparator interrupt signal
PWM1_PSCL
0x284B
Bit 7-0
Name
PWM1_PSCL
Access
R/W
POR
xx
PWM1_PSCL: PWM channel 1 Pre-scaler register
PWM1_PER
0x284C
Bit 15-0
Name
PWM1_PER
Access
R/W
POR
xxxx
PWM1_PER: PWM channel 1 period duration
PWM1_LT
0x284E
Bit 15-0
Name
PWM1_LT
Access
R/W
POR
xxxx
PWM1_LT: PWM channel 1 low-time threshold
PWM1_HT
0x2850
Bit 15-0
Name
PWM1_HT
Access
R/W
POR
xxxx
PWM1_HT: PWM channel 1 high-time threshold
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Datasheet
PWM1_CMP
0x2852
Bit 15-0
Name
PWM1_CMP
Access
R/W
POR
xxxx
PWM1_CMP: PWM channel 1 compare threshold to generate interrupt
PWM2_CTRL
0x2854
Bit 7
Bit 6
Bit 5
Name
Reserved
Reserved
Reserved
Access
POR
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ECI
EPI
MODE
EXT
EBLK
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
EBLK: Enable PWM module
EXT: Select the internal (0) or external (1) counter
MODE: Select the PWM mode independent (0) or mirror (1)
EPI: Enable the PWM counter interrupt signal
ECI: Enable the PWM comparator interrupt signal
PWM2_PSCL
0x2855
Bit 7-0
Name
PWM2_PSCL
Access
R/W
POR
xx
PWM2_PSCL: PWM channel 2 Pre-scaler register
PWM2_PER
0x2856
Bit 15-0
Name
PWM2_PER
Access
R/W
POR
xxxx
PWM2_PER: PWM channel 2 period duration
PWM2_LT
0x2858
Bit 15-0
Name
PWM2_LT
Access
R/W
POR
xxxx
PWM2_LT: PWM channel 2 low-time threshold
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Datasheet
PWM2_HT
0x285A
Bit 15-0
Name
PWM2_HT
Access
R/W
POR
xxxx
PWM2_HT: PWM channel 2 high-time threshold
PWM2_CMP
0x285C
Bit 15-0
Name
PWM2_CMP
Access
R/W
POR
xxxx
PWM2_CMP: PWM channel 2 compare threshold to generate interrupt
PWM3_CTRL
0x285E
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
ECI
EPI
MODE
EXT
EBLK
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Access
POR
0
0
0
EBLK: Enable PWM module
EXT: Select the internal (0) or external (1) counter
MODE: Select the PWM mode independent (0) or mirror (1)
EPI: Enable the PWM counter interrupt signal
ECI: Enable the PWM comparator interrupt signal
PWM3_PSCL
0x285F
Bit 7-0
Name
PWM3_PSCL
Access
R/W
POR
xxxx
PWM2_PSCL: PWM channel 3 Pre-scaler register
PWM3_PER
0x2860
Bit 15-0
Name
PWM3_PER
Access
R/W
POR
xxxx
PWM3_PER: PWM channel 3 period duration
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PWM3_LT
0x2862
Bit 15-0
Name
PWM3_LT
Access
R/W
POR
xxxx
PWM3_LT: PWM channel 3 low-time threshold
PWM3_HT
0x2864
Bit 15-0
Name
PWM3_HT
Access
R/W
POR
xxxx
PWM3_HT: PWM channel 3 high-time threshold
PWM3_CMP
0x2866
Bit 15-0
Name
PWM3_CMP
Access
R/W
POR
xxxx
PWM3_CMP: PWM channel 3 compare threshold to generate interrupt
PWM4_CTRL
0x2868
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
ECI
EPI
MODE
EXT
EBLK
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
POR
EBLK: Enable PWM module
EXT: Select the internal (0) or external (1) counter
MODE: Select the PWM mode independent (0) or mirror (1)
EPI: Enable the PWM counter interrupt signal
ECI: Enable the PWM comparator interrupt signal
PWM4_PSCL
0x2869
Bit 7-0
Name
PWM4_PSCL
Access
R/W
POR
xxxx
PWM4_PSCL: PWM channel 4 Pre-scaler register
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Datasheet
PWM4_PER
0x286A
Bit 15-0
Name
PWM4_PER
Access
R/W
POR
xxxx
PWM4_PER: PWM channel 4 period duration
PWM4_LT
0x286C
Bit 15-0
Name
PWM4_LT
Access
R/W
POR
xxxx
PWM4_LT: PWM channel 4 low-time threshold
PWM4_HT
0x286E
Bit 15-0
Name
PWM4_HT
Access
R/W
POR
xxxx
PWM4_HT: PWM channel 4 high-time threshold
PWM4_CMP
0x2870
Bit 15-0
Name
PWM4_CMP
Access
R/W
POR
xxxx
PWM4_CMP: PWM channel 4 compare threshold to generate interrupt
PWM5_CTRL
0x2872
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
ECI
EPI
MODE
EXT
EBLK
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
POR
EBLK: Enable PWM module
EXT: Select the internal (0) or external (1) counter
MODE: Select the PWM mode independent (0) or mirror (1)
EPI: Enable the PWM counter interrupt signal
ECI: Enable the PWM comparator interrupt signal
PWM5_PSCL
0x2873
Bit 7-0
Name
PWM5_PSCL
Access
R/W
POR
xxxx
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Datasheet
PWM5_PSCL: PWM channel 5 Pre-scaler register
PWM5_PER
0x2874
Bit 15-0
Name
PWM5_PER
Access
R/W
POR
xxxx
PWM5_PER: PWM channel 5 period duration
PWM5_LT
0x2876
Bit 15-0
Name
PWM5_LT
Access
R/W
POR
xxxx
PWM5_LT: PWM channel 5 low-time threshold
PWM5_HT
0x2878
Bit 15-0
Name
PWM5_HT
Access
R/W
POR
xxxx
PWM5_HT: PWM channel 5 high-time threshold
PWM5_CMP
0x287A
Bit 15-0
Name
PWM5_CMP
Access
R/W
POR
xxxx
PWM5_CMP: PWM channel 5 compare threshold to generate interrupt
SPI1_PCR
0x289A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SPI_RFIE
SPI_TFIE
SPI_BYTEMOD
SPI_MSTR
SPI_CPOL
SPI_CPHA
SPI_EN
SPI_CKEN
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
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SPI_CKEN: SPI clock enable
SPI_EN: SPI module enable
SPI_CPHA: Clock phase selector; 0 = transmission starts on first SPSCK edge; 1 = transmission starts on falling edge of SPISIB
SPI_CPOL: Clock polarity selector, 0 = SPSCK_OUT is low during transmission 1 = SPSCK_OUT is high during transmission
SPI_MSTR: Master mode; 0 = Slave mode; 1 = Master mode
SPI_BYTEMOD: Frame length selector; 0 = 16-bits frames; 1 = 8-bits frames
SPI_TFIE: SPI_TF interrupt
SPI_RFIE: SPI_RF interrupt
SPI1_PSCR
0x289B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SPI_RF
SPI_TF
SPI_OVRF
SPI_ MODF
SPI_ FRSSOEN
SPI_ MODFEN
SPI_
MSTRONLY
SPI_ERRIE
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
SPI_ERRIE: Error interrupt enable bit
SPI_MSTRONLY: Master transmit mode; 0 = full-duplex; 1 = transmit mode only
SPI_MODFEN: Mode Fault enable bit
SPI_FRSSOEN: Frame Slave Select Output Enable bit
SPI_MODF: Mode Fault bit
SPI_OVRF: Overflow flag
SPI_TF: Transmit full; 0 = Transmit port SPIR_DR is empty; 1 = Transmit port SPI_DR is full
SPI_RF: Receiver full; 0 = Receiver port SPIR_DR is empty; 1 = Receiver port SPI_DR is full
SPI1_BRR
0x289C
Bit 15-0
Name
SPI1_BRR
Access
R/W
POR
xxxx
SPI1_BRR: SPI Baudrate
SPI1_DR
0x289E
Bit 15-0
Name
SPI1_DR
Access
R/W
POR
xxxx
SPI1_DR: SPI Data Register
IO_CFG
0x28BE
Bit 15-9
Bit 8
Bit 7-0
Name
Reserved
LINRXIFRB
IOIFRB
Access
R/W
R/W
R/W
POR
0
0
0
ILNRXIFRB = LIN RX interrupt on rising edge (0) or falling edge(1)
IOIFRB[7:0] = I/O interrupt on rising edge (0) or falling edge (1)
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MLX81325 Smart LIN Driver for small motors <100W
Datasheet
IO_DEB
0x28C0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
IO7_DEBOUNCE
IO6_DEBOUNCE
IO5_DEBOUNCE
IO4_DEBOUNCE
Access
R/W
R/W
R/W
R/W
POR
00
0
00
00
0x28C0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
IO3_DEBOUNCE
IO2_DEBOUNCE
IO1_DEBOUNCE
IO0_DEBOUNCE
Access
R/W
R/W
R/W
R/W
POR
00
00
00
00
IO0_DEBOUNCE ... IO5_DEBOUNCE: IO[0…5] de-bounce time: 0b00 = OFF, 0b01 = 1 ms; 0b10 = 4 ms; 0b11 = 8 ms
IO6_DEBOUNCE & IO7_DEBOUNCE: IO[7:6] de-bounce time: 0b00 = OFF, 0b01 = 100us, 0b01 = 200us; 0b11 = 400us
DRVCFG_EXT
0x28C2
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
reserved
reserved
reserved
reserved
reserved
OVPM
UVPM
VDSPM
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0x20C2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
reserved
reserved
reserved
reserved
reserved
CPDRV
CS_CAL
DIS_VDS
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
CPDRV - level of CPDRV if TRIMCPOSC = 3'b100 (in ANA_OUTA[4:2])
CS_CAL - if set to 1 the current sensor is in offset calibration mode (offset can be measured at ADC)
DIS_VDS: disable VDS monitor :
0 –VDS monitor has no effect on phase pins,
1 – VDS monitor switches phase pins to ground or tristate (depending on VDSPM bit)
VDSPM: In case of VDS monitor event: 0 – phase pin switched to ground, 1 – phase pin switched to tristate
UVPM: In case of undervoltage event: 0 – phase pin switched to ground, 1 – phase pin switched to tristate
OVPM: In case of overvoltage event: 0 – phase pin switched to ground, 1 – phase pin switched to tristate
DRVCFG
0x28C6
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
DIS_OT
DIS_OC
DIS_UV
DIS_OV
OVTPM
DIS_SHOA
OCPM
DIS_DRV
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0x28C6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DRV_CFG_W
DRV_CFG_T
DRV_CFG_U
DRV_CFG_V
Access
R/W
R/W
R/W
R/W
POR
00
00
00
00
DRV_CFG_U: Motor Driver Phase U configuration: 0b00 = Tri-state; 0b01 = PWM; 0b10 = Low; 0b11 = High
DRV_CFG_V: Motor Driver Phase V configuration: 0b00 = Tri-state; 0b01 = PWM; 0b10 = Low; 0b11 = High
DRV_CFG_W: Motor Driver Phase W configuration: 0b00 = Tri-state; 0b01 = PWM; 0b10 = Low; 0b11 = High
DRV_CFG_T: Motor Driver Phase T configuration: 0b00 = Tri-state; 0b01 = PWM; 0b10 = Low; 0b11 = High
DIS_DRV: Motor driver: 0 = Enabled; 1 = Disabled
OCPM: Driver configuration at over-current: 0 = To Ground; 1 = Tri-state
DIS_SHOA: Enable (0) or Disable (1) Shunt current measurement (OpAmp for ADC measurement and overcurrent comparator)
OVTPM: Driver configuration at over-temperature: 0 = Tri-state; 1 = To Ground
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Datasheet
DIS_OV: Enable (0) or Disable (1) the Over Voltage motor driver hardware protection.
DIS_UV: Enable (0) or Disable (1) the Under Voltage motor driver hardware protection.
DIS_OC: Enable (0) or Disable (1) the Over Current motor driver hardware protection.
DIS_OT: Enable (0) or Disable (1) the Over Temperature motor driver hardware protection.
IO_WU
0x28C8
Bit 15-6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
IOWU3
Reserved
Reserved
Reserved
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
IOWU3: Enable wake-up on IO3-pin
IO_IN
0x28CA
Bit 15-8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
IO_DEB7
IO_DEB6
IO_DEB5
IO_DEB4
IO_DEB3
IO_DEB2
IO_DEB1
IO_DEB0
x
x
x
x
x
x
x
x
x
Access
POR
IO_DEB0 … IO_DEB7: Input de-bounced of IO-0 … IO-7
ANA_OUTG
0x28CD
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Name
Tvds[1:0]
DEB_OC[1:0]
Reserved
Access
R/W
R/W
R/W
POR
00
0x28CC
Bit 7
00
Bit 6
Bit 5
Bit 9
Bit 8
Bit 1
Bit 0
0000
Bit 4
Bit 3
Bit 2
Name
INACTIVE_OVT
INT_WU
T_DEAD
Reserved
DIS_GTSM
Access
R/W
R/W
R/W
R/W
R/W
POR
0
00
000
0
0
DIS_GTSM: 1: suppresses GOTO SLEEP mode request
INACTIVE_OVT: 1: inactivates overtemperature shutdown circuitry
T_DEAD[2:0]: Dead-time tDEAD = (T_DEAD + 1) * 0.4 µs
DEB_OC[1:0]: Debounce time Over-current
INT_WU: Internal Wake-up Timer: 0b00 = Disabled, 0b01: 0.41s, 0b10: 0.82s, 0b11: 1.64s (resp. 4k, 8k and 16k * 1/10kHz)
Tvds[1:0]: Top-FET VDS-monitor mask time: tVDS_MASK = (Tvds + 1) * 1.6 µs
ANA_OUTH
0x28CE
Bit 15
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
EN_LINAA_DAC
Bit 14
DIV[1:0]
Bit 13
SH4
SH3
SH2
SH1
CDEN
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
00
0
0
0
0
0
0x28CE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CDOUTEN
EN_LINAA
RST1
RST2
GAIN[3:0]
Access
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0000
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Datasheet
GAIN[3:0]: Gain of LINAA shunt measurement; 4b0000 Gain = 1, 4b0001 Gain = 2, …, 4b1111 Gain = 16
RST2: 1 – Offset calibration of LINAA shunt voltage amplifier, second stage, 0 – Normal shunt voltage measurement
RST1: 1 – Offset calibration of LINAA shunt voltage amplifier, first stage, 0 – Normal shunt voltage measurement
EN_LINAA: 1 – Enable LINAA shunt measurement and current source, 0 – LINAA block is switched off
CDEN: 1 – Enable op-amp for LINAA current source, 0 – op-amp is switched off
CDOUTEN: Connect the current DAC output to the LIN bus
SH4:1: Sample&Hold signals for LINAA current source
DIV[1:0]: Common mode suppression of LINAA shunt voltage amplifier, 2b00 – worst suppression, …, 2b11 – best suppression
EN_LINAA_DAC: 0 – DAC is in ADC mode, 1 – Output from digital to DAC is ANA_OUTP[9:0]
ANA_OUTI
0x28D0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Name
SEL_UV_VS
Reserved
Reserved
reserved
PROV
Bit 10
Bit 9
Bit 8
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0x28D0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
SWI_DAC_ OUT
VCMO_SEL_
LINAA
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 9
Bit 8
PRUV[2:0]
CALSLVTRM [1:0]
TRMISR[1:0]
TRMISR[1:0]: Calibration LIN Slew-rate
CALSLVTRM[1:0]: Calibration LIN Slave Termination pull-up resistor
VCMO_SEL_LINAA: Select VCM LINAA (default: new VCM)
SWI_DAC_OUT: Switch 10-bit DAC to LIN-AA
SEL_UV_VS: 0b0 = Enable UV and OV de-bounce circuitry; 0b1 = Disable UV and OV de-bounce circuitry
PROV : switch OV detection between 31V (=0) and 36V (=1)
PRUV[2:0] : programming the under voltage detection level
ANA_OUTK
0x28D2
Bit 15
Bit 14
Bit 13
Bit 12
Name
Reserved
Reserved
Reserved
Reserved
Bit 11
Bit 10
SEL_TX_OUT
Access
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0x28D2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0000
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
_DISTERM
_SLEEPB _LIN
_LSM
_HSM
_BYPASS
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
REVISION 1.7 – 27. Apr 2020
Page 180 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
SEL_TX_OUT: Select source for TX_OUT:
0b0000 = PWM2; 0b0001 = PWM3; 0b0010 = PWM4; 0b0011 = PWM1;
0b0100 = Timer 1 output; 0b0101 = Timer 2 output;
0b0110 = Software (ANA_OUTN bit SOFT_TX);
0b0111 = IO0-pin ; 0b1000 = IO1-pin ; 0b1001 = IO2-pin ; 0b1010 = IO3-pin ; 0b1011 = IO4-pin ; 0b1100 = IO5-pin ; 0b1101 = IO6-pin ; 0b1110 = IO7-pin
;0b1111=PWM5
ANA_OUTL
0x28D4
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Name
LIN_KEY
Access
R/W
POR
0x00
Bit 10
Bit 9
Bit 8
0x28D4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 1
Bit 0
LIN_KEY: LIN-key (0x43)
ANA_OUTM
0x28D6
Bit 15
Name
IO5_OUTCFG
IO4_OUTCFG
IO3_OUTCFG
Access
R/W
R/W
R/W
POR
0x28D6
00
Bit 7
00
Bit 6
000
Bit 5
Bit 4
Bit 3
Bit 2
Name
IO2_OUTCFG
IO1_OUTCFG
IO0_OUTCFG
Access
R/W
R/W
R/W
POR
000
000
000
IO[5:0]_OUTCFG: IO[5:0]-pin output configuration as below :
0b000 = SPI interface;
0b001 = Timer 1 output; 0b010 = Timer 2 output;
0b011 = PWM2 output; 0b100 = PWM3 output; 0b101 = PWM4 output; 0b110 = PWM1 output;
0b111 = Software (ANA_OUTN)
ANA_OUTN
0x28D8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
IO7_OUTCFG
IO6_OUTCFG
Reserved
Reserved
Reserved
SOFT_TX
Access
R/W
R/W
R/W
R/W
R/W
R/W
POR
00
00
0
0
0
0
0x28D8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SOFT_IO7
SOFT _IO6
SOFT_IO5
SOFT_IO4
SOFT_IO3
SOFT_IO2
SOFT_IO1
SOFT_IO0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
REVISION 1.7 – 27. Apr 2020
Page 181 of 182
MLX81325 Smart LIN Driver for small motors <100W
Datasheet
SOFT_IO0: IO0-pin software output
SOFT_IO1: IO1-pin software output
SOFT_IO2: IO2-pin software output
SOFT_IO3: IO3-pin software output
SOFT_IO4: IO4-pin software output
SOFT_IO5: IO5-pin software output
SOFT_IO6: IO6-pin software output
SOFT_IO7: IO7-pin software output
SOFT_TX: TX-pin software output
IO6_OUTCFG: IO6-pin output configuration: 0b00 = Reserved; 0b01 = Timer 1 output; 0b10 = Timer 2 output; 0b11 = Software (ANA_OUTN)
IO7_OUTCFG: IO7-pin output configuration: 0b00 = Reserved; 0b01 = Timer 1 output; 0b10 = Timer 2 output; 0b11 = Software (ANA_OUTN)
ANA_OUTO
0x28DA
Bit 15
Bit 14
Name
Bit 13
Bit 12
Bit 11
TMRCFG_T2_INB
Bit 10
Bit 9
Access
R/W
R/W
POR
0000
0000
0x28DA
Bit 7
Bit 6
Bit 5
Bit 8
TMRCFG_T2_INA
Bit 4
Bit 3
Bit 2
Bit 1
Name
TMRCFG_T1_INB
TMRCFG_T1_INA
Access
R/W
R/W
POR
0000
0000
Bit 0
TMRCFG_T1_INA: Timer 1 input A: See below
TMRCFG_T1_INB: Timer 1 input B: See below
TMRCFG_T2_INA: Timer 2 input A: See below
TMRCFG_T2_INB: Timer 2 input B: See below
0b0000 = IO0 de-bounced input; 0b0001 = IO1 de-bounced input; 0b0010 = IO2 de-bounced input; 0b0011 = IO3 de-bounced input; 0b0100 = IO4 de-bounced
input; 0b0101 = IO5 de-bounced input; 0b0110 = IO6 de-bounced input; 0b0111 = IO7 de-bounced input; 0b1000 = RX input
ANA_OUTP
0x28DC
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Access
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0x28DC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Name
Bit 9
Bit 1
LINAA_DACIN[7:0]
Access
POR
LINAA_DACIN[9:0]: Set current-level for LIN-AA.
REVISION 1.7 – 27. Apr 2020
Bit 8
LINAA_DACIN[9:8]
Page 182 of 182
Bit 0