VLSI Lecture series
Evolution of logic
complexity in Integrated
Circuit for information
technology services
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Evolution in logic complexity in Integrated circuits
❖ Evolution of size in Integrated services
❖ Prominent Information Technology services
❖ Features of Integrated circuits
Evolution in logic complexity in IC’s
MSI
LSI
• Medium Scale Integration
• Introduced in 1967
• Logic Block per chip 20-200
• Large Scale Integration
• Introduced in 1972
• Logic Block per chip 200-2000
VLSI
• Very Large Scale Integration
• Introduced in 1978
• Logic Block per chip 2000-20000
ULSI
• Ultra Large Scale Integration
• Introduced in 1989
• Logic Block per chip 20000 >>
Evolution of size in Integrated services
Minimum feature Size in (µm)
4.0 –
4.0
3.5 –
3.0 –
2.5 –
2.0 –
1.5 –
1.0 –
0.5 –
0.1
0.0 –
1975
1980
1985
1990
Year
1995
2000
Prominent Information Technology services
Video on Demand
Speech Processing
Wireless/Cellular Data Communication
Data Communication
Consumer Electronics
Main Frame Computer
1975
1980
Multi-media Application
Portable Computer
Personal Computer
1985
1990
Year
Computer Network
1995
2000
Features of Integrated circuits
❖ Less area/volume
❖ Less power consumption
❖ Less testing requirement at system level
❖ Higher reliability, mainly due to improved on chip interconnects
❖ Higher speed, mainly due to reduced interconnection length
❖ Significant cost savings
VLSI Lecture series
VLSI design
Methodologies
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Design Time
❖ Performance analysis versus design time
❖ Technology window
Design Time of IC
❖ Design Time of IC depends on follwing parameters
❑ Design complexity
❑ Performance level
❑ Acceptable cost
Types of design - Full custom design requires all the
components to be designed and verified right from the
transistor level. This methodology is used for mass
production and to optimize area speed and power. Semicustom design are used when there is less time for
design and for less quantities. Most of the modules are
prebuilt and pretested.Additional components can be
integrated. This saves a design time but not that
optimized and cost-efficient for mass production.
Performance analysis versus design time
Full-custom Design
longer design time
until “maturity”
Circuit Performance
Semi-custom Design
Less Opportunities
for performance
improvement
Shorter design
time until
“maturity”
Design Time
More Opportunities
for performance
improvement
Circuit Performance
Technology Window
Design
Production
Design
Production
Time
Technology Window 1
Technology Window 2
VLSI Lecture series
Semi Custom and Full
Custom design
By Prof. Hitesh Dholakiya
Engineering Funda
Full Custom Design
Semi Custom Design
1. Complete design, layout, geometry, orientation and
placement of transistor is done designer
1. Some commonly used design, layout, geometry and
placement of transistor is interfaced with given demand.
2. Entire design is made without use of any library.
2. Design is completed with the use of multiple library.
3. Development time for design before maturity is more.
3. Development time for design before maturity is less.
4. It has more opportunity for performance improvement
4. It has less opportunity for performance improvement
5. Less dependency on existing technology.
5. Complete dependency on existing technology.
6. High Cost
6. Low cost
Performance analysis versus design time
Full-custom Design
longer design time
until “maturity”
Circuit Performance
Semi-custom Design
Less Opportunities
for performance
improvement
Shorter design
time until
“maturity”
Design Time
More Opportunities
for performance
improvement
VLSI Lecture series
Semi Custom
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Semicustom design
❖ Classification of Semicustom design
❖ Working of Different Semicustom design
Basics of Semicustom design
❖ This method is used to reduce time to market.
❖ Here, we reduce cost of designing of product.
❖ Performance of semicustom design is lower then full custom design.
❖ Here, in semicustom design, we use readily available block, design,
library or modules.
Classification of Semicustom design
Semicustom Design
Standard Cell
Gate array
Programmable devices
Standard Cell
❖ Here, we use standard cell library.
❖ A typical library may contain a few hundred cells including inverters,
NAND Gates, NOR Gates, complex AOI/OAI Gates, D-Latches, FF and
Counters.
❖ In library, there are gates, with different driving capabilities, for example,
standard size, double size and quadruple size.
❖ We need to use size based on current driving capabilities and speed of
device.
❖ Designer sends the schematic to fabricator who prepares the mask if the
cells are from the library.
Advantages
❖ Larger the library, the larger the cost.
❑ Flexible design
Works with analog and digital function
❖ Standard cell guarantees that it will work. ❑
❑ Sophisticated system can be built easily
Disdvantages
❑ Mask Cost
Gate Array
❖ A Gate array circuit is a prefabricated circuit with no particular
function, in which transistors and other active devices are placed at
regular predefined positions.
❖ Only masks for metallization need to be created.
Advantages
❑ Reduces the mask cost
❑ Less time to market
Disadvantages
❑ Size is fixed
❑ Number of transistor are fixed
❑ Metal height is fix
❑ 2 metal layer are possible
❑ Low efficiency
❑ Suitable for low production volume
Programmable Logic Devices (PLD)
❖ There are variety of IC available in the market that could be
programmed according to specification.
❖ Some architecture are listed here
❑ SPLD – Simple Programmable logical device
❑ CPLD – Complex programmable logical device
❑ FPGA – Field programmable Gate Array
VLSI Lecture series
Hierarchy, Regularity,
Modularity & Locality
By Prof. Hitesh Dholakiya
Engineering Funda
Hierarchy
❖ It involves dividing complex design into various modules and
submodules.
❖ This division is done until the complexity of submodules is at an
understandable level of details.
Regularity
❖ Here designer divides the hierarchy into sets of similar building
blocks.
❖ Regularity is the design of array structures consisting of identical
cells.
❖ Regularity can be there at many levels,
❑ At transistor level
❑ At identical GATE level
❑ At micro block
❑ At macro block
Modularity
❖ Modularity means various functional blocks has well defined
functions and interfaces, so that, they can be implemented and
tested separately.
❖ All the blocks can be combined easily at the end of the design
process to form large system.
Locality
❖ Locality ensures that the internals of modules are not visible to any
exterior interface.
❖ This enables the outside world to treat each module as a block box
with well defined inputs and outputs.
VLSI Lecture series
Package Technology
in IC
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Through hole Package
❖ Surface Mount Package
❖ Contactless Package
Through Hole Package
❖ One or more leads go through holes of PCB and are soldered
underneath.
❖ Packages are made from either plastic or ceramic.
❖ In though hole package, mainly there three categories
1. SIP (Single In line Package)
2. DIP (Dual In line Package)
3. PGA (Pin Grid Array)
SIP (Single In line Package)
❖ IC package having single row of leads is SIP (Single In line Package)
❖ It has less number of leads in single raw.
DIP (Dual In line Package)
❖ IC package having two rows of leads is DIP (Dual In line Package)
❖ DIP’s are mostly used in educational institutes.
PGA (Package Grid Array)
❖ IC package having grid arrangement of leads, is PGA
❖ They offers more number of leads (at max 400 pins).
❖ It is better than DIP’s in terms of thermal conductivity and power
dissipation characteristics.
Surface Mount Package
❖ Unlike through hole package, the leads of surface mount packages are
mounted directly on the surface of PCB.
❖ They do not go through holes or fit into a socket.
❖ Normally, leads of Surface Mount Package is bent at an angle near foot to
aid soldering to the surface of PCB.
❖ BGA (Ball Grid Array)
❑ It has metal balls
❑ It does not have solderable leads,
❑ By little pressure we can fix it on PCB
❑ It has many terminals (56 to 1312)
❑ It can have packaging from multiple side (one to four sides)
Contactless Package
❖ It does not have physical contact with PCB.
❖ It does not have any leads.
❖ It provides information wirelessly.
VLSI Lecture series
VLSI Design Flow
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of VLSI Design flow
❖ Flow Chart of VLSI Design flow
❖ Domains of VLSI Design flow
❖ Y chart of VLSI Design flow
Basics of VLSI Design Flow
❖ The design flow start with a given set of specification or
requirements.
❖ So, system should get design with respect to given specifications.
❖ At the end, when the desired specifications are not met, the design
has to be modified and re-checked several times until it meets the
required specifications.
Flow Chart of VLSI Design Flow
Design Specification
HDL Coding
Architecture design
Simulation
Gate level design
Verification
Circuit level design
Meets
Yes
Fabrication
No
Domains of VLSI Design Flow
❖ The design description for a VLSI circuit may be described in forms of
three domains:
1. Behavioral Domain
2. Structural Domain
3. Physical Domain
Y Chart of VLSI Design
Structural
Domain
System
Behavior
Domain
Algorithm
Finite State
Machine
Module
Description
Boolean
Equation
Register
Logic Gate
Transistor
Mask
Cell placement
Modules
placement
Chip Floor plan
Physical Domain
VLSI Lecture series
Importance CAD tool
in VLSI design
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of CAD tool in VLSI design
❖ IC design process
❖ IC fabrication process
❖ Important feature of CAD tools in VLSI design
Basics of CAD tools in VLSI design flow
❖ As per Moore’s Law, complexity of IC’s is increasing over the years.
❖ Designing of VLSI circuit with millions of transistor in single IC is
beyond humans brain.
❖ To design VLSI circuit, Computer is required to check layout, circuit
performance, process etc.
❖ Computer are used to aid in the design and optimization process.
❖ VLSI designers are normally given a set of design rules based on
given technology.
IC design process and IC fabrication process
Pattern file
Design Entry
Produce mask
Design Verification,
DRC, Simulation etc.
Pattern Generator
For each layer wafer
processing, deposit,
expose, develop etch
etc.
Package
Test
Feature of VLSI CAD tools
❖VLSI CAD tools have following tools to meet design features:
1. Physical design (Layout, editor, circuit schematics)
2. Physical verification (DRC (design Rule Check), circuit extractor, plot output,
visual checking)
3. Behavioral verification.
VLSI Lecture series
Comparison of FPGA
and CPLD
By Prof. Hitesh Dholakiya
Engineering Funda
Comparison of FPGA and CPLD
FPGA
Parameters
CPLD
1. Full Form
1. Field Programable Gate Array
1. Complex Programable Logic Design
2. Architecture
2. Based on “Look up table”
2. Based on “Logic Function”
3. Blocks in Architecture
3. Around 100000
3. Few blocks
4. Architecture tuning
4. Fine Grain Devices
4. Course Grain Devices
5. Architectural Memory
5. SRAM
5. EPROM
6. Complexity
6. High
6. Less
7. Cost
7. High
7. Less
8. Time to ON
8. It takes time to load program
8. Instant ON
9. Volatility of Program
9. Program lost once power is OFF
9. Program stays in CPLD
10. Power Consumption
10. Ideal Power Consumption
10. Weaker Power Consumption
11. Timing Analysis
11. Complex to determine
11. Easier to determine
VLSI Lecture series
On Chip Clock Generation
and Distribution
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Clock in Digital Integrated circuits
❖ Pierce Crystal oscillator
❖ Generation of two non overlapping clocks
❖ Y chart of VLSI Design flow
Basics of Clock in Digital Integrated Circuits
❖ Clock signals are the heartbeats of digital systems. So, stability of
clock signal is highly important.
❖ Ideally, clock signal should have minimum rise time & fall time, it
should have specified duty cycles and zero skew.
Rise Time
Skew
Fall Time
Basics of Clock in Digital Integrated Circuits
❖ Practically, there is noticeable rise time and fall time, Duty cycles can
also vary.
❖ In fact, as much as 10% of a machine cycle time us expanded to
allow realistic clock skews in large computer system.
❖ On chip generated clock can be process dependent and unstable.
❖ As a result, usually separate clock chip which use crystal oscillators
have been used for high performance VLSI chip.
Pierce Crystal Oscillator
❖ In this crystal, series resonant exists.
❖ But
internal
series
resonant
determines the oscillation frequency.
❖ External load at the terminals has
considerable effect on its frequency
and frequency stability.
❖ Higher the series resistance, lower
the resonant frequency.
Generation of two non overlapping clock
❖ Product of two non overlapping clock is zero at all times.
Ck
Ck-1
Ck-2
VLSI Lecture series
Comparison of FPGA,
CPLD, PLC,
Microprocessor,
Microcontroller & DSP
By Prof. Hitesh Dholakiya
Engineering Funda
CPLD
PLC
MP
MC
1. Full Form
Field
Programmable
Gate Array
Complex
Programmable
Logic Device
Programmable
Logic Control
Microprocessor
Microcontroller
Digital Signal
Processor
2. Architecture
Look up table
Logical Blocks
CPU, IO port,
Memory
CPU, IO Port
Von Neumann
Mostly
Harvard
architecture
3. Applications
Real Time
Applications
(Fine Tuning)
Course Tuning
Applications
In Industries, at
high power &
high Temp.
Computer
Applications
Consumer
Electronics like
Camera,
Automobile
Real Time
Applications
(Fine Tuning)
4. Response
Fast for real
time
Slow
Slow
Optimized for
speed only
Slow
Fast for real
time
5. Immunity with noise
Very Good
Moderate
Highest
Needs
additional setup
Low
Good
6. Task
Not designed for
Multitasking
Single Task
Single Task
Multitasking
Not designed
for Multitasking
Not designed
for Multitasking
7. Turn ON time
It takes time to
get ON
Less Time (In
terms of mili
Sec)
Less Time (In
terms of Mili
Sec)
It takes time to
get ON
Less Time (In
terms of Micro
Sec)
Less Time (In
terms of Neno
Sec)
8. Cost
Expensive
Cheap
Expensive
Expensive
Cheap
Expensive
Parameters
FPGA
DSP
VLSI Lecture series
CMOS Fabrication
Process
By Prof. Hitesh Dholakiya
Engineering Funda
nMOS and pMOS structure on P Type Substrate
Create n well or p well
region and channel
stop region
Grow field oxide (Thick
Oxide) and gate oxide
(Thin Oxide)
Deposit and pattern
polysilicon layer
Implant source, drain
region and substrate
contacts
Create contact
windows, deposit and
pattern metal layer
❖ For nMOS and pMOS, special region must be created in which
semiconductor type is opposite to the substrate type, these region
are called wells or tubs.
❖ p well is created in n type substrate and n well is created in p type
substrate.
❖ nMOS transistor are created in p type substrate or p well and pMOS
transistor are created in n type substrate or n well.
❖ That well should be of defined boundary to have fixed channel stop
region.
❖ Thick Oxide is grown in active region of nMOS and pMOS.
❖ The thin gate oxide is grown on the surface through thermal
oxidation.
❖ As per circuit make a pattern of polysilicon layer.
❖ After that create n+ and p+ regions for source, drain and substrate.
❖ Final metallization for metal interconnects.
nMOS and pMOS on P Type Substrate
VLSI Lecture series
Twin Tube Fabrication
Process
By Prof. Hitesh Dholakiya
Engineering Funda
Basics of Twin tube fabrication process
❖ In our previous video, I have explained nMOS and pMOS structure on P Type Substrate.
❖ In that, there can be issues regarding, mutual coupling in between nMOS and pMOS.
❖ There can be major issues regarding, Latch up for CMOS fabrication.
❖ To avoid those issues, we should fabrication nMOS and pMOS by twin tube fabrication
process.
n – Type Substrate
❖ Let us use n Type substrate.
❖ The resistivity of substrate should be higher.
❖ Higher the resistivity lesser the current
through substrate.
Epitaxial Layer
❖ Then we should grow n+ layer epitaxially.
❖ That is having lesser resistance compared to
substrate.
n – Type Substrate
SiO2 Layer
Epitaxial Layer
n – Type Substrate
❖ After that, substrate is subjected to oxidation
and we grow SiO2 layer.
SiO2 Layer
Epitaxial Layer
❖ SiO2 layer is etched using masking.
❖ Two windows are formed, One for n-well and
another for p-well.
n – Type Substrate
P+ diffusion
Photoresist mask
SiO2 Layer
P well
Epitaxial Layer
n – Type Substrate
❖ 1st window is covered by photoresist mask.
❖ Then p type impurities diffused to form p
well.
N+ diffusion
Photoresist mask
SiO2 Layer
n well
p well
Epitaxial Layer
❖ 2nd window is covered by photoresist mask.
❖ Then n type impurities diffused to form n
well.
n – Type Substrate
SiO2 Layer
n well
p well
Epitaxial Layer
n – Type Substrate
❖ Grow Thin SiO2 layer by thermal oxidation
for Gate terminal
❖ Grow Polysilicon layer for photolithography
and pattern making.
SiO2 Layer
n well
p well
❖ Each SiO2 and Polysilicon to implant Drain
and Source.
Epitaxial Layer
n – Type Substrate
p+ diffusion
Photoresist mask
p+
n well
p+
SiO2 Layer
p well
Epitaxial Layer
n – Type Substrate
❖ p well covered with photoresist mask and p+
diffusion is done to form source and drain
region
n+ diffusion
Photoresist mask
p+
n well
p+
SiO2 Layer
n+
p well
n+
❖ n well covered with photoresist mask and n+
diffusion is done to form source and drain
region
Epitaxial Layer
n – Type Substrate
S
p+
G
D
n well
p+
S
SiO2 Layer
n+
G
p well
Epitaxial Layer
n – Type Substrate
D
n+
❖ Metal diffusion is done
formation.
❖ Metal etching is done.
for
contact
❖ Contact formations for source S, Drain D and
Gate G is done
VLSI Lecture series
Two Terminal MOS
and it’s Energy band
diagram
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of MOS
❖ Two terminal MOS structure
❖ MOS substrate basic properties
❖ Energy band diagram of p type substrate
❖ Energy band diagram of MOS structure
❖ Energy Band diagram of Combined MOS structure
Basics of MOS
❖ Full form of MOS is ‘Metal Oxide Semiconductor’.
❖ Compared to BJT, it occupy less space. So it is more suitable for
integrated circuits.
❖ At gate terminal, if voltage is applied, it creates channel for
conduction in between DRAIN and SOURCE terminal.
❖ Conduction is only depends on majority carrier only.
Two Terminal MOS structure
Gate G Terminal
𝑽𝑮 Gate Voltage
Metal
Oxide SiO2
P Type Si Substrate
Substrate Terminal
𝑽𝑩 Substrate Voltage
❖By Adding impurities like BORON
(Trivalent) in pure semiconductor,
we make P type material.
❖ SiO2 layer is acting like a dielectric
layer. That forms capacitor in
between gate and substrate.
❖ Thickness is there in order of 10nm
to 50nm.
❖External voltage is applied in
between gate and substrate
terminal, which will justify carrier
concentration for channel.
MOS substrate basic properties
❖ At equilibrium as per Mass Action Law
𝒏𝒑 = 𝒏𝒊 𝟐
❖ Where, n & p are electrons & holes concentration, respectively.
❖ 𝑛𝑖 is intrinsic carrier concentration, its value at room temperature
300K is approximately 1.45 × 1010 1/𝑐𝑚−3 .
❖ Here, we have substrate of acceptor concentration 𝑁𝐴 (in order of
1015 to 1016 𝑐𝑚−3 ), so holes and electrons concentration is given by,
𝒑 = 𝑵𝑨
𝒏𝒊 𝟐
𝒏=
𝑵𝑨
Energy Band diagram of P Type substrate
❖ The bandgap in between conduction band and valance
band is 1.1eV.
Free Space
𝒒𝝌
𝑬𝒄 Conduction
Band
❖ For p type semiconductor, Fermi potential can be
approximated by
𝒌𝑻 𝒏𝒊
𝝓𝑭𝒑 =
𝐥𝐧
𝒒
𝑵𝑨
𝑬𝒊 Intrinsic Fermi
Level
❖ For n type semiconductor, Fermi potential can be
approximated by
𝒌𝑻 𝑵𝑫
𝝓𝑭𝒑 =
𝐥𝐧
𝒒
𝒏𝒊
Band gap 1.1eV
𝒒𝝓𝑭
❖ Fermi potential 𝝓𝑭 , is based on intrinsic Fermi Level 𝑬𝒊
and Fermi level 𝑬𝑭
𝑬𝑭 − 𝑬𝒊
𝝓𝑭 =
𝒒
𝑬𝑭 Fermi Level
𝑬𝒗 valance Band
❖ Electron affinity is 𝒒𝝌, which is energy gap in between
conduction band and Free space.
❖ Energy required to move electron from fermi level to free
space is work function 𝒒𝝓𝑺 .
𝒒𝝓𝒔 = 𝒒𝝌 + (𝑬𝑪 − 𝑬𝑭 )
Energy band diagram of MOS structure
Metal Al
Oxide
Semiconductor Si
𝒒𝝌 = 𝟎. 𝟗𝟓𝐞𝐕
𝒒𝝓𝑴 = 𝟒. 𝟏𝒆𝑽
𝑬𝒄 Conduction Band
𝑬𝑭 Fermi Level
Band gap 8eV
𝑬𝒗 valance Band
𝒒𝝌 = 𝟒. 𝟏𝟓𝐞𝐕
Energy band Diagram of combined MOS structure
❖ When we combined the three MOS material, fermi level must lined up in
single line and Free space must be continuous.
❖ Because of work function difference in between semiconductor and metal,
there is voltage drop across MOS and banding of bands.
Metal Al
Oxide
Semiconductor Si
𝑬𝒄 Conduction Band
𝑬𝒊 Intrinsic Level
𝑬𝑭 Fermi Level
𝑬𝑽 Valance Band
VLSI Lecture series
Flat Band Voltage
and Example on Flat
Band Voltage
By Prof. Hitesh Dholakiya
Engineering Funda
Basics of Flat Band Voltage
❖ Individually there is a different work function with Metal, SiO2 and
Substrate.
❖ When we combine three layers, Because of work function difference
between metal and semiconductor, voltage drop occurs across the
MOS structure.
❖ Part of this voltage appears across SiO2 layer and rest across the
silicon surface.
❖ This results into banding of energy bands.
❖ So, to get energy band without any banding, voltage required is
referred as flat band voltage
Consider the MOS structure that consists of a p type doped Si substrate, a SiO2 layer and a metal (Al)
gate. The equilibrium Fermi potential of the doped Si substrate is 𝒒𝝓𝑭𝒑 = 𝟎. 𝟐𝒆𝑽. Using electron
affinity for Si & work function for Al given in figure, Calculate the built in potential difference across
MOS system.
❖ Work Function for Si
∴ 𝒒𝝓𝒔 = 𝒒𝝌 + (𝑬𝑪 − 𝑬𝑭 )
∴ 𝒒𝝓𝒔 = 𝟒. 𝟏𝟓 + (𝟎. 𝟓𝟓 + 𝟎. 𝟐)
∴ 𝒒𝝓𝒔 = 𝟒. 𝟗𝒆𝑽
❖ So work function difference
in between metal and
substrate is given by
∴ 𝒒𝝓𝒎 − 𝒒𝝓𝒔 = 𝟒. 𝟏 − 𝟒. 𝟗
∴ 𝒒𝝓𝒎 − 𝒒𝝓𝒔 = −𝟎. 𝟖𝒆𝑽
❖ So if voltage corresponding to this is applied externally between gate and substrate then the banding of energy bands
can be compensated and energy bands become flat. So flat band voltage is given by
∴ 𝑽𝑭𝑩 = 𝝓𝒎 − 𝝓𝒔
VLSI Lecture series
MOS under External
Bias
By Prof. Hitesh Dholakiya
Engineering Funda
Basics of External biasing to MOS
❖ Here, we apply external bias to MOS by Gate voltage 𝑉𝐺 and
substrate voltage 𝑉𝐵 .
❖ Here we keep, 𝑉𝐵 = 0 (constant) and 𝑉𝐺 as controlling voltage.
❖ Depending on the polarity and magnitude of 𝑉𝐺 , MOS functions in
three different regions.
❑ Accumulation
❑ Depletion
❑ Inversion
Condition 1 : 𝑽𝑮 < 𝟎 and 𝑽𝑩 = 𝟎 Accumulation
Gate G Terminal
𝑽𝑮 Gate Voltage
Metal Al
𝑽𝑮 < 𝟎
Metal
𝑬𝒐𝒙
Oxide SiO2
Semiconductor Si
𝑬𝒄 Conduction
Band
𝑬𝒐𝒙
Holes accumulated on the surface
P Type Si Substrate
Oxide
𝒒𝑽𝑮
𝑬𝒊 Intrinsic Fermi
Level
𝑬𝑭 Fermi Level
𝑬𝒗 valance Band
Substrate Terminal
𝑽𝑩 Substrate Voltage
𝑽𝑩 = 𝟎
❖ Here carrier concentration becomes larger on surface, this is
called accumulation of carrier on the surface.
❖ Here, electron concentration goes deeper inside due to negative
potential
Condition 1 : 𝑽𝑮 > 𝟎 (small) and 𝑽𝑩 = 𝟎 Depletion
Gate G Terminal
𝑽𝑮 Gate Voltage
Metal Al
𝑽𝑮 > 𝟎
Oxide SiO2
𝑬𝒐𝒙
𝑬𝒊 Intrinsic Fermi
Level
Depletion Region
P Type Si Substrate
𝒒𝑽𝑮
Substrate Terminal
𝑽𝑩 Substrate Voltage
𝑽𝑩 = 𝟎
Semiconductor Si
𝑬𝒄 Conduction
Band
Metal
𝑬𝒐𝒙
Oxide
𝑬𝑭 Fermi Level
𝑬𝒗 valance Band
❖ Here carrier concentration (holes) will move deeply inside P type
material, and that forms depletion region near to surface of oxide layer.
Condition 1 : 𝑽𝑮 > 𝟎 (Large) and 𝑽𝑩 = 𝟎 Inversion
Gate G Terminal
𝑽𝑮 Gate Voltage
Metal Al
𝑽𝑮 > 𝟎
Oxide SiO2
𝑬𝒐𝒙
𝑬𝒊 Intrinsic Fermi
Level
Electrons
Depletion Region
P Type Si Substrate
𝒒𝑽𝑮
Substrate Terminal
𝑽𝑩 Substrate Voltage
𝑽𝑩 = 𝟎
Semiconductor Si
𝑬𝒄 Conduction
Band
Metal
𝑬𝒐𝒙
Oxide
𝑬𝑭 Fermi Level
𝑬𝒗 valance Band
❖ For Large gate voltage, electrons will make layer at surface of oxide, which is
opposite to p type substrate, that is called surface inversion.
❖ Below electrons, there will depletion layer.
❖ After some voltage, depletion layer will not increase and electrons will
increase.
VLSI Lecture series
Thickness of depletion
region, Depletion region
charge density and Surface
Inversion in MOS structure
By Prof. Hitesh Dholakiya
Engineering Funda
𝑽𝑮 > 𝟎 (small) and 𝑽𝑩 = 𝟎 Depletion region
Gate G Terminal
𝑽𝑮 Gate Voltage
❖ Here we will calculate depletion
width 𝒙𝒅 as a function of surface
potential 𝝓𝑺 .
❖ Mobile hole charge in a thin
horizontal layer parallel to the
surface is
𝑽𝑮 > 𝟎
Metal
𝑬𝒐𝒙
Oxide SiO2
𝑬𝒐𝒙
Depletion Region 𝒙𝒅
P Type Si Substrate
X
𝒅𝑸 = −𝒒𝑵𝑨 𝒅𝒙
❖ The change in surface potential
required to displace thin charge
dQ by distance 𝒙𝒅 can be
calculated by Poisson equation.
𝒅𝑸
𝒅𝝓 = −𝒙 .
𝜺𝑺𝒊
Substrate Terminal
𝑽𝑩 Substrate Voltage
𝑽𝑩 = 𝟎
𝒒𝑵𝑨 𝒙𝒅𝒙
𝜺𝑺𝒊
❖ In integration, dx varies from 0 to
𝒙𝒅 and potential varies from
Fermi potential 𝝓𝑭 to surface
potential 𝝓𝑺 .
𝒅𝝓 =
𝝓𝑺
𝒙𝒅
∴ න 𝒅𝝓 = න
𝝓𝑭
𝟎
𝒒𝑵𝑨 𝒙𝒅𝒙
𝜺𝑺𝒊
𝒒𝑵𝑨 𝒙𝒅 𝟐
∴ 𝝓𝑺 − 𝝓𝑭 =
𝟐𝜺𝑺𝒊
❖ So depth of depletion region is
∴ 𝒙𝒅 =
𝟐𝜺𝑺𝒊 (𝝓𝑺 − 𝝓𝑭 )
𝒒𝑵𝑨
❖ So depletion region charge density
is given by
∴ 𝑸 = −𝒒𝑵𝑨 𝒙𝒅
∴ 𝑸 = − 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊 (𝝓𝑺 − 𝝓𝑭 )
❖ Now if we further increase the
gate voltage then it will start to
create surface inversion by
attracting electrons.
𝑽𝑮 > 𝟎 (Large) and 𝑽𝑩 = 𝟎 Inversion Region
Gate G Terminal
𝑽𝑮 Gate Voltage
𝑽𝑮 > 𝟎
Metal
𝑬𝒐𝒙
Oxide SiO2
𝑬𝒐𝒙
Depletion Region
P Type Si Substrate
Substrate Terminal
𝑽𝑩 Substrate Voltage
𝑽𝑩 = 𝟎
❖ When surface inversion takes place, the density of
mobile electrons on the surface equals to the density
of holes in the p type.
❖ Condition for that is given by (𝝓𝑺 = −𝝓𝑭 )
❖ Now if we further increase gate voltage 𝑽𝑮 then
width of depletion region will not increase but it
increase the number of electrons.
❖ So maximum depletion region depth can be
Electrons
calculated by
∴ 𝒙𝒅𝒎 =
𝟐𝜺𝑺𝒊 (𝟐𝝓𝑭 )
𝒒𝑵𝑨
❖ So this creation of inversion layer by externally
applied gate voltage is used for channel creation in
MOSFET, Which is used for current conduction in
between drain and source.
VLSI Lecture series
MOS Transistor
MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of MOS Transistor
❖ Types of MOS Transistor
❖ Structure of n channel MOSFET
❖ Working of n channel MOSFET
Basics of MOS Transistor
❖ It is MOSFET (Metal Oxid Semiconductor Field Effect Transistor)
❖ It has four terminals : Gate, Substrate, Drain and Source.
❖ This device is formed using MOS structure.
❖ Structure of MOS transistor is symmetrical to drain and source
terminal.
Types of MOS Transistor
❖ There are two types of MOS transistor based on channel.
❑ Enhancement type MOS Transistor : It has no conducting channel
region at zero gate bias voltage.
❑ Depletion type MOS Transistor : It has conducting channel region
at zero gate bias voltage.
Structure of n Channel MOSFET
Gate G
Source S
Source n+
Metal
Oxide SiO2
Channel Length L
P Type Si Substrate
Substrate
Drain D
Drain n+
Working of n Channel MOSFET in cut off region
𝑽𝑮𝑺 < 𝑽𝑻𝟎
Depletion Region
Working of n Channel MOSFET cut off region
𝑽𝑮𝑺 > 𝑽𝑻𝟎
Inversion Layer (Channel)
Depletion Region
Working of n Channel MOSFET in Linear region
𝑽𝑮𝑺 > 𝑽𝑻𝟎
𝑽𝑫 small
Inversion Layer (Channel)
Depletion Region
Working of n Channel MOSFET threshold of
linear region
𝑽𝑮𝑺 > 𝑽𝑻𝟎
𝑽𝑫 = 𝑽𝑫𝑺𝑨𝑻
Inversion Layer (Channel)
Depletion Region
Pinch off Point
Working of n Channel MOSFET in saturation
region
𝑽𝑮𝑺 > 𝑽𝑻𝟎
𝑽𝑫 > 𝑽𝑫𝑺𝑨𝑻
Inversion Layer (Channel)
Depletion Region
Pinch off Point
VLSI Lecture series
Threshold Voltage of
MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Threshold Voltage of MOSFET
❖ Parameters of Threshold Voltage of MOSFET
❖ Derivation of Threshold Voltage of MOSFET
Basics of Threshold Voltage of MOSFET
❖ It is a minimum voltage 𝑉𝐺𝑆 (Gate to Source) required to form
inversion layer (channel) in between source and drain.
❖ Threshold voltage defines operation of MOSFET.
❖ If 𝑉𝐺𝑆 is less than threshold voltage then MOSFET will stay in cut off
region.
Parameters of Threshold Voltage in MOSFET
❖ There are four physical parameters which effects the
threshold voltage of MOS structure:
❑ Work function difference between gate and the channel.
❑ The gate voltage component to change surface potential.
❑ The gate voltage component to offset the depletion region
charge.
❑ The voltage component to offset the fixed charges in the gate
oxide and in the silicon oxide interface.
Derivation of Threshold Voltage in MOSFET
❖ Work function difference 𝝓𝑮𝑪 in between the gate and
the channel is given by
𝝓𝑮𝑪 = 𝝓𝑭 𝑺𝒖𝒃𝒔𝒕𝒓𝒂𝒕𝒆 − 𝝓𝑴 (𝑴𝒆𝒕𝒂𝒍)
𝝓𝑮𝑪 = 𝝓𝑭 𝑺𝒖𝒃𝒔𝒕𝒓𝒂𝒕𝒆 − 𝝓𝑭 (𝑮𝒂𝒕𝒆 𝒑𝒐𝒍𝒚𝒔𝒊𝒍𝒊𝒄𝒐𝒏)
❖ For surface inversion, surface potential should change
form 𝝓𝑭 to −𝝓𝑭 . So net change will be −𝝓𝑭 − 𝝓𝑭 =
− 𝟐𝝓𝑭 .
❖ When voltage is applied at gate, it repelled holes deeper
inside substrate, and it forms depletion region. This
region has ions which forms offset voltage due to charges
of ions near the surface.
❖ So depletion region charge density at surface inversion
(𝝓𝑺 = −𝝓𝑭 ) is given by
𝑸𝑩𝑶 = − 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊 −𝟐𝝓𝑭
❖ If substrate bias is given with 𝑽𝑺𝑩 then depletion region
charge density is given by
𝑸𝑩 = − 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊 −𝟐𝝓𝑭 + 𝑽𝑺𝑩
❖ So, the component of voltage which nullify the value will
be −𝑸𝑩 /𝑪𝑶𝑿, where 𝑪𝑶𝑿 is gate oxide capacitance per
unit area.
❖ There is also fixed positive charge density 𝑸𝑶𝑿 , it is due
to lattice imperfections at the interface.
❖ So the forth component for threshold voltage will be
− 𝑸𝑶𝑿 /𝑪𝑶𝑿 .
❖ So, for zero substrate bias, threshold voltage is given by
𝑸𝑩𝑶 𝑸𝑶𝑿
𝑽𝑻𝑶 = 𝝓𝑮𝑪 − 𝟐𝝓𝑭 −
−
𝑪𝑶𝑿 𝑪𝑶𝑿
❖ For non zero substrate bias, threshold voltage is given by
𝑸𝑩 𝑸𝑶𝑿
𝑽𝑻 = 𝝓𝑮𝑪 − 𝟐𝝓𝑭 −
−
𝑪𝑶𝑿 𝑪𝑶𝑿
𝑸𝑩𝑶 𝑸𝑶𝑿 𝑸𝑩 − 𝑸𝑩𝑶
𝑽𝑻 = 𝝓𝑮𝑪 − 𝟐𝝓𝑭 −
−
−
𝑪𝑶𝑿 𝑪𝑶𝑿
𝑪𝑶𝑿
𝑸𝑩 − 𝑸𝑩𝑶
𝑽𝑻 = 𝑽𝑻𝑶 −
𝑪𝑶𝑿
❖ Here,
𝑸𝑩 − 𝑸𝑩𝑶 − 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊
=
( −𝟐𝝓𝑭 + 𝑽𝑺𝑩 − −𝟐𝝓𝑭 )
𝑪𝑶𝑿
𝑪𝑶𝑿
❖ So Threshold voltage is given by
𝑽𝑻 = 𝑽𝑻𝑶 + 𝜸(
−𝟐𝝓𝑭 + 𝑽𝑺𝑩 −
❖ Where, ϒ is substrate bias or
body effect coefficient
𝜸=
−𝟐𝝓𝑭 )
𝟐𝒒𝑵𝑨 𝜺𝑺𝒊
𝑪𝑶𝑿
VLSI Lecture series
Gradual Channel
Approximation, Drain
Current Equation &
MOSFET Characteristics
By Prof. Hitesh Dholakiya
Engineering Funda
Gradual Channel Approximation in MOSFET
𝑽𝑮𝑺 > 𝑽𝑻𝟎
𝑽𝑫𝑺 small
Y=L
Y=0
Y
X
Depletion Region
Inversion Layer (Channel)
❖ 𝑽𝑮𝑺 > 𝑽𝑻𝑶 and 𝑽𝑮𝑫 > 𝑽𝑻𝑶 , to form a channel.
❖ Threshold voltage 𝑽𝑻𝑶 is assumed to be constant.
❖ Channel Voltage 𝑽𝑪 (𝒚) will change with respect to Y.
𝑽𝑪 𝒀 = 𝟎 = 𝑽𝑺 = 𝟎
𝑽𝑪 𝒀 = 𝑳 = 𝑽𝑫𝑺
❖ Electric field component in Y direction is dominant
compared to X direction, so current flow only confined in
Y direction.
❖ Let 𝑸𝑰 (𝒀) is the charge density in channel,
𝑸𝑰 (𝒀) = −𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑪 𝒀 − 𝑽𝑻𝑶
❖ Net voltage at source is (𝑽𝑮𝑺 − 𝑽𝑻𝑶 ) maximum and Net
voltage at drain is (𝑽𝑮𝑺 − 𝑽𝑫𝑺 − 𝑽𝑻𝑶 ) minimum. So, for dy
thickness, we will calculation incremental resistance dR.
𝒅𝑹 = −
𝒅𝒚
𝑾. 𝝁𝒏 . 𝑸𝑰 (𝒀)
❖ Channel current density is assumed to be constant, 𝑰𝑫
current flows from source to drain. So as per Ohm’s law
𝑰𝑫
. 𝒅𝒚
𝑾. 𝝁𝒏 . 𝑸𝑰 𝒀
❖ Here, y changes from 0 to L and 𝑽𝑪 changes from 0 to 𝑽𝑫𝑪
𝒅𝑽𝑪 = 𝑰𝑫 . 𝒅𝑹 = −
𝑳
𝑽𝑫𝑺
∴ න 𝑰𝑫 . 𝒅𝒚 = −𝑾. 𝝁𝒏 න
𝟎
𝟎
𝑽𝑫𝑺
∴ 𝑰𝑫 . 𝑳 = 𝑾. 𝝁𝒏 . 𝑪𝑶𝑿 න
𝟎
∴ 𝑰𝑫 =
𝑸𝑰 𝒀 . 𝒅𝑽𝑪
[𝑽𝑮𝑺 −𝑽𝑪 − 𝑽𝑻𝑶 ] . 𝒅𝑽𝑪
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
.
𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐
𝑳
❖ Here, if consider, 𝒌′ = 𝝁𝒏 . 𝑪𝑶𝑿 , then drain current will be
∴ 𝑰𝑫 =
𝒌′ 𝑾
.
𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐 𝑳
❖ So for saturation region drain current 𝑰𝑫 will be
𝑾
❖ Here, if consider, 𝐤 = 𝒌′ , then drain current will be
𝑳
𝒌
∴ 𝑰𝑫 = 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐
❖ This equation of drain current 𝑰𝑫 is valid in linear region of
MOSFET.
❖ In saturation region of MOSFET,
∴ 𝑽𝑫𝑺 ≥ 𝑽𝑫𝑺𝑨𝑻 = 𝑽𝑮𝑺 − 𝑽𝑻𝑶
𝒌
𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 (𝑽𝑮𝑺 − 𝑽𝑻𝑶 ) − (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐
𝒌
= . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
=
. . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐
𝑳
∴ 𝑰𝑫𝑺𝑨𝑻 =
∴ 𝑰𝑫𝑺𝑨𝑻
∴ 𝑰𝑫𝑺𝑨𝑻
VLSI Lecture series
Channel Length
Modulation of MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Channel Length Modulation
❖ Channel length Modulation in MOSFET
❖ Derivation of drain current for channel length modulation
❖ Characteristics of MOSFET with channel length modulation
Basics of Channel length Modulation
❖ In saturation region of working with MOSFET, there is channel length
Modulation with MOSFET.
❖ In that channel length will change with respect to drain voltage of
MOSFET.
❖ Channel length will decrease with respect to increase in drain
voltage in saturation region.
Channel Length Modulation in MOSFET
𝑽𝑮𝑺 > 𝑽𝑻𝟎
𝑽𝑫 >
=
𝑽𝑫𝑺𝑨𝑻
small
L’
∆L
L
Inversion Layer (Channel)
Depletion Region
Pinch Off Point Pinch Off Point
❖ At pinch off point of channel, channel voltage will be 𝑽𝑫𝑺𝑨𝑻
❖ Gradual channel approximation is only valid in channel,
as per that drain current in deep saturation is given by
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 (𝒔𝒂𝒕) =
. . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐
𝑳′
𝝁𝒏 . 𝑪𝑶𝑿
𝑾
∴ 𝑰𝑫 (𝒔𝒂𝒕) =
.
. (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐
(𝑳 − ∆𝑳)
❖ Total charge density in channel is given by
𝑸𝑰 (𝒀) = −𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑪 𝒀 − 𝑽𝑻𝑶
❖ Inversion layer charge at source (Y=0) end is given by
𝑸𝑰 (𝒀 = 𝟎) = −𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑻𝑶
❖ Inversion layer charge at Drain end (Y=L) end is given by
𝑸𝑰 (𝒀 = 𝑳) = −𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑫𝑺 − 𝑽𝑻𝑶
❖ At the edge of saturation 𝑽𝑫𝑺 = 𝑽𝑫𝑺𝑨𝑻
𝑽𝑫𝑺 = 𝑽𝑫𝑺𝑨𝑻 = 𝑽𝑮𝑺 − 𝑽𝑻𝑶
❖ Inversion layer charge at Drain end (Y=L) in saturation
region is given by
𝑸𝑰 (𝒀 = 𝑳) ≈ 𝟎
❖ Effective channel length in saturation region will become
𝑳′ = 𝑳 − ∆𝑳
∴ 𝑰𝑫 (𝒔𝒂𝒕) =
❖ Here,
∆𝑳 ∝
𝟏
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
. . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
∆𝑳
𝟐
𝑳
𝟏−
𝑳
𝑽𝑫𝑺 − 𝑽𝑫𝑺𝑨𝑻
❖ To simplify this drain current equation, we will take λ
(Channel length modulation coefficient)
∆𝑳
𝟏
= 𝟏 − 𝝀𝑽𝑫𝑺 ⇒
= 𝟏 + 𝝀𝑽𝑫𝑺
∆𝑳
𝑳
𝟏−
𝑳
❖ So drain current is given by
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 𝒔𝒂𝒕 =
. . 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝟐 . (𝟏 + 𝝀𝑽𝑫𝑺 )
𝟐
𝑳
∴𝟏−
❖ Drain current is given by
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 𝒔𝒂𝒕 =
. . 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝟐 . (𝟏 + 𝝀𝑽𝑫𝑺 )
𝟐
𝑳
Drain Current
with λ ≠ 0
𝑽𝑮𝑺𝟐 with λ=0
with λ ≠ 0
𝑽𝑮𝑺𝟏 with λ=0
Drain Voltage
VLSI Lecture series
Examples on Drain
Current Calculation
By Prof. Hitesh Dholakiya
Engineering Funda
Drain current 𝑰𝑫 is given by
∴ 𝑰𝑫
∴ 𝑰𝑫
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
=
.
𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐
𝑳
𝟒𝟎𝟎 × 𝟏𝟎−𝟒 × 𝟖𝟎𝟎 × 𝟏𝟎−𝟔
=
× 𝟏. 𝟓 × 𝟐 𝟏. 𝟖 − 𝟏 𝟏 − 𝟏𝟐
𝟐
∴ 𝑰𝑫 = 𝟏𝟒. 𝟒 × 𝟏𝟎−𝟔 𝑨
∴ 𝑰𝑫 = 𝟏𝟒. 𝟒 𝝁𝑨
Example 2 : For an n channel MOS transistor with 𝝁𝒏 = 𝟔𝟎𝟎 𝒄𝒎𝟐 /𝑽𝑺𝒆𝒄, 𝑪𝑶𝑿 =
𝟕 × 𝟏𝟎−𝟖 𝑭/𝒄𝒎𝟐 , 𝑾 = 𝟐𝟎𝝁𝒎, 𝐋 = 𝟐𝝁𝒎 and 𝑽𝑻𝑶 = 𝟏𝑽.
Here biasing voltages for drain, Source and substrate are given by 3V, 0V and 0V,
respectively. For drain current to be 1mA, what should be gate bias voltage?
Drain current 𝑰𝑫 is given by
∴ 𝑰𝑫
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
𝒌
𝟐
=
.
𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐
𝑳
𝟐
k is given by
𝑾
∴ 𝒌 = 𝝁𝒏 . 𝑪𝑶𝑿 .
𝑳
−𝟖
−𝟔
𝟕
×
𝟏𝟎
𝟐𝟎
×
𝟏𝟎
∴ 𝒌 = 𝟔𝟎𝟎 × 𝟏𝟎−𝟒 ×
×
−𝟒
𝟏𝟎
𝟐 × 𝟏𝟎−𝟔
∴ 𝒌 = 𝟒. 𝟐 × 𝟏𝟎−𝟒 𝑨/𝑽𝟐
∴ 𝒌 = 𝟎. 𝟒𝟐 𝒎𝑨/𝑽𝟐
Drain current 𝑰𝑫 is given by
𝒌
∴ 𝑰𝑫 = . 𝟐 𝑽𝑮 − 𝑽𝑻𝑶 𝑽𝑫 − 𝑽𝑫 𝟐
𝟐
𝟎. 𝟒𝟐
∴𝟏 =
. 𝟐 𝑽𝑮 − 𝟏 𝟑 − 𝟑𝟐
𝟐
∴ 𝑽𝑮 = 𝟑. 𝟐𝟗 𝑽𝒐𝒍𝒕
For pMOSFET to be in Saturation region
Part -1 for pMOSFET
∴ 𝑽𝑫𝑺 ≤ 𝑽𝑮𝑺 − 𝑽𝑻𝑶
∴ (𝟑 − 𝟓) ↔ (𝟎 − 𝟓) − (−𝟏. 𝟓)
∴ −𝟐 ↔ −(𝟑. 𝟓)
∴ −𝟐 > − 𝟑. 𝟓 (so Linear region)
For nMOSFET to be in Saturation region
Part -2 for nMOSFET
∴ 𝑽𝑫𝑺 ≥ 𝑽𝑮𝑺 − 𝑽𝑻𝑶
∴ (𝟑 − 𝟎) ↔ (𝟓 − 𝟎) − (𝟏. 𝟓)
∴ 𝟑 ↔ (𝟑. 𝟓)
∴ 𝟑 < 𝟑. 𝟓 (so Linear region)
VLSI Lecture series
Substrate Bias Effect
in MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Substrate Bias Effect in MOSFET
❖ Substrate Bias Effect with MOSFET characteristics
❖ Threshold voltage under substrate bias voltage
❖ Drain Current under substrate bias voltage
Basics of Substrate Bias Effect
❖ We have studied MOSFET characteristics with substrate bias
voltage 𝑽𝑺𝑩 = 𝟎.
❖ For zero substrate bias voltage, threshold voltage is referred as
𝑽𝑻𝑶 .
❖ In many digital circuit applications, the source potential of nMOS
transistor can be larger values, which results into 𝑽𝑺𝑩 > 𝟎.
❖ In that cases, Threshold voltage will change with respect to 𝑽𝑺𝑩
and that leads to change in drain current, it means drain current is a
function of 𝑽𝑺𝑩 , 𝑽𝑮𝑺 and 𝑽𝑫𝑺 .
𝑰𝑫 = 𝒇(𝑽𝑮𝑺 , 𝑽𝑫𝑺 , 𝑽𝑺𝑩 )
Substrate Bias Effect
Threshold Voltage under substrate bias voltage
❖ Threshold voltage under substrate bias voltage is given by
𝑽𝑻 (𝑽𝑺𝑩 ) = 𝑽𝑻𝑶 + 𝜸(
−𝟐𝝓𝑭 + 𝑽𝑺𝑩 −
−𝟐𝝓𝑭 )
❖ Where, ϒ is substrate bias or body effect coefficient
𝜸=
𝟐𝒒𝑵𝑨 𝜺𝑺𝒊
𝑪𝑶𝑿
Drain Current under substrate bias voltage
❖ Drain current in linear and saturation region with substrate bias
voltage is given by
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 (𝒍𝒊𝒏) =
.
𝟐 𝑽𝑮𝑺 − 𝑽𝑻 (𝑽𝑺𝑩 ) 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐
𝑳
∴ 𝑰𝑫
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
𝒔𝒂𝒕 =
. . 𝑽𝑮𝑺 − 𝑽𝑻 (𝑽𝑺𝑩 ) 𝟐 . (𝟏 + 𝝀𝑽𝑫𝑺 )
𝟐
𝑳
❖ Where, λ is Channel length Modulation coefficient
VLSI Lecture series
MOSFET
Capacitances
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of MOSFET Capacitances
❖ Structural overview of MOSFET Capacitances
❖ MOSFET capacitance Model
❖ MOSFET Capacitances in different regions of MOSFET
Basics of MOSFET Capacitances
❖ Speed of integrated circuit is limited by Capacitances.
❖ These capacitances are not lumped but distributed.
❖ It’s values can be calculated by three dimensional
overview of MOSFET.
❖ Here, we have already studied 𝑪𝑶𝑿 , which is gate oxide
capacitance, it’s unit is 𝑭ൗ𝑪𝒎𝟐 .
𝑪𝑶𝑿
𝜺𝑶𝑿
=
𝒕𝑶𝑿
Structural Overview of MOSFET Capacitances
MOSFET Capacitances in different regions
Cut Off region
𝑪𝑮𝑩 = 𝑪𝑶𝑿 𝑾𝑳
𝑪𝑮𝑫 = 𝑪𝑶𝑿 𝑾𝑳𝑫
𝑪𝑮𝑺 = 𝑪𝑶𝑿 𝑾𝑳𝑫
Linear region
𝑪𝑮𝑩 = 𝟎
𝟏
𝑪𝑮𝑫 = 𝑪𝑶𝑿 𝑾𝑳 + 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟐
𝟏
𝑪𝑮𝑺 = 𝑪𝑶𝑿 𝑾𝑳 + 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟐
Saturation region
𝑪𝑮𝑩 = 𝟎
𝑪𝑮𝑫 = 𝑪𝑶𝑿 𝑾𝑳𝑫
𝑪𝑮𝑺
𝟐
= 𝑪𝑶𝑿 𝑾𝑳 + 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟑
VLSI Lecture series
BIST
(Built In Self Test)
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of BIST
❖ Types of BIST
❖ Architecture of BIST
❖ Working of BIST
❖ Issues of designing BIST
❖ Advantages of BIST
❖ Disadvantages of BIST
Basics of BIST
❖ It is technique of designing additional hardware and software into
integrated circuits to allow them to perform self testing.
❖ Aim of BIST technique is to avoid costly use of ATE (Automated Test
Equipment) testing.
❖ As IC’s are getting complex, many blocks are interfaced in IC with
analog and digital ports, in that ATE testing is difficult and costly
service.
❖ BIST is also useful to those blocks of IC which has no direct
connection with external pins.
❖ As IC’s are upgrading, in future conventional testers will no longer be
adequate for the latest and fastest chip.
Types of BIST
❖ Here, I will give basic explanation about two different BIST
1. Logic BIST (LBIST)
2. Memory BIST (MBIST)
Logic BIST (LBIST)
❖ It is designed for testing random logic.
❖ Here we use pseudo random pattern generator to generate random
input pattern.
❖ Multiple Input signature register (MISR) gives response of input
pattern and MISR output indicates defect in the device.
Memory BIST (MBIST)
❖ It is used for testing memories.
❖ It has a circuit that apply, read and compare test patterns.
❖ There are some industry standard for MBIST
❑ The March Algorithm
❑ The checkerboard Algorithm
❑ The varied pattern background Algorithm
Basic Architecture of BIST
Test
ROM
Test Controller
Reference
Signature
Hardware
Pattern
generator
MUX
Normal
Input
CUT
(Circuit Under Test)
Output
Response
Compactor
Signature
Comparator
Good/Faulty
Issues of BIST designing
❖ how many faults to be covered
❖ how much chip area occupied by BIST
❖ Test Time
❖ Flexibility by software and hardware
Advantages of BIST
❖ It lowers testing cost
❖ Testing is independent on future technology
❖ better fault coverage
❖ shorter test time
❖ Easier customer support
Disadvantages of BIST
❖ Additional circuit (Silicon area) for BIST testing in IC
❖ Additional Pin required for BIST testing in IC
❖ On chip testing may get failed then how to test it.
VLSI Lecture series
Resistive Load
Inverter
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Circuit of resistive load inverter
❖ Working of resistive load inverter
❖ Voltage transfer characteristics of resistive load inverter
❖ Parameters of resistive load inverter
Circuit of Resistive load Inverter
𝑽𝑫𝑫
R
𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑺
𝑽𝑰𝑵 = 𝑽𝑮𝑺
Working of Resistive load Inverter
❖ Due to capacitance of gate oxide layer, gate
current is zero.
❖ So, 𝑰𝑹 = 𝑰𝑫
𝑰𝑹
❖ So, Output voltage 𝑽𝑶𝑼𝑻 equation will be
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 − 𝑰𝑹 𝑹
𝑰𝑫
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 − 𝑰𝑫 𝑹
❖ If input is lower voltage (logic 0), then
inversion layer will not get formed, So Drain
current will be zero
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 (logic 1)
❖ If input is higher voltage (Logic 1), then
inversion layer will get formed, So drain
current will increase, which will decrease
output to logic 0.
Working of Resistive load Inverter
❖ So, drain current equation will be
∴ 𝑰𝑫 =
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
𝑹
❖ Here, If MOSFET is there in linear region then 𝑽𝒊𝒏 − 𝑽𝑻𝑶 > 𝑽𝑶𝑼𝑻
❖ Drain current 𝑰𝑫 in linear region will be
𝒌
𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐
𝒌
= 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐
𝟐
∴ 𝑰𝑫 =
∴ 𝑰𝑫
❖ Here, If MOSFET is there in saturation region then 𝑽𝒊𝒏 − 𝑽𝑻𝑶 < 𝑽𝑶𝑼𝑻
∴ 𝑰𝑫
∴ 𝑰𝑫
𝒌
= . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐
𝒌
= . (𝑽𝑰𝑵 − 𝑽𝑻𝑶 )𝟐
𝟐
Voltage Transfer Characteristics of Resistive load Inverter
𝑽𝑶𝑼𝑻
𝑽𝑶𝑯
𝒅𝑽𝑶𝑼𝑻
= −𝟏
𝒅𝑽𝑰𝑵
𝒅𝑽𝑶𝑼𝑻
= −𝟏
𝒅𝑽𝑰𝑵
𝑽𝑶𝑳
𝑽𝑰𝑳
𝑽𝑰𝑯
𝑽𝑶𝑯
𝑽𝑰𝑵
Calculation of 𝑽𝑶𝑯
❖ Input voltage is less, so drain current is zero,
so per
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 − 𝑰𝑫 𝑹
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫
Calculation of 𝑽𝑶𝑳
❖ Here, 𝑽𝒊𝒏 − 𝑽𝑻𝑶 > 𝑽𝑶𝑼𝑻 , so MOSFET is there in
linear region, so drain current will be
∴ 𝑰𝑫 =
𝒌
𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐
𝟐
❖ Drain current is already derived
∴ 𝑰𝑫 =
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
𝑹
❖ From above equation
𝑽𝑫𝑫 − 𝑽𝑶𝑳 𝒌
= 𝟐 𝑽𝑫𝑫 − 𝑽𝑻𝑶 𝑽𝑶𝑳 − 𝑽𝑶𝑳 𝟐
𝑹
𝟐
𝟏
𝟐
∴ 𝑽𝑶𝑳 𝟐 − 𝟐 𝑽𝑫𝑫 − 𝑽𝑻𝑶 +
𝑽𝑶𝑳 +
𝑽 =𝟎
𝒌𝑹
𝒌𝑹 𝑫𝑫
∴
❖ Solution of this equation is
∴ 𝑽𝑶𝑳
𝟏
= 𝑽𝑫𝑫 − 𝑽𝑻𝑶 +
−
𝒌𝑹
𝟏
𝑽𝑫𝑫 − 𝑽𝑻𝑶 +
𝒌𝑹
𝟐
−
𝟐𝑽𝑫𝑫
𝒌𝑹
Calculation of 𝑽𝑰𝑳
❖ Here, 𝑽𝒊𝒏 − 𝑽𝑻𝑶 < 𝑽𝑶𝑼𝑻 , so MOSFET is there in
saturation region, so drain current will be
∴ 𝑰𝑫 =
𝒌
. (𝑽𝑰𝑵 − 𝑽𝑻𝑶 )𝟐
𝟐
❖ Drain current is already derived
∴ 𝑰𝑫 =
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
𝑹
❖ From above equation
∴
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻 𝒌
= . (𝑽𝑰𝑵 − 𝑽𝑻𝑶 )𝟐
𝑹
𝟐
❖ If differentiate given equation with respect to 𝑽𝒊𝒏
𝟏 𝒅𝑽𝑶𝑼𝑻
.
= 𝒌. 𝑽𝑰𝑵 − 𝑽𝑻𝑶
𝑹 𝒅𝑽𝑰𝑵
𝟏
∴ − . (−𝟏) = 𝒌. 𝑽𝑰𝑳 − 𝑽𝑻𝑶
𝑹
𝟏
∴ 𝑽𝑰𝑳 = 𝑽𝑻𝑶 +
𝒌𝑹
∴−
Calculation of 𝑽𝑰𝑯
❖ Here, 𝑽𝒊𝒏 − 𝑽𝑻𝑶 > 𝑽𝑶𝑼𝑻 , so MOSFET is there in
linear region, so drain current will be
∴ 𝑰𝑫
𝒌
= 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐
𝟐
❖ Drain current is already derived
∴ 𝑰𝑫 =
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
𝑹
❖ From above equation
∴
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻 𝒌
= 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐
𝑹
𝟐
❖ If differentiate given equation with respect to 𝑽𝒊𝒏
𝟏 𝒅𝑽𝑶𝑼𝑻 𝒌
𝒅𝑽𝑶𝑼𝑻
𝒅𝑽𝑶𝑼𝑻
∴− .
= 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶
− 𝟐𝑽𝑶𝑼𝑻
𝑹 𝒅𝑽𝑰𝑵
𝟐
𝒅𝑽𝑰𝑵
𝒅𝑽𝑰𝑵
𝟏
∴ 𝑽𝑰𝑳 = 𝑽𝑻𝑶 + 𝟐𝑽𝑶𝑼𝑻 −
𝒌𝑹
∴ 𝑽𝑰𝑳
𝟖 𝑽𝑫𝑫
𝟏
= 𝑽𝑻𝑶 +
−
𝟑 𝒌𝑹 𝒌𝑹
Average DC Power consumption
❖ Power consumption is voltage into current.
❖ Here duty cycle is 50%, so voltage = 𝑉𝐷𝐷ൗ2
❖ Here current =
𝑉𝐷𝐷 −𝑉𝑂𝐿
𝑅
❖ So average DC power dissipation is given by
𝑽𝑫𝑫 𝑽𝑫𝑫 − 𝑽𝑶𝑳
∴ 𝑷𝑫𝑪 (𝑨𝒗𝒆𝒓𝒂𝒈𝒆) =
×
𝟐
𝑹
VLSI Lecture series
Ion Implantation
and it’s Advantage
over Diffusion
By Prof. Hitesh Dholakiya
Engineering Funda
Ion Implantation
❖ It is alternative to diffusion process in IC fabrication.
❖ Diffusion Process is done at high temperature, but Ion implantation
is done at low temperature.
❖ In Ion Implantation, high energy dopant ions are accelerated, so that
ions can easily penetrate the Si wafer.
❖ The depth of penetration can be increased by increasing accelerating
voltage.
VLSI Lecture series
Faults in Integrated
Circuit
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Faults
❖ Types of Faults
❑ Permanent fault
❑ Non Permanent fault
Basics of Faults in IC
❖ It leads to improper output of IC.
❖ It may give false output in IC or It may reduce speed of IC.
❖ There are basically two types of faults in IC
❑ Permanent Fault
❑ Non Permanent Fault
Permanent Fault
❖ It changes functional behavior permanently.
❖ Mostly it happens due to physical fault.
❖ Examples
❑ Incorrect IC Mask
❑ Wrong Connections in IC’s
❑ PCB heating
Non Permanent Fault
❖ It happens at random moments
❖ It effects system behavior for random time period
❖ It is comparatively difficult to detect.
❖ There are two types
❑ Transient Faults : It is caused by environmental conditions such as humidity,
Pressure, vibrations, α particles etc.
❑ Intermittent Faults : It is caused by non environmental conditions such as
loose connections, Ageing of components etc.
VLSI Lecture series
Photolithography
By Prof. Hitesh Dholakiya
Engineering Funda
Photolithography
❖ It is a process to produce circuit/pattern on the Si Layer.
❖ UV light exposure is used.
❖ Two important steps are there in photolithography
1. Photographic Masking : It contains information which we want to project on
Si wafer.
2. Photographic Etching : It contains pattern information which we wants to
remove from layer.
❑ There are two types of photographic etching
➢ Wet Etching (By Chemical)
➢ Dry Etching (By UV light exposure)
VLSI Lecture series
Stuck at Fault
By Prof. Hitesh Dholakiya
Engineering Funda
Stuck at fault
❖ Any terminal may stuck at logic ‘0’ or Logic ‘1’ is referred as stuck at
fault.
❖ At that terminal, it has no dependency on I/P and O/P.
A
B
Correct Y Actual Y
❖ Examples
❑ Stuck at logic ‘1’
Stuck at ‘1’
A
Y
B
❑ Stuck at logic ‘0’
Stuck at ‘0’
A
Y
B
0
0
0
0
0
1
0
1
1
0
0
0
1
1
1
1
A
B
Correct Y
Actual Y
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
0