Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Philadelphia University
Faculty of Engineering
Communication and Electronics Engineering
Amplifier Circuits
Multistage Amplifier Analysis:
- Cascaded Systems:
Based on the two-port approach, the multistage amplifier is clearly shown
in the figure below.
Each of these stages could be one of the previously studied BJT, FET
transistor amplifiers.
The loaded voltage gain of an amplifier is always less than the no-load level.
From the Figure shown above let the under loaded system voltage gain
is Av , where Av  Av Av Av Av . Then the total current gain could be
T
T
found as Ai 
T
1
2
3
n
Zi
I o  Vo RL

  AvT  1 .
Ii
Vi Z i
RL
The no-load parameters can be used to determine the loaded gains as
follows:
Fig. 5.76 Two-port system
Fig. 5.80
Including the effects of the source resistance Rs.
Lecturer: Dr. Omar Daoud
Fig. 5.77 Substituting the internal elements for
the two-port system of Fig. 5.76
Fig. 5.79
Part I
Applying a load to the two-port system of Fig. 5.77.
1
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Applying the voltage-divider rule to the output circuit of Fig 5.79 results
in
V o  A v NL V i
 Av 
RL
RL  Ro
Vo
RL
 A v NL
Vi
RL  Ro
The fraction of the applied signal reaching the input terminals of the
amplifier of Fig 5.80 is also determined by the voltage-divider rule again

Vo
Ri

 Av NL
  Av s 
Vs
Ri  Rs
and Vo  Av  Av NL Vi 
Vi  Vs
Ri
Ri  Rs
At the existence of both of R s and R L , the voltage gain equation will be
modified as:
Av s 
Vo
Ri
RL
 Av NL

Vs
Ri  Rs RL  Ro
For the current gain
Ii  I s 
Vi
Vs

Ri Rs  Ri
 Ai   Av
Ri
RL
and Ais   Av s
Ri  Rs
RL
The larger the source resistance and/or smaller the load resistance, the less the
overall gain of an amplifier
Ex. For the given single-stage amplifier, with R =4.7
L
k and R s =0.3 k, determine: (a) Avs, (b) A v , (c) A i .
The two-port parameters for the fixed-bias
configuration are Z i =1.071k, Zo=3k, and Av =280.11.
NL
Lecturer: Dr. Omar Daoud
Part I
2
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Ex: The two-stage system of the given Fig. employed a transistor emitter-follower
configuration prior to a common-base configuration to ensure that the maximum percent
of the applied signal appears at the input terminals of the common-base amplifier. In this
Fig., the no-load values are provided for each system, with the exception of Zi and Zo for
the emitter-follower, which are the loaded values. For the given configuration, determine:
(a) The loaded gain for each stage.
(b) The total gain for the system, Av and Avs.
(c) The total current gain for the system.
(d) The total gain for the system if the emitter-follower configuration were removed.
Lecturer: Dr. Omar Daoud
Part I
3
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Ex.: For the given RC-coupled BJT amplifier given below, calculate the
following
a) the no-load voltage gain and the output voltage
b) the overall gain if a 10-k load is applied to the second stage and compare it to the
results of (a)
c) the input impedance of the first stage and the output once of the second stage.
Lecturer: Dr. Omar Daoud
Part I
4
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Note: The name of RC-coupled is derived from the fact that the coupling capacitor is combined with the input
impedance of the next stage to perform the load on the stage itself. The coupling capacitor prevents the two
stages from DC viewpoint.
Solution
a) The DC analysis of both transistors gives

 15 
VB  20
  4.7V 
VE
I
26m
 4mA  I B  E  20A, and re 
 6.5
 15  4.7 
I E 
RE

4m

VE  VB -VBE  4V

R //( Z i2  R1 // R2 // re )

Rc // RL
665.2

 102.3
 c
6.5
re
re

3
 AvT ( NL )  34.6  10
R
2.2k

Av 2   c  
 338.46

re
6.5
 Vo  AvT ( NL )  Vi  34.6  103  25  10  6  865  10 3 V
Av1  
b) The overall gain with the 10k load applied is
AvT 
Vo
RL
10
 AvT

 34.6  103  28.4  103
( NL )
Vi
RL  Z o 10  2.2
c) The input impedance of the first stage
Z i1  R1 // R2 // re  953.6
Whereas the output impedance for the second stage is
Z o2  Rc  2.2k
Lecturer: Dr. Omar Daoud
Part I
5
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Ex. 8.16: Calculate the dc
bias, voltage gain, input
output
impedance,
impedance, and resulting
output
voltage
for
the
cascade amplifier shown in
the Fig. 8.49. Calculate the
load voltage if 10-k load
is connected across the
Fig. 8.49
Cascade amplifier circuit for Example 8.16.
output.
Solution:
Using the dc biasing techniques to find the Q-values,



2

 V
plot the curve of the Shockley equation I D  I DSS 1  GS
VP


plot the dc load line from the GS loop, in this case V GS =-I S R S
From these two plots V GSQ =-1.9V and I DQ =2.8mA.

gm 
2 I DSS
VP
 VGS
1  V
P


  2.6mS

The two JFET stages are CS, thus the voltage gain for each of them is


Av1   g m RD // RL  Ri2  RG   g m RD  6.24
 AvT  38.4
Av 2   g m RD  6.24

The input impedance Z i =R G =3.3M
The output impedance Z o =R D =2.4k assuming that r d is 
The resulting output voltage V o = A v V i =384mV
The output voltage across the load resistor
VL  Vo
RL
 310 mV
RL  Z o
Ex. 8.17: For the cascade
amplifier of Fig.8.50, use the
dc bias calculated in the
previous
examples
to
calculate input impedance,
Lecturer: Dr. Omar Daoud
Part I
Fig. 8.50
6
Cascaded JFET-BJT amplifier for Example 8.17
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
output impedance, voltage gain and resulting output voltage.
Solution:
Av1   g m RD // RL  R1 // R2 // re    g m RD // 953.5  1.77 

RC
 AvT  599.1
Av 2  
 338.46

re

Vo  AvVi  0.6V
Z i  3.3M
Z o  2.2k
- Cascoded Systems:
 The cascode configuration has one of two configurations. In each case
the collector of the leading stage is connected to the emitter of the
following stage.
 The arrangements provide relatively high-input impedance with low
voltage gain for the first stage to ensure minimum input Miller
capacitance, whereas the following CB stage provides an excellent
high-frequency response.
Fig. 5.86: Cascode configuration.
Lecturer: Dr. Omar Daoud
Part I
7
Fig.5.87: Practical cascode circuit for Example 5.19.
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Ex. 5.19: Calculate the no-load voltage gain for the cascode configuration of
Fig. 5.87.
Solution:
Applying the voltage-divider rule to find the Base voltages,

4.7
4.25


VB1  18
 3.8mA
  4.95V VE  VB1  0.7  4.27V  I E 
1.1k
 4.7  5.6  6.8 

 4.7  5.6 
VB2  18
  10.8V
 4.7  5.6  6.8 
26
re 
 6.8
3.8
Note: The loading on the first transistor is the input of the second one. The
result is the replacement of R C with the input impedance of a CB configuration
(R C =r e ).

For the first stage (CE), the voltage gain could be calculated as:
Av1  

While the voltage gain for the second stage (CB) is
Av 2 

Rc
 1
re
Rc
 265
re
The overall no-load gain is
AvT  Av1 Av 2  265
Note: The CE stage provides higher input impedance than can be expected from the CB
stage.
Power Amplifier Classes:
- Class-A Power Amplifier :
 The output signal varies for a full 360° of the cycle. Thus, this requires the
Q-point to be biased at a level so that at least half the signal swing of the
Lecturer: Dr. Omar Daoud
Part I
8
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
output may vary up and down without going to a high-enough voltage to
be limited by the supply voltage level or too low to approach the lower
supply level, or 0 V in this description.
 It has a very poor efficiency, especially with small input signals, when
very little ac power is delivered to the load. In fact, the maximum
efficiency of a class A circuit, occurring between 25% to 50% which is
based on the circuit configuration. This is due to that it uses a good
amount of power to maintain bias, even with no input signal and the dc
bias is at the half of the supply voltage level.
 There are two types of configuration:
1) Series-Fed
Main Specifications:
- In this type we can use the simple
fixed-bias circuit connection as
shown in the Fig,
- To be used as a power transistor, it
is used in the range of a few to tens
of Watts,
- <100,
- Capable of handling large power or
current while not providing much
voltage gain,
- It is not the best choice to be used as a large-signal amplifier because of
its poor power efficiency.
DC Bias Operation:
-
-
-
-
The importance of the dc bias is to determine
the operating point (the intersection of the dc
bias value of IB with the dc load line).
The quiescent-point values could be calculated
as
V  0.7
I B  CC
 I C  I B
RB
VCE  VCC  I C RC
Fig. 12.3 Transistor characteristic showing
If the dc bias collector current is set at one-half load line and Q-point.
the possible signal swing (between 0 and
VCC/RC), the largest collector current swing will be possible.
If the quiescent collector–emitter voltage is set at
one-half the supply voltage, the largest voltage
swing will be possible. With the Q-point set at
this optimum bias point.
AC Operation:
Lecturer: Dr. Omar Daoud
Part I
9
Fig. 12.4 Amplifier input and output signal variation.
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
-
-
An input ac signal is applied to the amplifier, thus the output will vary from its
dc bias operating voltage and current as shown in the Fig. 12.4.
A small input signal will cause the base current to vary above and below the dc bias
point, which will then cause the collector current (output) to vary from the dc bias
point set as well as the collector–emitter voltage to vary around its dc bias value.
As the input signal is made larger, the output will vary further around the
established dc bias point until ??? (either the current or the voltage reaches a
limiting condition; for the current this limiting condition is either zero current at
the low end or VCC/RC at the high end of its swing. For the collector–emitter
voltage, the limit is either 0 V or the supply voltage, VCC).
Power Considerations:
-
-
The power into an amplifier is provided by the supply. With no input signal, the dc
current drawn is the collector bias current, ICQ, The power then drawn from the
supply is
Pi(dc)= VCCICQ
Even with an ac signal applied, the average current drawn from the supply remains
the same, so that it represents the input power supplied to the class A series-fed
amplifier.
Output Power:
-
The larger the input signal, the larger the output swing, up to the maximum set by
the circuit.
The ac power delivered to the load (RC) can be expressed in a number of ways.
a) Using rms signals:
b) Using peak signals:
c) Using peak-to-peak signals:
Lecturer: Dr. Omar Daoud
Part I
10
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Efficiency:
-
The efficiency of an amplifier represents the amount of ac power delivered
(transferred) from the dc source.
-
Maximum efficiency could be calculated as follows:
 The maximum power output can be calculated as
VCE max  VCC 
2
VCC

P

V  o ( ac ) max
I C max  CC 
8RC
RC 
 The maximum power input can be calculated using the dc bias current set to
one-half the maximum value:
VCC
2
RC VCC

Pi ( dc ) max  VCC  I C max  VCC 
2
2 RC

The maximum efficiency is
The maximum efficiency of a class A series-fed amplifier is thus seen to be 25%.
Since this maximum efficiency will occur only for ideal conditions of both voltage
swing and current swing, most series-fed circuits will provide efficiencies of
much less than 25%.
Ex. Calculate the input power, output power, and efficiency of the amplifier
circuit in the given Fig. below for an input voltage that result in a base current
of 10 mA peak.
Lecturer: Dr. Omar Daoud
Part I
11
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Solution:
The Q-point can be determined to be
2) Transformer-Coupled
Main Specifications:
- A form of class A amplifier having
maximum efficiency of 50% uses a
transformer to couple the output signal
to the load as shown in Fig.
Lecturer: Dr. Omar Daoud
Part I
12
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Operation of Amplifier Stage:
a) DC Load line
-
-
-
The
transformer
(dc)
winding
resistance
determines the dc load line
for the circuit. Typically,
this dc resistance is small
(ideally=0) and, as shown
in the given Fig., a 0 dc
load line is a straight
vertical line.
A practical transformer
winding resistance would
be a few ohms, but only the
ideal
case
will
be
considered
in
this
discussion.
There is no dc voltage drop
across the 0 dc load
resistance, and the load line is drawn straight vertically from the
voltage point, VCEQ = VCC.
b) Signal Swing and Output AC Power
-
The ac power developed across the transformer primary can be calculated
using
The ac power calculated is that developed across the primary of the
transformer. Assuming an ideal transformer (a highly efficient transformer
has an efficiency of well over 90%), the power delivered by the secondary to
the load is approximately that calculated using the previous Eq.
-
The output ac power can also be determined using the voltage delivered to the
load.
 The voltage delivered to the load can be calculated
Lecturer: Dr. Omar Daoud
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Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky

The power across the load can then be expressed as

The output ac power then calculated using
where the load current
Ex. Calculate the ac power delivered to the 8 speaker for the given circuit. The
circuit component values result in a dc base current of 6 mA, and the input signal
(Vi) results in a peak base current swing of 4 mA.
Lecturer: Dr. Omar Daoud
Part I
14
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Efficiency:
- The input (dc) power obtained from the supply is calculated from
the supply dc voltage and the average power drawn from the supply:
Pi(dc) = VCCICQ
Lecturer: Dr. Omar Daoud
Part I
15
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
-
For the transformer-coupled amplifier, the power dissipated by the
transformer is small (due to the small dc resistance of a coil) and
will be ignored in the present calculations. Thus the only power loss
considered here is that dissipated by the power transistor (as a heat)
and calculated using.
PQ = Pi(dc) - Po(ac)
- For a class A transformer-coupled amplifier, the maximum
theoretical efficiency goes up to 50%. Based on the signals obtained
using the amplifier, the efficiency can be expressed as
The larger the value of VCEmax and the smaller the value of
VCEmin, the closer the efficiency approaches the theoretical limit
of 50%.
Ex. For the circuit in the previous example, calculate the dc input power, power dissipated by the
transistor, and efficiency.
Solution:
Ex. Calculate the efficiency of a transformer-coupled class A amplifier for a supply of 12 V and
outputs of:
(a) V(p) = 12 V.
(b) V(p) = 6 V.
(c) V(p) =2 V.
Solution:
Lecturer: Dr. Omar Daoud
Part I
16
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
- Class-B Power Amplifier
 A class B circuit provides an
output signal varying over onehalf the input signal cycle, or
for 180° of signal.
 The dc bias point for class B is
therefore at 0 V, with the
output then varying from this
bias point for a half-cycle.
 Obviously, the output is not a
faithful reproduction of the
input if only one half-cycle is present. Two class B operations—one to
provide output on the positive-output half-cycle and another to provide
operation on the negative-output half-cycle are necessary. The combined
half-cycles then provide an output for a full 360° of operation (This type
of connection is referred to as push-pull operation).
 Class B operation, with no dc bias power for no input signal, can be
shown to provide a maximum efficiency that reaches 78.5%.
Input (DC) Power:
The amount of this input power can be calculated using
Pi(dc) = VCCIdc
where I dc is the average or dc current drawn from the power supplies.
Note: In class B operation, the current drawn from a single power supply has
the form of a full-wave rectified signal, while that drawn from two power
supplies has the form of a half-wave rectified signal from each supply.
In either case, the value of the average current drawn can be expressed as
Then the dc power input results in
Output (AC) Power:
The output power can be calculated as
Lecturer: Dr. Omar Daoud
Part I
17
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Efficiency:
(using I(p)=V L (p)/R L ). The previous equation shows that the larger the peak voltage, the
higher the circuit efficiency, up to a maximum value when V L (p)=V CC , this maximum
efficiency then being
Power Dissipated by Output Transistor:
The power dissipated (as heat) by the output power transistors is the difference between
the input power delivered by the supplies and the output power delivered to the load.
P2Q= Pi(dc) - Po(ac)
where P2Q is the power dissipated by the two output power transistors. The dissipated
power handled by each transistor is then half of the P2Q.
Ex. For a class B amplifier providing a 20-V peak signal to a 16 load (speaker) and a
power supply of VCC = 30 V, determine the input power, output power, and circuit
efficiency.
Lecturer: Dr. Omar Daoud
Part I
18
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Maximum Power Considerations:
For class B operation, the maximum output power is delivered to the load when V L(p) =
VCC:
The corresponding peak ac current I(p) is then
so that the maximum value of average current from the power supply is
Using this current to calculate the maximum value of input power results in
The maximum power dissipated by the two output transistors occurs when the output
voltage across the load is
for a maximum transistor power dissipation of
Ex. For a class B amplifier using a supply of VCC=30 V and driving a load of 16,
determine the maximum input power, output power, and transistor dissipation.
Lecturer: Dr. Omar Daoud
Part I
19
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Ex. Calculate the efficiency of a class B amplifier for a supply voltage of VCC =24 V
with peak output voltages of:
(a) VL(p) = 22 V.
(b) VL(p) = 6 V.
- Class-AB Power Amplifier :
 An amplifier may be biased at a dc level above
the zero base current level of class B and
above one-half the supply voltage level of
class A; this bias condition is class AB. This is
to reduce the crossover distortion that
happened in class B.
 Class AB operation still requires a push-pull
connection to achieve a full output cycle, but
the dc bias level is usually closer to the zero
base current level for better power efficiency,
as described shortly.
 For class AB operation, the output signal
swing occurs between 180° and 360° and is
neither class A nor class B operation.
 The average power supplied by each source
and the average power dissipated in each
transistor are larger than the one for class B,
which results in less power efficiency.
Power Considerations:
- Each transistor draws current for a half-cycle, then
the dc current is
I
I dc  C

Then the input power delivered by the source is
V I
Pi ( dc )  VCC I dc  CC C

-
The ac output power could be calculated as
vCEQ I C VCC I C
Po ( ac ) rms  vo io  Po ( ac ) p 


4
2
2
Lecturer: Dr. Omar Daoud
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20
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Efficiency:
- Class-C Power Amplifier :

The output of a class C amplifier is biased for operation at less than
180° of the cycle and will operate only with a tuned (resonant)
circuit, which provides a full cycle of operation for the tuned or
resonant frequency. This operating class is therefore used in special
areas of tuned circuits, such as radio or communications.
 The power dissipated of the transistor is low because it is ON for a
small percentage only of the input cycle.
The Basic Concept of Operation:
 A common emitter class C amplifier with a resistive load is
shown in the given figure.
 It is biased below cutoff with the negative V BB supply. The ac
source has a peak value that is slightly greater than V BB +V BE so
that the base voltage exceeds the barrier potential of the BEjunction for a short time near the positive peak of each cycle.
 During this short interval the transistor is turned ON and then
the ideal maximum collector current is I C(sat) and the ideal
minimum collector voltage is V CE(sat) .
The Power Dissipation:

If the output swings over the entire load, the maximum collector current is
I C(sat) and the ideal minimum collector voltage is V CE(sat) , therefore the power
dissipation during the ON could be defined as
Lecturer: Dr. Omar Daoud
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21
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
P D(ON) = I C(sat) V CE(sat)
t 
t
PD ( avg )   on  PD ( on )   on
T
T 

 I C ( sat )VCE ( sat )

Ex. A Class C amplifier is driven by a 200kHz signal. The transistor is ON for 1s,
and the amplifier is operating over 100 percent of its load line. If the I C(sat) =100mA
and V CE(sat) =0.2V, what is the average power dissipation?
Solution:
T
 1s 
1
100mA 0.2V   4mV
 5s  PD ( avg )  
200kHz
 5s 
Tuned Operation:

The resistively loaded Class C power amplifier is of no value in linear
applications. ???? (The output is not a replica of the input). Thus, class C with
parallel resonant circuit appears as shown in the figure.

The short pulse of collector current on each cycle of the input initiates and
sustains the oscillation of the tank circuit so that the output sinusoidal voltage
is produced.
Lecturer: Dr. Omar Daoud
Part I
22
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky



The resonant frequency of the circuit is determined by the formula of
1
fr 
.
2 LC
The current pulse charges the capacitor to approximately V CC . After the pulse,
the capacitor quickly discharges, thus charging the inductor. Then, after the
capacitor completely discharges, the inductor's magnetic field collapses and
then quickly recharges C to near V CC in a direction opposite to the previous
charge (This completes one half-cycle of the oscillation).
The capacitor discharges again, increasing the inductor's magnetic field. The
inductor then quickly recharges the capacitor back to a positive peak slightly
less than the previous one??? (due to energy loss in the winding resistance),
which completes one full cycle and then the peak-to-peak voltage is therefore
approximately equal to 2V CC .
Note: The amplitude of each successive cycle of the oscillation is less than that of
the previous cycle ??? (Because of energy loss in the resistance of tank
circuit) and the oscillation will eventually die out. However, the regular
recurrence of the collector pulse re-energizes the resonant circuit and
sustains the oscillation at constant amplitude.
Lecturer: Dr. Omar Daoud
Part I
23
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky

When the tank circuit is tuned to the frequency of the input signal, reenergizing occurs on each cycle of the tank. A class C amplifier operates as a
frequency multiplier. By tuning the resonant tank circuit to higher harmonics.
Lecturer: Dr. Omar Daoud
Part I
24
Module: Electronics II
Module Number: 650321
th
Electronic Devices and Circuit Theory, 9 ed., Boylestad and Nashelsky
Maximum Output Power and Efficiency:
U

The voltage developed across the tank circuit has a peak-to-peak value of
approximately 2V CC , the maximum output power can be expressed as:
2
0.707VCC 2 VCC2
Vrms


Pout 
RC
RC
2 RC
where R C is equivalent parallel resistance of the collector tank circuit and
represents the parallel combination of the coil resistance and the load
resistance.
The total power that must be supplied to the amplifier is
P T =P out +P D(avg)
R
R

R
R
R
R
R
R
R
Therefore, the efficiency is

Pout
, when Pout  PD ( avg )  the class C efficiency closely approaches 1
Pout  PD ( avg )
- Class-D Power Amplifier :
 This operating class is a form of amplifier operation using pulse (digital)
signals, which are on for a short interval and off for a longer interval.
 Using digital techniques makes it possible to obtain a signal that varies
over the full cycle (using sample-and-hold circuitry) to recreate the
output from many pieces of input signal.
 The major advantage of class D operation is that the amplifier is on
(using power) only for short intervals and the overall efficiency can
practically be very high.
 Class D operation can achieve power efficiency over 90% and provides
the most efficient operation of all the operating classes.
Lecturer: Dr. Omar Daoud
Part I
25