ECE2020 Digital System Design Lecture 14: FSM Digital Designs Prof. Youngtak Lee School of Electrical and Computer Engineering Georgia Tech Today’s agenda • Test #3 Scheduled on: – 4/5 Tuesday • Homework #6 due Thursday this week (3/31) 2 2 Homework #5 Q1 3 3 Homework #5 Q2 4 4 Homework #5 Q3 5 5 Homework #5 Q4 6 6 Today we will explore: • Logic circuits design steps • State diagram implementation • State table implementation • Examples 7 7 Recap: Sequential Circuits Introduction • With the descriptions of a FSM as a state diagram and a state table, the next question is how to develop a sequential circuit, or logic diagram from the FSM • Effectively, we wish to form a circuit as follows 8 8 Logic Circuits Design Steps • Generate a Boolean function for – Each external output – Each state encoded bit • Simplify the Boolean functions • Draw a D F/F (or register) for each state encoded bit • Draw logic circuits for – – – – 9 External outputs Each inputs of state encoded bits Input of state encoded bits = the next state Output of state encoded bits = the current state 9 Sequential Circuits from State Table • The procedure for developing a logic circuit from a state table is the same as with a regular truth table! – Generate Boolean functions for • Each external outputs using external inputs and present state bits • Each next state bit using external inputs and present state bits – Use Boolean algebra, K-maps, etc. to simplify – Draw a D F/F for each state bit – Draw logic diagram components connecting external outputs to external inputs and outputs of state bit registers (which have the present state) – Draw logic diagram components connecting inputs of state bits (for next state) to the external inputs and outputs of state bit registers (which have the present state) 10 10 Logic Circuits Design Example 1 Get together with your peers and create K-maps and Boolean expressions for them! Present State P1 P0 0 0 0 Next State X Z N1 N0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 X X P1P0 N1 00 01 11 10 0 0 0 0 1 1 0 1 0 1 P1P0 N1 XP1P0 P1P0 N0 00 01 11 10 0 0 0 0 1 N0 XP1P0 XP1P0 XP1P0 1 1 0 1 0 X(P1 P0 ) XP1P0 Z XP1P0 11 11 Logic Circuits Design Example 1 N0 X(P1 P0 ) XP1P0 Z XP1P0 N1 XP1P0 P1P0 X N0 D0 F/F P0 1 2 N1 D1 F/F Z P1 1 2 12 12 Seq. Circuits Pattern Detect Example • Following the procedure outlined, Boolean functions for the pattern detector state table can be formed using K-maps as follows. 13 13 Seq. Circuits Pattern Detect Example • Notice that the previous Boolean functions can also be expressed with time as follows • An important thing to note in these equations is the relation between the present states P and the next states N 14 14 Sequential Circuits – Pattern Detect Example • The following logic circuit implements the pattern detect example Get together with your peers and create logic circuit implementations! 15 15 FSM Example #1 • Consider the following system description • Input: X(t) {a, b, c} • Output: Z(t) {q, p} q, when input sequence has even # of a' s and odd # of b' s Z(t) p, Otherwise 16 16 FSM Examples #1 • We can begin forming a state machine for the system description by reviewing the possible states. In addition, assign each state a state name – – – – SEE: even # of a’s and even # of b’s / output is p SEO: even # of a’s and odd # of b’s / output is q SOO: odd # of a’s and odd # of b’s / output is p SOE: odd # of a’s and even # of b’s / output is p • Note that this machine can be a Moore machine. So, we can associate the output with each state 17 17 State Diagram q, when input sequence has even # of a' s and odd # of b' s Z(t) p, Otherwise Get together with your peers and create the state diagram! b c a c SEE/p b C SEO/q b SOO/p a b SOE/p c a a A Moore Machine 18 18 FSM Examples #1 • A state table can also be formed for this state diagram as follows – First, assign a binary number to each state • i.e.) SEE = 00, SEO = 01, SOO = 10, SOE = 11 – Assign a binary number to each input • i.e.) a = 00, b = 01, c = 10 – Assign a binary number to each output • i.e.) p = 0, q = 1 – Then for each state, find the next state for each input. In this case there are three possible input values, so three possible state transitions from each state • Let’s create the state table on the following slide 19 19 State Table b c a c 00/p b b 01/q 10/p a = 00 b = 01 c = 10 p=0 q=1 20 11/p b a a SEE = 00 SEO = 01 SOO = 10 SOE = 11 What does a state table look like? Create a state table! C c a Present State Input (a, b, c) Next State Output P1 P0 X1 X0 N1 N0 Z 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 0 20 Vending Machine State Machine • Dispense a Coke when depositing 15 ¢ • Inputs – 5 = a nickel – 10 = a dime – BC = bad coin (including quarters in this example) • Outputs – R = reject – C = coke – N = no coke 21 21 State Diagram 5/N BC/R 0¢ 10/C 5¢ BC/R 5/C 10/N 10/C 5/N 10 ¢ BC/R 22 22 State Table Present State (0¢, 5¢, 10¢) 5/N BC/R 0¢ (00) 10/C 5/C 10/N 5¢ (01) 10/C 5/N 10 ¢ (10) BC/R 5: 00 10: 01 BC: 10 23 N: 00 C: 01 R: 10 BC/R Input (5¢, 10¢ , BC) Next State (0¢, 5¢, 10¢) Output (C, N, R) P1 P0 X1 X0 N1 N0 C1 C0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 X X 1 1 X X X X 1 1 X X X X X X 23 Logic Circuits Design Get together with your peers and create K-maps and Boolean expressions for N1 and N0! Present State 24 Input Next State 01 11 10 00 0 1 X 0 01 1 0 X 0 P1P0 Output N1 X1X0 00 P1 P0 X1 X0 N1 N0 C1 C0 11 X X X X 0 0 0 0 0 1 0 0 10 0 0 X 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 N1 P0 X 1X 0 P1P0X 0 P1X 1 P1P0 N0 X1X0 00 01 11 10 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 00 1 0 X 0 1 0 0 0 0 0 0 1 01 0 0 X 1 1 0 0 1 0 1 0 1 11 X X X X 1 0 1 0 1 0 1 0 10 0 1 X 0 X X 1 1 X X X X 1 1 X X X X X X N0 P1P 0 X 1X 0 P1X 0 P 0 X 1 24 Logic Circuits Design Get together with your peers and create K-maps and Boolean expressions for C1 and C0! Present State 25 Input Next State P1 P0 X1 X0 N1 N0 C1 C0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 0 1 X X 1 1 1 1 X X 01 11 10 00 0 0 X 1 01 0 0 X 1 11 X X X X 10 0 0 X 1 P1P0 Output C1 X1X0 00 C1 X1 C0 X1X0 00 01 11 10 00 0 0 X 0 1 01 0 1 X 0 0 1 11 X X X X 0 1 0 10 1 1 X 0 X X X X X X X X P1P0 C0 P1X1 P0X0 25 Logic Circuits of the Vending Machine Logic circuit implementation? N1 P0X1X0 P1P0X0 P1X1 C1 X1 C0 P1X1 P0X0 N0 P1P0 X1X0 P1X0 P0X1 X1 X0 P1 P0 N0 D0 F/F P0 1 2 N1 D1 F/F P1 1 2 C0 C1 26 26 Summary • We covered various examples of state machine and state diagrams – Logic circuits design steps – State diagram implementation – State table implementation – Examples • Next class (Thursday 3/31): – FSM Architecture 27 27