Summary Tables Supplement
Table 1.1
The Four Amplifier Types
Type
Voltage Amplifier
Circuit Model
Gain Parameter
Ideal Characteristics
Open-Circuit Voltage Gain
v Av o ≡ o (V/V)
vi i =0
Ri = ∞
Ro = 0
o
Current Amplifier
Short-Circuit Current Gain
i (A/A)
Ais ≡ o i
vo =0
i
Transconductance
Amplifier
Short-Circuit Transconductance
i Gm ≡ o (A/V)
v
i
Transresistance
Amplifier
Ri = 0
Ro = ∞
Ri = ∞
Ro = ∞
vo =0
Open-Circuit Transresistance
v Rm ≡ o (V/A)
ii i =0
Ri = 0
Ro = 0
o
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ST-1
ST-2 Summary Tables Supplement
Table 1.2
Frequency Response of STC Networks
Low-Pass (LP)
High-Pass (HP)
Transfer Function T(s)
K
1 + (s/ω0 )
Ks
s + ω0
Transfer Function (for physical
frequencies) T( jω)
K
1 + j(ω/ω0 )
K
1 − j(ω0 /ω)
Magnitude Response |T( jω)|
|K|
1 + (ω/ω0 )2
|K|
1 + (ω0 /ω)2
Phase Response ∠T( jω)
− tan (ω/ω0 )
tan (ω0 /ω)
Transmission at ω = 0 (dc)
K
0
Transmission at ω = ∞
0
K
3-dB Frequency
Bode Plots
Table 2.1
1.
2.
3.
4.
5.
−1
−1
ω0 = 1/τ ; τ ≡ time constant
τ = CR or L/R
in Fig. 1.23
in Fig. 1.24
Characteristics of the Ideal Op Amp
Infinite input impedance
Zero output impedance
Zero common-mode gain or, equivalently, infinite common-mode rejection
Infinite open-loop gain A
Infinite bandwidth
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Summary Tables Supplement ST-3
Table 3.1
Summary of Important Semiconductor Equations
Quantity
Relationship
Values of Constants and Parameters (for
Intrinsic Si at T = 300 K)
15
−3
−3/2
Carrier concentration in
−3
intrinsic silicon (cm )
ni = BT e
B = 7.3 × 10 cm K
Eg = 1.12 eV
k = 8.62 × 10−5 eV/K
10
3
ni = 1.5 × 10 /cm
Diffusion current
2
density (A/cm )
dp
Jp = −qDp
dx
dn
Jn = qDn
dx
q = 1.60 × 10
2
Dp = 12 cm /s
Dn = 34 cm2 /s
Drift current density
2
(A/cm )
Resistivity ( · cm)
Relationship between
mobility and diffusivity
3/2 −Eg /2kT
−19
coulomb
Jdrift = q pμp + nμn E
μp = 480 cm2 /V · s
2
μn = 1350 cm /V · s
ρ = 1/ q pμp + nμn
μp and μn decrease with the increase in
doping concentration
Dp
Dn
=
= VT
μn
μp
VT = kT/q 25.9 mV
Carrier concentration in
−3
n-type silicon (cm )
nn0 ND
2
pn0 = ni /ND
Carrier concentration in
p-type silicon (cm−3 )
pp0 NA
2
np0 = ni /NA
Junction built-in
voltage (V)
V0 = VT ln
Width of depletion
region (cm)
xn N A
=
xp ND
W = xn + xp
2es 1
1 =
+
V0 + VR
q NA ND
N A ND
n2i
es = 11.7e0
−14
e0 = 8.854 × 10 F/cm
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ST-4 Summary Tables Supplement
Table 3.1
continued
Quantity
Charge stored in depletion
layer (coulomb)
Relationship
QJ = q
Values of Constants and Parameters (for
Intrinsic Si at T = 300 K)
NA ND
AW
NA + N D
I = Ip + I n
Dp
2
Forward current (A)
Ip = Aqni
2
In = Aqni
Saturation current (A)
I–V relationship
IS =
Lp ND
Dn
eV/VT − 1
Ln NA
Aqn2i
τp = Lp2 /Dp
Minority-carrier
charge storage
(coulomb)
Qp = τp Ip
Dn
+
Lp ND Ln NA
τn = Ln2 /Dn
Lp , Ln = 1 µm to 100 µm
4
τp , τn = 1 ns to 10 ns
Qn = τn In
Q = Qp + Qn = τT I
es q
N A ND
2
NA + N D
V m
Cj = Cj0
1+ R
V0
τT
Cd =
I
VT
Cj0 = A
Diffusion
capacitance (F)
Dp
V/V
I = IS e T − 1
Minority-carrier
lifetime (s)
Depletion capacitance (F)
eV/VT − 1
1
V0
m=
1
1
to
3
2
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Summary Tables Supplement ST-5
Table 4.1
Exact
Diode models
i = IS (ev/Vr − I),
VT =
kT
q
−5
−23
k = Boltzmann’s constant = 8.62 × 10 eV/K = 1.38 × 10 J/K
T = the absolute temperature in Kelvin = 273 + temperature in °C
q = the magnitude of electronic charge = 1.60 × 10−19 coulomb
I
V2 − V1 = 2.3 VT log I2
1
Constant
voltage drop
model
i
vD
i > 0, vD = 0.7 V
IZ
Reverse bias
model
VZ0
VZ VZ0 rz IZ
VZ
rz
Small-signal
model
rd =
VT
ID
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ST-6 Summary Tables Supplement
Table 5.1
Regions of Operation of the Enhancement NMOS Transistor
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Summary Tables Supplement ST-7
Table 5.2
Regions of Operation of the Enhancement PMOS Transistor
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ST-8 Summary Tables Supplement
Table 6.1
BJT Modes of Operation
Mode
EBJ
CBJ
Cutoff
Active
Saturation
Reverse
Forward
Forward
Reverse
Reverse
Forward
Table 6.2
v
Summary of the BJT Current–Voltage Relationships in the Active Mode
/V
iC = IS e BE T
I
i
iB = C = S evBE /VT
β
β
IS vBE /VT
iC
iE =
=
e
α
α
Note: For the pnp transistor, replace vBE with vEB .
iC = αiE
iB = (1 − α)iE =
iC = βiB
α
β=
1−α
iE
β +1
iE = (β + 1)iB
β
α=
β +1
kT
25 mV at room temperature
VT = thermal voltage =
q
Table 6.3
Simplified Models for the Operation of the BJT in DC Circuits
npn
Active
EBJ:
Forward
Biased
pnp
E
IB
B
VBE
C
0.7 V
bIB
VCE 0.3 V
CBJ:
Reverse
Biased
VEB
bIB
VEC 0.3 V
B
E
C
IB
IC
IB
Saturation
B
EBJ:
Forward
Biased
VBE 0.7 V
CBJ:
Forward
Biased
0.7 V
bforced IB
E
C
VCEsat
0.2 V
VEB
0.7 V
B
E
IB
VECsat
0.2 V
C
IC = bforcedIB
βforced < βmin
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Summary Tables Supplement ST-9
Table 7.1
1.
Systematic Procedure for the Analysis of Transistor Amplifier Circuits
Eliminate the signal source and determine the dc operating point of the transistor.
2. Calculate the values of the parameters of the small-signal model.
3.
Eliminate the dc sources by replacing each dc voltage source by a short circuit and each dc current source
by an open circuit.
4.
Replace the transistor with one of its small-signal, equivalent-circuit models. Although any of the models
can be used, one might be more convenient than the others for the particular circuit being analyzed. This
point is made clearer in Section 7.3.
5. Analyze the resulting circuit to determine the required quantities (e.g., voltage gain, input resistance).
Table 7.2
Small-Signal Models of the MOSFET
Small-Signal Parameters
NMOS transistors
Transconductance:
g = μ C WV
L
=
2I
2μ C W I =
V
L
Output resistance:
r = V /I = 1/λI
PMOS transistors
Same formulas as for NMOS except using |V
|, V , | λ| and replacing μ with μ .
Small-Signal , Equivalent-Circuit Models
D
D
i
g v
G
D
v
g v
r
S
Hybrid-π model
G
r
G
1
g
v
r
1
g
i
S
S
T models
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ST-10 Summary Tables Supplement
Table 7.3
Small-Signal Models of the BJT
Hybrid-π Model
gm vπ Version
βib Version
i
B
C
v
r
g v
B
C
r
r
r
i
E
E
T Model
gm vπ Version
αi Version
C
C
i
gmv
B
ro
v
B
ro
re
re
i
E
E
Model Parameters in Terms of DC Bias Currents
gm =
IC
VT
re =
VT
V
=α T
IE
IC
rπ =
β
gm
rπ =
VT
V
=β T
IB
IC
gm +
1
1
=
rπ
re
ro =
V A
IC
In Terms of gm
α
gm
re =
In Terms of re
gm =
α
re
rπ = (β + 1)re
Relationships between α and β
β=
α
1−α
α=
β
β +1
β +1 =
1
1−α
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Summary Tables Supplement ST-11
Table 7.4
a,b
Characteristics of MOSFET Amplifiers
Characteristics
Amplifier type
Rin
Av o
Ro
Av
Common source (Fig. 7.36)
∞
−gm RD
RD
−gm RD RL
−gm RD RL
Common source with Rs (Fig. 7.38)
∞
−
−gm RD RL
1 + gm Rs
−
g m RD R L
1 + gm Rs
RD R L
1/gm + Rs
−
RD RL
1/gm + Rs
gm RD
1 + gm Rs
RD
−
Gv
Common gate (Fig. 7.40)
1
gm
gm RD
RD
g m RD R L
RD RL
Rsig + 1/gm
Source follower (Fig. 7.43)
∞
1
1
gm
RL
RL + 1/gm
RL
RL + 1/gm
a
b
For the interpretation of Rin , Av o , and Ro , refer to Fig. 7.35(b).
The MOSFET output resistance ro is not taken into account in these formulas.
Table 7.5
a,b,c
Characteristics of BJT Amplifiers
Common
emitter
(Fig. 7.37)
Common
emitter with
Re (Fig. 7.39)
Common base
(Fig. 7.41)
Rin
Av o
Ro
Av
(β + 1)re
−gm RC
RC
−gm RC RL
−α
(β + 1) re + Re
−
gm RC
1 + gm Re
RC
re
gm RC
RC
Emitter
follower
(Fig. 7.44)
(β + 1) re + RL
1
re
R C RL
Rsig + (β + 1)re
−β
RC R L
Rsig + (β + 1) re + Re
RC RL
re + Re
gm RC RL
α
−β
R C RL
re
−gm RC RL
1 + gm Re
−α
Gv
RC RL
re
RL
RL + re
α
RC RL
Rsig + re
RL
RL + re + Rsig /(β + 1)
Gv o = 1
Rout = re +
a
Rsig
β +1
For the interpretation of Rm , Av o , and Ro refer to Fig. 7.35.
The BJT output resistance ro is not taken into account in these formulas.
c Setting β = ∞ (α = 1) and replacing r with 1/g , R with R , and R with R results in the corresponding formulas for MOSFET amplifiers
e
m C
D
e
s
(Table 7.4).
b
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ST-12 Summary Tables Supplement
Table 8.1
Gain Distribution in the MOS Cascode Amplifier for Various Values of RL
Case
RL
Rin2
Rd1
Av1
Av2
1
∞
ro
3
ro
4
0.2r0
ro
2
gm
1.2
gm
ro /2
2
gm
1.2
gm
−gm ro
1
− gm ro
2
−2
gm ro
2
∞
gm ro ro
−1.2
0.17(gm ro )
Av
2
− gm ro
2
1
− gm ro
2
− gm ro
gm ro
1
g r
2 m o
−0.2(gm ro )
Table 10.1 The MOSFET High-Frequency Model
Model
Cgd
G
D
Cgs
Vgs
gmVgs
ro
gmbVbs
Cdb
Csb
Vbs
S
B
Model Parameters
gm = μn Cox
gmb = χ gm ,
W V =
L OV
2μn Cox
2I
D
V Csb =
Csb0
V 1 + SB
V0
Cdb =
Cdb0
V 1 + DB
V0
OV
χ = 0.1 to 0.2
ro = VA /ID
Cgs =
W
I =
L D
2
WLCox + WLov Cox
3
Cgd = WLov Cox
fT =
gm
2π(Cgs + Cgd )
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Summary Tables Supplement ST-13
Table 10.2 The BJT High-Frequency Model
gm = IC /VT
Cπ + C μ =
gm
2π fT
Cμ = Cjc0 1 +
m
V CB
V0c
ro = VA /IC
rπ = β0 /gm
Cπ = Cde + Cje
Cde = τF gm
Cje 2Cje0
m = 0.3−0.5
Table 11.1 Summary of the Parameters and Formulas for the Ideal
Feedback-Amplifier Structure of Fig. 11.1
• Open-loop gain ≡ A
• Feedback factor ≡ β
• Loop gain ≡ Aβ (positive number)
• Amount of feedback ≡ 1 + Aβ
x
A
• Closed-loop gain ≡ Af = o =
xs
1 + Aβ
Aβ
• Feedback signal ≡ xf =
x
1 + Aβ s
• Input signal to basic amplifier ≡ xi =
• Af |ideal =
1
x
1 + Aβ s
1
β
1
:A =
β f
1
1
• For A = ∞, xi = 0, xf = xs , xo = xs , Af = Af |ideal =
β
β
• For large loop gain, Aβ 1,
• Closed-loop gain as a function of the ideal value
Af 1
β
xf xs
1
β
1
1 + 1/Aβ
xi 0
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Feedback
Topology
Series–Shunt
Shunt–Series
Series–Series
Shunt–Shunt
Feedback
Amplifier
Voltage
Current
Transconductance
Transresistance
Ii
Vi
Ii
Vi
xi
Vo
Io
Io
Vo
xo
If
Vf
If
Vf
xf
Is
Vs
Is
Vs
xs
Vo
Ii
Io
Vi
Io
Ii
If
Io
Vs
Vo
Is
If
Vo
Io
Vf
Io
Io
Is
Vo
Vs
Vf
Vo
Vi
Vo
Af
β
A
Norton
Thévenin
Norton
Thévenin
Source
Form
By shortcircuiting
port 2 of
feedback
network
By opencircuiting
port 2 of
feedback
network
By opencircuiting
port 2 of
feedback
network
By shortcircuiting
port 2 of
feedback
network
At Input
By shortcircuiting
port 1 of
feedback
network
By opencircuiting
port 1 of
feedback
network
By shortcircuiting
port 1 of
feedback
network
By opencircuiting
port 1 of
feedback
network
At Output
Loading of Feedback
Network Is Obtained
Table 11.2 Summary of Relationships for the Four Feedback-Amplifier Topologies
a voltage,
and find the
short-circuit
current at
port 1
a current,
and find the
open-circuit
voltage at
port 1
a current,
and find the
short-circuit
current at
port 1
a voltage,
and find the
open-circuit
voltage at
port 1
To Find β,
Apply to
Port 2 of
Feedback
Network
Ri
1 + Aβ
Ri (1 + Aβ)
Ri
1 + Aβ
Ri (1 + Aβ)
Ri f
Ro
1 + Aβ
Ro (1 + Aβ)
Ro (1 + Aβ)
Ro
1 + Aβ
Rof
11.25
11.26
11.21
11.22
11.28
11.29
11.14
11.16
Refer
to Figs.
ST-14 Summary Tables Supplement
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Summary Tables Supplement ST-15
Table 16.1 Important Parameters of the VTC of the Logic Inverter (Refer to Fig. 16.13)
VOL :
VOH :
VIL :
VIH :
NML :
NMH :
Output low level
Output high level
Maximum value of input interpreted by the inverter as a logic 0
Minimum value of input interpreted by the inverter as a logic 1
Noise margin for low input = VIL – VOL
Noise margin for high input = VOH – VIH
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ST-16 Summary Tables Supplement
Table 17.1 Implications of Device and Voltage Scaling
Parameter
Relationship
Scaling Factor
1
W, L, tox
1/S
2
VDD , Vt
1/S
3
Area/Device
4
Cox
5
kn , kp
μn Cox , μp Cox
S
6
Cgate
WLCox
1/S
7
tP (intrinsic)
αC/k VDD
1/S
8
Energy/Switching cycle
(intrinsic)
2
CVDD
1/S3
9
Pdyn
2
fmax CVDD
=
Power density
Pdyn /Device area
WL
1/S
ox /tox
2
S
2
10
CVDD
2tP
1/S2
1
Table 17.2 Summary of Important Speed and Power Characteristics of the CMOS Logic Inverter
Propagation Delay
Using average currents (Fig. 17.4):
αn C
2
where αn =
2
k (W/L)n VDD
7 3Vtn
Vtn
−
+
4 VDD
VDD
αp C
2
tPLH where αp =
kp (W/L)p VDD
7 3|Vtp |
|Vtp |
−
+
4
VDD
VDD
tPHL n
2
Using equivalent resistances (Fig. 17.5):
Reff ,N (Weff /Leff )
(Wn /Ln )
Reff ,P (Weff /Leff )
tPLH = 0.69RP C where RP =
(Wp /Lp )
tPHL = 0.69RN C where RN =
For a ramp-input signal, tPHL RN C and tPLH RP C.
Power Dissipation
2
Pdyn = fCVDD
PDP = PD × tP
EDP = PDP × tP
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Summary Tables Supplement ST-17
Table G.3
Comparison of MOSFET and the BJT
NMOS
Circuit Symbol
iG vGD
vGS
To Operate in
the Active Mode,
Two Conditions
Have to Be
Satisfied
Low-Frequency,
Hybrid-π Model
iD
vDS
iB vBC
iC
vCE
vBE
(1) Induce a channel:
(1) Forward-bias EBJ:
vGS ≥ Vt ,
vBE ≥ VBEon ,
Let
Vt = 0.3–0.5 V
VBEon 0.5 V
vGS = Vt + vOV
(2) Pinch-off channel at drain:
(2) Reverse-bias CBJ:
vGD < Vt
vBC < VBCon ,
or equivalently,
or equivalently,
vDS ≥ VOV ,
Current–Voltage
Characteristics in
the Active Region
npn
vCE ≥ 0.3 V
VOV = 0.1–0.3 V
2
v
W
1
v − Vt
1 + DS
μC
2 n ox L GS
VA
v
W 2
1
= μn Cox vOV 1 + DS
2
L
VA
VBCon 0.4 V
iD =
iC = IS evBE /VT 1 +
iG = 0
iB = iC /β
G
D
gmvgs
vgs
B
ro
VA
C
vp
vCE
rp
gmvp
S
Low-Frequency
T Model
E
D
C
1i
ai
ro
G
S
ro
ro
B
i
i
rs g1
m
re ga
m
E
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ST-18 Summary Tables Supplement
Table G.3
continued
NMOS
npn
gm = ID / VOV /2
Transconductance
gm
gm = IC /VT
W
VOV
gm = μn Cox
L
W
gm u 2 μn Cox
I
L D
ro = VA /ID =
Output Resistance
ro
VA L
ro = VA /IC
ID
A0 = VA / VOV /2
Intrinsic Gain
A0 ≡ gm ro
A0 = VA /VT
2VA L
A0 =
VOV
VA 2μn Cox WL
A0 =
ID
∞
Input Resistance with
Source (Emitter)
Grounded
rπ = β/gm
High-Frequency
Model
Cgd
G
rx
D B
Vgs
Cgs
Vp
ro
gmVgs
Cm
B
rp
C
Cp
S
Capacitances
Cgs =
E
2
WLCox + WLov Cox
3
Cgd = WLov Cox
Transition
Frequency fT
fT =
gm
2π (Cgs + Cgd )
For Cgs Cgd and Cgs fT gmVp
Cπ = Cde + Cje
Cde = τF gm
Cje 2Cje0
m
V
Cμ = Cμ0 1 + CB
VC0
fT =
2
WLCox ,
3
1.5μn VOV
2π L2
W
L
Design
Parameters
ID , VOV , L,
Good Analog
Switch?
Yes, because the device is symmetrical
and thus the iD –vDS characteristics pass
directly through the origin.
g
m
2π Cπ + Cμ
For Cπ Cμ and Cπ Cde ,
fT 2μn VT
2π WB2
IC , VBE , AE (or IS )
No, because the device is asymmetrical
with an offset voltage VCEoff .
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ro
Summary Tables Supplement ST-19
Table J.1 Standard Resistance Values
1% Resistor Values (k)
5% Resistor Values (k)
100–174
178–309
316–549
562–976
10
11
12
13
15
16
18
20
22
24
27
30
33
36
39
43
47
51
56
62
68
75
82
91
100
102
105
107
110
113
115
118
121
124
127
130
133
137
140
143
147
150
154
158
162
165
169
174
178
182
187
191
196
200
205
210
215
221
226
232
237
243
249
255
261
267
274
280
287
294
301
309
316
324
332
340
348
357
365
374
383
392
402
412
422
432
442
453
464
475
487
499
511
523
536
549
562
576
590
604
619
634
649
665
681
698
715
732
750
768
787
806
825
845
866
887
909
931
953
976
Table J.2 SI Unit Prefixes
Name
Symbol
Factor
femto
pico
nano
micro
milli
kilo
mega
giga
tera
peta
f
p
n
µ
m
k
M
G
T
P
×10−15
−12
×10
−9
×10
−6
×10
−3
×10
3
×10
6
×10
×109
12
×10
15
×10
Table J.3 Meter Conversion Factors
1 µm = 10
−4
cm = 10
2
−6
m
6
9
1 m = 10 cm = 10 µm = 10 nm
0.1 µm = 100 nm
1 Å = 10−8 cm = 10−10 m
©2020 Oxford University Press
Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press is prohibited.
ST-20 Summary Tables Supplement
Table K.1 Typical Values of CMOS Device Parameters
0.8 µm
0.5 µm
0.25 µm
0.18 µm
0.13 µm
Parameter
NMOS PMOS
NMOS PMOS
NMOS PMOS
NMOS PMOS
NMOS PMOS
NMOS PMOS NMOS PMOS
(nm)
2
(fF/µm )
2
μ (cm /V · s)
2
μCox (µA/V )
Vt0 (V)
VDD (V)
|VA | (V/µm)
Cov (f F/µm)
15
2.3
550
127
0.7
5
25
0.2
9
3.8
500
190
0.7
3.3
20
0.4
6
5.8
460
267
0.5
2.5
5
0.3
4
8.6
450
387
0.5
1.8
5
0.37
2.7
12.8
400
511
0.4
1.3
5
0.36
1.4
25
216
540
0.35
1.0
3
0.33
tox
Cox
Table K.2
Parameter
2
AE (µm )
IS (A)
β 0 (A/A)
VA (V)
VCEO (V)
τF
Cje0
Cμ0
rx ()
15
2.3
250
58
−0.7
5
20
0.2
9
3.8
180
68
−0.8
3.3
10
0.4
6
5.8
160
93
−0.6
2.5
6
0.3
4
8.6
100
86
−0.5
1.8
6
0.33
2.7
12.8
100
128
−0.4
1.3
6
0.33
65 nm
1.4
25
40
100
−0.35
1.0
3
0.31
28 nm
1.4
34
220
750
0.3
0.9
1.5
0.4
Typical Parameter Values for BJTs*
Standard High-Voltage Process
Advanced Low-Voltage Process
npn
Lateral pnp
npn
Lateral pnp
500
5 × 10−15
200
130
50
0.35 ns
1 pF
0.3 pF
200
900
2 × 10−15
50
50
60
30 ns
0.3 pF
1 pF
300
2
6 × 10−18
100
35
8
10 ps
5 fF
5 fF
400
2
6 × 10−18
50
30
18
650 ps
14 fF
15 fF
200
*Adapted from Gray et al. (2001); see Appendix I.
©2020 Oxford University Press
Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press is prohibited.
1.4
34
200
680
−0.3
0.9
1.5
0.4