EE-221 Digital Logic Design
DE-42 EE (Syndicate-C)
Instructor: Lec. Aamir Javed
Chapter # 4: Optimized Implementation of Logic
Functions
Karnaugh Map
• 𝑓 = 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3
𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3
• 𝑓 = 𝑥1 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2
• 𝑓 = 𝑥1 𝑥3 + 𝑥1 𝑥3 + 𝑥1 𝑥2
• 𝑓 = 𝑥3 + 𝑥1 𝑥2
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Karnaugh Map
• It would be advantageous to devise a method that allows easy
discovery of groups of minterms which can be combined into single
terms
• The Karnaugh map allows us to do exactly this
• Karnaugh map can be used directly to derive a minimum-cost circuit
for a logic function
• Karnaugh map is an alternative to the truth-table form for
representing a function
• The map consists of cells that correspond to the rows of the truth
table.
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Two Variable Karnaugh Map
𝑥1
𝑥1
x1
x2
0
0
m
0
1
m
1
0
m
1
1
m
(a) Truth table
x
x
2
0
0
1
2
1
0
m
1
m
1
0
1
3
(b) Karnaugh map
EE-221 Digital Logic Design (FALL 2021) Chapter 4
m
m
2
𝑥2
3
𝑥2
Two Variable Karnaugh Map - σ 𝒎(𝟎, 𝟏, 𝟑)
𝑥1
𝑥1
x
x
2
𝑥1 +𝑥2
1
0
0
m
1
m
x
1
0
1
m
m
x
2
1
0
1
2
𝑥2
0
1
0
3
𝑥2
1
1
1
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Two Variable Karnaugh Map - σ 𝒎(𝟏, 𝟐, 𝟑)
𝑥1
𝑥1 +𝑥2
𝑥1
x
x
2
1
0
0
m
1
m
x
1
0
1
m
m
x
2
1
0
1
2
𝑥2
0
0
1
3
𝑥2
1
1
1
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Three Variable Karnaugh Map
𝑥1
x1 x2 x3
0
0
0
m0
0
0
1
m1
0
1
0
m2
0
1
1
m3
1
0
0
m4
1
0
1
m5
1
1
0
m6
1
1
1
m7
x3
x1 x2
00
01
11
10
0
m0
m2
m6
m4
1
m1
m3
m7
m5
(b) Karnaugh map
(a) Truth table
EE-221 Digital Logic Design (FALL 2021) Chapter 4
𝑥2
𝑥3
0
1
Three Variable Karnaugh Map σ 𝒎(𝟏, 𝟒, 𝟓, 𝟔)
𝑥1
x3
x1 x2
00
01
11
10
0
m0
m2
m6
m4
1
m1
m3
m7
m5
2
3
4
5
(b) Karnaugh map
𝑥3
x3
x1x2
00
01
11
10
0
0
0
1
1
1
1
0
0
1
6
7
𝑥2
EE-221 Digital Logic Design (FALL 2021) Chapter 4
f = x1x3 + x2x3
Three Variable Karnaugh Map σ 𝒎(𝟎, 𝟐, 𝟒, 𝟓, 𝟔)
𝑥1
m0
m1
m2
m3
x3
x1 x2
00
01
11
10
0
m0
m2
m6
m4
1
m1
m3
m7
m5
m4
m5
(b) Karnaugh map
m6
m7
e
𝑥2
𝑥3
x3
x1 x2
00
01
11
10
0
1
1
1
1
1
0
0
0
1
EE-221 Digital Logic Design (FALL 2021) Chapter 4
f = x3 + x x2
1
Four Variable Karnaugh
Map
𝑥
1
𝑥4
𝑥3
𝑥2
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Four Variable Karnaugh Map - Example
x
x
𝑥1
𝑥4
𝑥3
3
x
1
x
2
4
00
01
11
10
00
0
0
0
0
01
0
0
1
1
11
1
0
0
1
1
0
0
1
10
𝑥2
f
1
=
EE-221 Digital Logic Design (FALL 2021) Chapter 4
x
2
x
3
+ x
1
x
3
x
4
Four Variable Karnaugh Map - Example
x
x
𝑥1
3
x
1
4
𝑥4
𝑥3
x
2
00
01
11
10
00
0
0
0
0
01
0
0
1
1
11
1
1
1
1
10
1
1
1
1
𝑥2
f
EE-221 Digital Logic Design (FALL 2021) Chapter 4
2
=
x
3
+ x
1
x
4
Four Variable Karnaugh Map - Example
x
x
𝑥1
3
x
1
x
2
4
𝑥4
𝑥3
00
01
11
10
00
1
0
0
1
01
0
0
0
0
11
1
1
1
0
10
1
1
0
1
𝑥2
f
3
EE-221 Digital Logic Design (FALL 2021) Chapter 4
=
x
2
x
4
+ x
1
x
3
+ x
2
x
3
x
4
Four Variable Karnaugh Map - Example
x
x
𝑥1
𝑥4
𝑥3
3
x
1
4
x
2
00
01
11
10
00
1
1
1
0
01
1
1
1
0
11
0
0
1
1
10
0
0
1
1
𝑥2
𝑥1 𝑥3 + 𝑥1 𝑥3 + 𝑥1 𝑥2
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Four Variable Karnaugh Map - Example
x
x
𝑥1
𝑥4
𝑥3
3
x
1
4
x
2
00
01
11
10
00
1
1
1
0
01
1
1
1
0
11
0
0
1
1
10
0
0
1
1
𝑥2
𝑥1 𝑥3 + 𝑥1 𝑥3 + 𝑥2 𝑥3
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Five Variable Karnaugh Map
x3 x4
x1 x2
00
01
11
10
00
x3 x4
x1 x2
00
01
00
01
1
1
01
1
1
1
11
1
1
10
1
1
10
1
1
x5 = 0
=
10
1
11
𝑓1
11
x5 = 1
𝑥1 𝑥3 + 𝑥1 𝑥3 𝑥4 + 𝑥1 𝑥2 𝑥3 𝑥5
EE-221 Digital Logic Design (FALL 2021) Chapter 4
1
Strategy for Minimization
𝑓 = 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3
• Terminology
• Literal
• Implicant
• Prime Implicant
• 𝑥1 𝑥3
• 𝑥1 𝑥2
• 𝑥2 𝑥3
Cost = 27
x3
x1x2
00
01
11
10
0
0
0
1
1
1
1
0
0
1
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Strategy for Minimization
𝑓 = 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3
• Prime Implicant
• 𝑥1 𝑥3
• 𝑥1 𝑥2
• 𝑥2 𝑥3
• Cover
•
•
•
•
Cost = 27
x3
A set of implicants that accounts for all 1s
Set of minterms
Set of prime implicants (𝑥1 𝑥3 + 𝑥1 𝑥2 + 𝑥2 𝑥3 )
Subset of prime implicants (𝑥1 𝑥3 + 𝑥2 𝑥3 )
x1x2
00
01
11
10
0
0
0
1
1
1
1
0
0
1
• Cost
• Essential Prime Implicant
• 𝑥1 𝑥3
• 𝑥2 𝑥3
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Strategy for Minimization
• Minimization Procedure
• Generate all Prime Implicants for the given function 𝑓
• Find the set of Essential Prime Implicants (EPI)
• If the set of EPI covers all valuations for which 𝑓 = 1, then the set is desired
cover of 𝑓 .
• Otherwise, determine the non-essential Prime Implicants that should be
added to form a complete minimum cost cover.
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Strategy for Minimization
𝑓 = 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3
• Prime Implicant
• 𝑥1 𝑥3
• 𝑥1 𝑥2
• 𝑥2 𝑥3
• Essential Prime Implicant
• 𝑥1 𝑥3
• 𝑥2 𝑥3
• Min cost Cover
• 𝑥1 𝑥3 +𝑥2 𝑥3
Cost = 27
x3
x1x2
00
01
11
10
0
0
0
1
1
1
1
0
0
1
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Strategy for Minimization
• Prime Implicants
• 𝑥1 𝑥4
• 𝑥2 𝑥4
• 𝑥1 𝑥2 𝑥3
• Essential Prime Implicants
x
x
3
x
1
4
• 𝑥1 𝑥4
• 𝑥2 𝑥4
• 𝑥1 𝑥2 𝑥3
• Min cost cover
• 𝑥1 𝑥4 + 𝑥2 𝑥4 + 𝑥1 𝑥2 𝑥3
EE-221 Digital Logic Design (FALL 2021) Chapter 4
x
2
00
01
11
10
00
0
0
0
0
01
1
1
1
0
11
1
1
1
0
10
0
1
0
0
Strategy for Minimization
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Minimization Procedure
• Prime Implicants
•
•
•
•
•
x
x
𝑥2 𝑥3
𝑥1 𝑥3
𝑥3 𝑥4
𝑥1 𝑥2 𝑥4
𝑥2 𝑥3 𝑥4
4
x
2
00
01
11
1
1
10
00
• Essential Prime Implicants
• 𝑥2 𝑥3
• 𝑥3 𝑥4
• 𝑥2 𝑥3 𝑥4
3
x
1
01
11
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
1
1
1
1
1
1
1
Minimization Procedure
• Essential Prime Implicants
x
x
• 𝑥2 𝑥3
• 𝑥3 𝑥4
• 𝑥2 𝑥3 𝑥4
3
x
1
4
x
2
00
01
11
1
1
10
00
• Min cost cover
01
•𝑥2 𝑥3 + 𝑥3 𝑥4 + 𝑥2 𝑥3 𝑥4
11
1
1
1
1
1
+𝑥1 𝑥3
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
1
1
Minimization Procedure
• Prime Implicants
•
•
•
•
•
•
𝑥3 𝑥4
𝑥1 𝑥3 𝑥4
𝑥1 𝑥2 𝑥3
𝑥1 𝑥2 𝑥4
𝑥1 𝑥2 𝑥3
𝑥1 𝑥2 𝑥4
x
x
3
x
1
4
00
2
00
01
11
10
1
1
1
1
01
1
11
1
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
x
1
1
Minimization Procedure
x
• Prime Implicants
x
• 𝑥3 𝑥4 , 𝑥1 𝑥3 𝑥4 , 𝑥1 𝑥2 𝑥3 , 𝑥1 𝑥2 𝑥4 ,
• 𝑥1 𝑥2 𝑥3 , 𝑥1 𝑥2 𝑥4
3
x
1
4
00
x
2
00
01
11
10
1
1
1
1
• Essential Prime Implicants
• 𝑥3 𝑥4
• Cover
• 𝑥3 𝑥4 +
01
1
11
1
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
1
1
Minimization Procedure – Solution (Not Min
Cost)
x
• Prime Implicants
x
• 𝑥3 𝑥4 , 𝑥1 𝑥3 𝑥4 , 𝑥1 𝑥2 𝑥3 , 𝑥1 𝑥2 𝑥4 ,
• 𝑥1 𝑥2 𝑥3 , 𝑥1 𝑥2 𝑥4
3
x
1
4
00
x
2
00
01
11
10
1
1
1
1
• Essential Prime Implicants
• 𝑥3 𝑥4
• Cover
• 𝑥3 𝑥4 + 𝑥1 𝑥2 𝑥4 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥3 𝑥4
01
1
11
1
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
1
1
Minimization Procedure – Min Cost Solution
x
• Prime Implicants
x
• 𝑥3 𝑥4 , 𝑥1 𝑥3 𝑥4 , 𝑥1 𝑥2 𝑥3 , 𝑥1 𝑥2 𝑥4 ,
• 𝑥1 𝑥2 𝑥3 , 𝑥1 𝑥2 𝑥4
3
x
1
4
00
x
2
00
01
11
10
1
1
1
1
• Essential Prime Implicants
• 𝑥3 𝑥4
• Cover
• 𝑥3 𝑥4 + 𝑥1 𝑥2 𝑥4 + 𝑥1 𝑥2 𝑥3
01
1
11
1
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
1
1
Minimization Procedure – No EPI
x
x
3
x
1
4
00
x
2
00
01
1
1
01
1
11
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
11
1
1
1
10
1
1
Minimization Procedure – No EPI
x
x
3
x
1
4
00
x
x
2
x
00
01
1
1
01
1
11
10
11
3
4
00
1
1
1
10
x
1
x
2
00
01
1
1
01
1
1
EE-221 Digital Logic Design (FALL 2021) Chapter 4
1
11
10
11
1
1
1
10
1
1
෍ 𝒎(𝟎, 𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟏, 𝟏𝟑, 𝟏𝟓)
x
x
3
x
1
4
x
2
00
00
10
11
1
01
11
01
1
1
EE-221 Digital Logic Design (FALL 2021) Chapter 4
10
1
1
1
1
1
1
1
1
෍ 𝒎(𝟎, 𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟏, 𝟏𝟑, 𝟏𝟓)
x
• Prime Implicants
x
• 𝑥2 𝑥4 , 𝑥2 𝑥4 , 𝑥1 𝑥4 , 𝑥3 𝑥4 , 𝑥1 𝑥2 , 𝑥2 𝑥3
3
x
1
4
• Essential Prime Implicants
x
2
00
00
01
11
1
10
1
• 𝑥2 𝑥4 , 𝑥2 𝑥4
• Cover
01
1
1
1
1
1
1
• 𝑥2 𝑥4 + 𝑥2 𝑥4 + ?
11
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
1
1
1
෍ 𝒎(𝟎, 𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟏, 𝟏𝟑, 𝟏𝟓)
x
• Prime Implicants
x
• 𝑥2 𝑥4 , 𝑥2 𝑥4 , 𝑥1 𝑥4 , 𝑥3 𝑥4 , 𝑥1 𝑥2 , 𝑥2 𝑥3
3
x
1
4
• Essential Prime Implicants
x
2
00
00
01
11
1
10
1
• 𝑥2 𝑥4 , 𝑥2 𝑥4
• Cover
01
• 𝑥2 𝑥4 + 𝑥2 𝑥4 + 𝑥1 𝑥4 + 𝑥3 𝑥4
11
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
1
1
1
1
1
1
1
1
1
෍ 𝒎(𝟎, 𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟏, 𝟏𝟑, 𝟏𝟓)
x
• Prime Implicants
x
• 𝑥2 𝑥4 , 𝑥2 𝑥4 , 𝑥1 𝑥4 , 𝑥3 𝑥4 , 𝑥1 𝑥2 , 𝑥2 𝑥3
3
x
1
4
• Essential Prime Implicants
x
2
00
00
01
11
1
10
1
• 𝑥2 𝑥4 , 𝑥2 𝑥4
• Cover
•
•
•
•
01
𝑥2 𝑥4 + 𝑥2 𝑥4 + 𝑥1 𝑥4 + 𝑥3 𝑥4
𝑥2 𝑥4 + 𝑥2 𝑥4 + 𝑥3 𝑥4 + 𝑥1 𝑥2
𝑥2 𝑥4 + 𝑥2 𝑥4 + 𝑥2 𝑥3 + 𝑥1 𝑥4
𝑥2 𝑥4 + 𝑥2 𝑥4 + 𝑥2 𝑥3 + 𝑥1 𝑥2
EE-221 Digital Logic Design (FALL 2021) Chapter 4
11
10
1
1
1
1
1
1
1
1
1
POS Minimization
EE-221 Digital Logic Design (FALL 2021) Chapter 4
POS Minimization
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Incompletely Specified Functions
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Multiple Output Circuits
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Multiple Output Circuits
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Minimization of Logic Expression using K-Map
• Minimize 𝑓 = 𝑥3 𝑥4 + 𝑥1 𝑥2 𝑥4 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥3 𝑥4 using Karnaugh
Map
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Solution
• 𝑥3 𝑥4 + 𝑥1 𝑥2 𝑥4 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥3 𝑥4
• 𝑥3 𝑥4 + 𝑥1 𝑥2 𝑥4 + 𝑥1 𝑥2 𝑥3
x
x
3
x
1
4
00
2
00
01
11
10
1
1
1
1
01
1
11
1
10
EE-221 Digital Logic Design (FALL 2021) Chapter 4
x
1
1
Example – Converting Circuit to NAND Gates
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Example – Converting Circuit to NAND Gates
EE-221 Digital Logic Design (FALL 2021) Chapter 4
Example – Converting Circuit to NAND Gates
EE-221 Digital Logic Design (FALL 2021) Chapter 4