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Logic Gates

Logic Gates
• The Gates are manufactured using semiconductor devices like BJT, Diodes, or FETs.
• Different Gate’s are constructed using Integrated circuits.
• Digital logic circuits are manufactured depending on the specific circuit technology
or logic families.
• The different logic families are RTL(Resistor Transistor Logic), DTL(Diode Transistor
Logic), TTL(Transistor-Transistor Logic), ECL(Emitter Coupled Logic) &
CMOS(Complementary Metal Oxide Semiconductor Logic)
• Out of these, RTL and DTL are rarely used.
TTL logic Gates
• In the year 1970, the Datapoint 2200 was used TTL components and it was the base
for the 8008 & after that the x86 instruction set.
• The Transistor-Transistor Logic (TTL) is a logic family made up of BJTs (bipolar junction
transistors). As the name suggests, the transistor performs two functions like logic as
well as amplifying.
• The best examples of TTL are logic gates namely the 7402 NOR Gate & the 7400
NAND gate.
• The designing of TTL logic gates can be done with resistors and BJTs.
• TTLs are available in different types and their classification is done based on the
• TTL logic includes several transistors that have several emitters as well as several
inputs. The types of TTL or transistor-transistor logic mainly include Standard TTL, Fast
TTL, Schottky TTL, High power TTL, Low power TTL & Advanced Schottky TTL.
Characteristics of TTL
1. Fan Out: Number of loads the output of a GATE can drive without affecting its usual
performance. By load we mean the amount of current required by the input of another Gate
connected to the output of the given gate.
2. Power Dissipation: It represents the amount of power needed by the device. It is measured
in mW. It is usually the product of supply voltage and the amount of average current drawn
when the output is high or low.
3. Propagation Delay: It represents the transition time that elapses when the input level
changes. The delay which occurs for the output to make its transition is the propagation delay.
4. Noise Margin: It represents the amount of noise voltage allowed at the input, which
doesn’t affect the standard output.
TTL circuit
The main feature is that its output is 0 when low and floating when
high. Usually, an external Vcc may be applied.
Transistor Q1 behaves as a cluster of diodes placed back to back. With
any of the input at logic low, the corresponding emitter-base junction is
forward biased and the voltage drop across the base of Q1 is around
0.9V, not enough for the transistors Q2 and Q3 to conduct. Thus the
The applications of open collector
output include the following.
output is either floating or Vcc, i.e. High level.
Similarly, when all inputs are high, all base-emitter junctions of Q1 are
reverse biased and transistor Q2 and Q3 get enough base current and
1. driving lamps or relays
2. performing wired logic
3. the construction of a common
bus system
are in saturation mode. The output is at logic low. (For a transistor to go
to saturation, collector current should be greater than β times the base
Totem pole output
Totem Pole means the addition of an active pull up the circuit in the output
of the Gate which results in a reduction of propagation delay.
Logic operation is the same as the open collector output. The use of
transistors Q4 and diode is to provide quick charging and discharging of
parasitic capacitance across Q3. The resistor is used to keep the output
current to a safe value.
TTL Family Features
The features of the TTL family include the following.
1. Logic low level is at 0 or 0.2V.
2. Logic high level is at 5V.
3. Typical fan out of 10. It means it can support at most 10 gates at its output.
4. A basic TTL device draws a power of almost 10mW, which reduces with the use
of Schottky devices.
5. The average propagation delay is about 9ns.
6. The noise margin is about 0.4V.
TTL ICs mostly start with the 7 series. It has 6 subfamilies given as:
Low Power device with a propagation delay of 35 ns and power dissipation of 1mW.
Low power Schottky device with a delay of 9ns
Advanced Schottky device with a delay of 1.5ns.
Advanced low power Schottky device with a delay of 4 ns and power dissipation of 1mW.
Note: In any TTL device nomenclature, the first two names indicate the name of the subfamily the device belongs
to. The first two digits indicate the temperature range of operation. The next two alphabets indicate the subfamily
the device belongs to. The last two digits indicate the logic function performed by the chip. The examples are 74LS022 neither input NOR gate, 74LS10- Triple 3 input NAND gate.
Diode Resistor Logic (DRL)
The diode logic uses diodes and resistors to implement Boolean functions. Diodes function as a switch that conducts
only during the forward biasing condition.
The simplicity in the circuits is the main advantage of diode logic but it lacks amplification of the input signal. This
limits the application of diode logic.
• The diode logic can implement only logic OR and logic AND operations that are noninverting.
The diode OR gate has two inputs and an output. The output is high only if at least one input is high and is low
when both the inputs are low. The circuit for a basic DL OR is shown in figure below. The OR logic gate is
implemented in the diode logic by connecting the diodes parallel. The diodes are normally open switches. It is clear
from the circuit that the input is applied to the anode of the diode and the output is taken at the cathode of the
diode across the resistor R1 to the ground. The +5 volts always represent logic 1 or ON, and ground, or zero volts a
logic 0 is represented as in figure below.
Inputs at logic 1: In the circuit, if both the inputs are connected to +5 V or logic high input logical 1 then the diodes are forward
biased and are closed. The current passes across the diode and causes high voltage drop across the resistor R1. The output is at high or
logic 1. If one input is high and the other input is low, then the diode connected to the high input acts as closed switch and the output is
still high.
Inputs at logic 0: When both the inputs are connected to zero volts or ground, then the inputs are at logic 0. Both the diodes are
reverse biased and switches are open and do not conduct. Therefore, the output across the resistor will also be zero volts.
Thus, the diode logic implements the OR functions. Assume that the diode induces error in the circuit. The silicon diode introduces a
voltage drop of 0.65 V–0.7 V therefore even when the voltage is not exactly +5 V but +4.35 V at the output still the diodes are said to be
conducting. We consider the noise margin in this case. Thus, any voltage above +3.5 volts is considered to be logic 1, any voltage below
+1.5 volts shall be logic 0. Output voltages between +1.5 and +3.5 volts fall under the undefined voltage region.
The Diode Logic (DL)-AND gate is implemented by connecting open switches in series. Since diodes are two terminal
devices, they cannot be driven by grounded input voltage sources when connected in series. Thus to overcome this
problem, the diodes are connected in parallel as in the case of OR diode gates with modification. To obtain AND logic
instead of OR function the input and output logical variables are inverted or reversed. The circuit of DL AND gate is
shown in figure below. In a diode AND gate, if both the input voltages are high then the output voltage is high. If both
the inputs are low and one is low then the output voltage is low.
Consider the circuit for AND logic gate, the input to the diodes is connected in opposite direction. The input voltage flows across the
resistor thus creating the current to flow across the anode of the diodes and then to its cathode. The output is taken across the resistor
R and ground terminal. This gives the complementary voltage drop.
Inputs at logic 1: When both the inputs A and B are at high, then the diodes are neutralized. There is no voltage drop across the
diodes and the diode switches are open. Since no current flows across the resistor and no voltage drop, the output is high. Thus, the
operation of diode logic AND is the reverse of diode logic OR gate since the diodes are reversed.
Inputs at logic 0: When both the inputs are at low, the biasing voltage (+5 V) flows through the resistor and reaches the diodes and
finally the input source. This causes the diodes to be forward biased and the diode switch is closed. Thus, the output voltage drop across
the diode is logic 0. If one of the inputs is high and the other is maintained at low, then the diode connected to high input voltages or
logic 1 is reverse biased and its input voltage is disconnected from the output. The output is again 0. Thus, this circuit performs the
logical AND functions.
DRL Disadvantages
• Diode logic only permits the OR and AND functions.
• Diode logic suffers from voltage drop from one stage to the next. Unlike the active
logic gates that can be integrated to larger components, the diode logic cannot be
cascaded as they face few problems.
– The diodes possess a voltage drop of 0.65 V during the forward bias condition.
When the identical diodes are cascaded, this voltage is either added to or
subtracted from the input of every gate. Thus, this voltage accumulates at each
stage. For an OR gate, the voltage drop decreases the high voltage level (logic 1)
while in an AND gate, it increases the low voltage level (logic 0).
– The second problem the diodes face during cascading is that of the voltage
divider. The input voltage sources possess an internal resistance that joins the
gate resistor to produce a voltage divider action on the voltage levels. The source
resistance decreases logic 1 level in an OR gate. In an AND gate, the gate
resistance increases logic 0 level.
Diode logic is used extensively to produce simple logic functions but not in integrated
These issues restrict the usage of diode logic and have made them obsolete.
• Emitter-coupled logic is the fastest of all digital logic families. It was invented
by Hannon S. Yourke in the year 1956 at IBM. It is also called as current mode logic.
The design of ECL circuit consists of transistors and resistors.
• By preventing the transistor from entering into saturation, the high-speed operation
is achieved in ECL logic family. Very small voltage swing is necessary to switch
between the two different voltage levels.
• Emitter-coupled logic family offers an incredible propagation delay of 1ns. The delay
is more reduced in the latest ECL families.
The circuit shown below represents the emitter-coupled logic circuit of an
inverter. It has two NPN transistors connected in differential single-ended input
Both the emitters are connected together with common resistance RE. It is a
current limiting resistance, used to prevent the transistor from entering into
It has two outputs: inverting output(VOUT1) and non-inverting output(VOUT12). VIN is
the input terminal, where LOW or HIGH input is given.