MMMC synthesis
cd /home/uceeml2/T-018-CM-SP-018-K3_1_0A/TSMC_20K/MMMC_Flow/work_mmmc
genus -log syn_mmmc.log
source ../SCRIPTS/run_SPI.tcl
cd /home/uceeml2/T-018-CM-SP-018-K3_1_0A/TSMC_20K/FPR/work/
run.tcl
if {[file exists /proc/cpuinfo]} {
sh grep "model name" /proc/cpuinfo
sh grep "cpu MHz"
/proc/cpuinfo
}
puts "Hostname : [info hostname]"
set
set
set
set
DESIGN dtmf_recvr_core
SYN_EFF medium
MAP_EFF medium
OPT_EFF medium
set RELEASE [lindex [get_db program_version] end]
set _OUTPUTS_PATH OUTPUT/outputs_${RELEASE}
set _REPORTS_PATH OUTPUT/reports_${RELEASE}
if {![file exists ${_OUTPUTS_PATH}]} {
file mkdir ${_OUTPUTS_PATH}
puts "Creating directory ${_OUTPUTS_PATH}"
}
if {![file exists ${_REPORTS_PATH}]} {
file mkdir ${_REPORTS_PATH}
puts "Creating directory ${_REPORTS_PATH}"
}
set rtlDir ../RTL
set_db init_lib_search_path {. ../}
set_db script_search_path { . }
set_db init_hdl_search_path {. ../RTL}
set_db max_cpus_per_server 8
set_db syn_generic_effort $SYN_EFF
set_db syn_map_effort $MAP_EFF
set_db syn_opt_effort $OPT_EFF
set_db information_level 9
# set_db pbs_mmmc_flow true
set_db tns_opto true
set_db lp_insert_clock_gating true
puts "Now load RTL LIST"
set rtlList " \
${rtlDir}/pllclk.v \
${rtlDir}/accum_stat.v \
"
suspend //resume
## Reading in MMMC defination file and lef files
read_mmmc ../SCRIPTS/mmmc.tcl
read_physical -lef { \
../LEF/gsclib045_v3.5/lef/gsclib045_tech.lef
../LEF/gsclib045_v3.5/lef/gsclib045_macro.lef
}
# Reading hdl files, initialize the database and elaborating them
read_hdl $rtlList
elaborate $DESIGN
#read_def ../DEF/dtmf.def
init_design
time_info init_design
check_design -unresolved
## Set the innovus executable to be used for placement and routing
## set_db innovus_executable <Innovus Executables>
###########################################################################
#########################
## Synthesizing the design
###########################################################################
#########################
syn_generic
write_snapshot -directory $_OUTPUTS_PATH -tag syn_generic
report_summary -directory $_REPORTS_PATH
puts "Runtime & Memory after 'syn_generic'"
time_info GENERIC
syn_map
write_snapshot -directory $_OUTPUTS_PATH -tag syn_map
report_summary -directory $_REPORTS_PATH
puts "Runtime & Memory after 'syn_map'"
time_info MAPPED
syn_opt
## generate reports to save the Innovus stats
write_snapshot -innovus -directory $_OUTPUTS_PATH -tag syn_opt
report_summary -directory $_REPORTS_PATH
puts "Runtime & Memory after syn_opt"
time_info OPT
## write out the final database
write_db -to_file ${DESIGN}.db
puts "Final Runtime & Memory."
time_info FINAL
puts "============================"
puts "Synthesis Finished ........."
puts "============================"
#quit
MMMC.tcl
create_library_set -name wcl_slow -timing {
../LIB/gsclib045_v3.5/timing/slow.lib
}
create_library_set -name wcl_fast -timing {
../LIB/gsclib045_v3.5/timing/fast.lib
}
create_library_set -name wcl_typical -timing {
../LIB/gsclib045_v3.5/timing/typical.lib
}
create_opcond -name op_cond_wcl_slow
-process 1 -voltage 1.08 temperature 125
create_opcond -name op_cond_wcl_fast
-process 1 -voltage 1.32 temperature 0
create_opcond -name op_cond_wcl_typical -process 1 -voltage 1.2 temperature 25
create_timing_condition -name timing_cond_wcl_slow
-opcond
op_cond_wcl_slow
-library_sets { wcl_slow }
create_timing_condition -name timing_cond_wcl_fast
-opcond
op_cond_wcl_fast
-library_sets { wcl_fast }
create_timing_condition -name timing_cond_wcl_typical -opcond
op_cond_wcl_typical -library_sets { wcl_typical }
create_rc_corner -name rc_corner -cap_table
../Captable/cln28hpl_1p10m+alrdl_5x2yu2yz_typical.capTbl
create_delay_corner -name delay_corner_wcl_slow -early_timing_condition
timing_cond_wcl_slow \
-late_timing_condition timing_cond_wcl_slow early_rc_corner rc_corner \
-late_rc_corner rc_corner
create_delay_corner -name delay_corner_wcl_fast -early_timing_condition
timing_cond_wcl_fast \
-late_timing_condition timing_cond_wcl_fast early_rc_corner rc_corner \
-late_rc_corner rc_corner
create_delay_corner -name delay_corner_wcl_typical -early_timing_condition
timing_cond_wcl_typical \
-late_timing_condition timing_cond_wcl_typical early_rc_corner rc_corner \
-late_rc_corner rc_corner
create_constraint_mode -name functional_wcl_slow -sdc_files { \
../Constraints_MMMC/dtmf_recvr_core_gate_slow.sdc
}
create_constraint_mode -name functional_wcl_fast -sdc_files { \
../Constraints_MMMC/dtmf_recvr_core_gate_fast.sdc
}
create_constraint_mode -name functional_wcl_typical -sdc_files { \
../Constraints_MMMC/dtmf_recvr_core_gate_typical.sdc
}
create_analysis_view -name view_wcl_slow -constraint_mode
functional_wcl_slow -delay_corner delay_corner_wcl_slow
create_analysis_view -name view_wcl_fast -constraint_mode
functional_wcl_fast -delay_corner delay_corner_wcl_fast
create_analysis_view -name view_wcl_typical -constraint_mode
functional_wcl_typical -delay_corner delay_corner_wcl_typical
set_analysis_view -setup { view_wcl_slow view_wcl_fast view_wcl_typical }
typical.sdc
# Set the current design
current_design dtmf_recvr_core
set_case_analysis 0 [get_ports test_mode]
set_case_analysis 0 [get_ports scan_en]
create_clock -name "refclk" -add -period 6.0 -waveform {0.0 3.0} [get_ports
refclk]
create_clock -name "m_clk" -add -period 6.0 -waveform {0.0 3.0} [get_pins
TEST_CONTROL_INST/m_clk]
set_false_path -from [list \
[get_ports reset] \
[get_ports test_mode] ]
set_false_path -hold -through [get_pins PM_INST/clk_enable]
set_input_delay -clock
set_input_delay -clock
pllrst]
set_input_delay -clock
spi_fs]
set_input_delay -clock
spi_data]
set_input_delay -clock
test_mode]
set_input_delay -clock
scan_clk]
set_input_delay -clock
scan_en]
set_input_delay -clock
{port_pad_data_in[0]}]
set_input_delay -clock
{port_pad_data_in[1]}]
set_input_delay -clock
{port_pad_data_in[2]}]
[get_clocks refclk] -add_delay 0.3 [get_ports ibias]
[get_clocks refclk] -add_delay 0.3 [get_ports
[get_clocks refclk] -add_delay 0.3 [get_ports
[get_clocks refclk] -add_delay 0.3 [get_ports
[get_clocks refclk] -add_delay 0.3 [get_ports
[get_clocks refclk] -add_delay 0.3 [get_ports
[get_clocks refclk] -add_delay 0.3 [get_ports
[get_clocks refclk] -add_delay 0.3 [get_ports
[get_clocks refclk] -add_delay 0.3 [get_ports
[get_clocks refclk] -add_delay 0.3 [get_ports
set_input_delay -clock [get_clocks refclk] -add_delay 0.3 [get_ports
{port_pad_data_in[3]}]
set_input_delay -clock [get_clocks m_clk]
set_input_delay -clock [get_clocks m_clk]
set_input_delay -clock [get_clocks m_clk]
set_input_delay -clock [get_clocks m_clk]
spi_data]
set_input_delay -clock [get_clocks m_clk]
test_mode]
set_input_delay -clock [get_clocks m_clk]
scan_clk]
set_input_delay -clock [get_clocks m_clk]
scan_en]
set_input_delay -clock [get_clocks m_clk]
{port_pad_data_in[0]}]
set_input_delay -clock [get_clocks m_clk]
{port_pad_data_in[1]}]
set_input_delay -clock [get_clocks m_clk]
{port_pad_data_in[2]}]
set_input_delay -clock [get_clocks m_clk]
set_max_fanout 15.000 [current_design]
set_max_transition 1.2 [current_design]
-add_delay
-add_delay
-add_delay
-add_delay
0.3
0.3
0.3
0.3
[get_ports ibias]
[get_ports pllrst]
[get_ports spi_fs]
[get_ports
-add_delay 0.3 [get_ports
-add_delay 0.3 [get_ports
-add_delay 0.3 [get_ports
-add_delay 0.3 [get_ports
-add_delay 0.3 [get_ports
-add_delay 0.3 [get_ports
-add_delay 0.3 [get_ports
iSpatial synthesis
DEF (design exchange format)
represent physical layout of an IC
[VERSION statement] 5.3 – 5.8
[DIVIDERCHAR statement] default value ‘/’
[BUSBITCHARS statement] default value ‘[ ]’
[DESIGN statement] design name
[TECHNOLOGY statement] TSMC
[UNITS statement] units distance microns(conversion factor)
[DIEAREA statement] diearea multiplied by the conversion factor
[ROW statement] ROW
rowname sitename: specify the LEF site used for the row. origX origY siteorientation(N FS)
DO numx BY numy: specify the repeating set of sites that create the row. One of the number must be
1. If numY is 1, it’s horiaental.
STEP stepX stepY: spacing.
Example: We have Site array: Width=0.14 Height=1.2
Let’s suppose die area: Width=1167.32 Height=972
Then no. of sites per row:1167.32/0.14. No. of row is 972/1.2
Track statement
X/Y start: define the direction and