CHAPTER
10
Programmable Logic
CHAPTER OUTLINE
10–1
10–2
10–3
10–4
10–5
10–6
10–7
Simple Programmable Logic Devices (SPLDs)
Complex Programmable Logic Devices (CPLDs)
Macrocell Modes
Field-Programmable Gate Arrays (FPGAs)
Programmable Logic Software
Boundary Scan Logic
Troubleshooting
Applied Logic
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■
■
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■
■
■
■
■
■
Discuss the types of programmable logic, SPLDs
and CPLDs, and explain their basic structure
Describe the basic architecture of two types of
SPLDs—the PAL and the GAL
Explain the basic structure of a programmable logic
array (PLA)
Discuss the operation of macrocells
Distinguish between CPLDs and FPGAs
Explain the basic operation of a look-up table (LUT)
Define intellectual property and platform FPGA
Discuss embedded functions
Show a basic software design flow for a
programmable device
Explain the design flow elements of design entry,
functional simulation, synthesis, implementation,
timing simulation, and downloading
Discuss several methods of testing a programmable
logic device, including boundary scan logic
KEY TERMS
Key terms are in order of appearance in the chapter.
■
PAL
■
Registered
■
GAL
Macrocell
■
CPLD
LAB
■
LUT
■
■
FPGA
■
■
CLB
Intellectual property
Design flow
Target device
Schematic entry
■
■
■
■
■
■
■
■
■
Text entry
Functional simulation
Compiler
Timing simulation
Downloading
Break point
Boundary scan
VISIT THE WEBSITE
Study aids for this chapter are available at
http://www.pearsonglobaleditions.com/floyd
CHAPTER OBJECTIVES
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INTRODUCTION
The distinction between hardware and software is
hazy. Today, new digital circuits are programmed into
hardware using languages like VHDL. The density
(number of equivalent gates on a single chip) has
increased dramatically over the past few years. The
maximum number of gates in an FPGA (a type of PLD
known as a field-programmable gate array) is doubling every 18 months, according to Moore’s law. At
the same time, the price for a PLD is decreasing.
PLDs, such as the FPGA, can be used in conjunction
with processors and software in an embedded system,
or the FPGA can be the sole component with all the
logic functions programmed in. An embedded system
is one that is dedicated to a single task or a very limited
number of tasks unlike the computer, which is multipurpose and can be programmed to perform just about any
task. With PLDs, logic is described with software and
then implemented with the internal gates of the PLD.
In this chapter, the basic architecture (internal
structure and organization) of SPLDs, CPLDs, and
FPGAs is discussed. A discussion of software development tools covers the generic design flow for programming a device, including design entry, functional
simulation, synthesis, implementation, timing simulation, and downloading.
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10–1 Simple Programmable Logic Devices (SPLDs)
Two major types of simple programmable logic devices (SPLDs) are the PAL and the
GAL. PAL stands for programmable array logic, and GAL stands for generic array
logic. Generally, a PAL is one-time programmable (OTP), and a GAL is a type of
PAL that is reprogrammable. The term GAL is a designation originally used by Lattice
Semiconductor and later licensed to other manufacturers. The basic structure of both
PALs and GALs is a programmable AND array and a fixed OR array, which is a basic
sum-of-products architecture.
After completing this section, you should be able to
◆
Describe SPLD operation
◆
Show how a sum-of-products expression is implemented in a PAL or GAL
◆
Explain simplified PAL/GAL logic diagrams
◆
Describe a basic PAL/GAL macrocell
SPLD: The PAL
A PAL (programmable array logic) consists of a programmable array of AND gates that
connects to a fixed array of OR gates. Generally, PALs are implemented with fuse process
technology and are, therefore, one-time programmable (OTP).
The PAL structure allows any sum-of-products (SOP) logic expression with a defined
number of variables to be implemented. As you have learned, any combinational logic
function can be expressed in SOP form. A simple PAL structure is shown in Figure 10–1
for two input variables and one output; most PALs have many inputs and many outputs.
As you learned earlier, a programmable array is essentially a grid or matrix of conductors
that form rows and columns with a programmable link at each cross point. Each programmable link, which is a fuse in the case of a PAL, is called a cell. Each row is connected to
the input of an AND gate, and each column is connected to an input variable or its complement. By programming the presence or absence of a fuse connection, any combination
of input variables or complements can be applied to an AND gate to form any desired
product term. The AND gates are connected to an OR gate, creating a sum-of-products
(SOP) output.
A
A
B
B
X
FIGURE 10–1 Basic AND/OR structure of a PAL.
Simple Programmable Logic Devices (SPLDs)
Implementing a Sum-of-Products Expression
An example of a simple PAL is programmed as shown in Figure 10–2 so that the product
term AB is produced by the top AND gate, AB is produced by the middle AND gate, and
A B is produced by the bottom AND gate. As you can see, the fuses are left intact to connect
the desired variables or their complements to the appropriate AND gate inputs. The fuses
are opened where a variable or its complement is not used in a given product term. The final
output from the OR gate is the SOP expression,
X = AB + AB + A B
A
A
B
B
X = AB + AB + AB
FIGURE 10–2 PAL implementation of a sum-of-products expression.
SPLD: The GAL
The GAL is essentially a PAL that can be reprogrammed. It has the same type of AND/
OR organization that the PAL does. The basic difference is that a GAL uses a reprogrammable process technology, such as EEPROM (E2CMOS), instead of fuses, as shown in
Figure 10–3.
A
A
B
B
+V
+V
X
+V
+V
FIGURE 10–3 Simplified GAL array.
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Programmable Logic
Simplified Notation for PAL/GAL Diagrams
Actual PAL and GAL devices have many AND and OR gates in addition to other elements
and are capable of handling many variables and their complements. Most PAL and GAL
diagrams that you may see on a data sheet use simplified notation, as illustrated in Figure 10–4, to keep the schematic from being too complicated.
Input
buffer
Input lines
A
A
B
B
A
Fixed connection
B
Single line with slash represents multiple
AND gate inputs. (In this case, 2 inputs)
Product
term lines
2
AB
2
AB
X = AB + AB + AB
2
AB
Fuse blown
(no connection)
Fuse intact
(connection)
FIGURE 10–4 A portion of a programmed PAL/GAL.
The input variables to a PAL or GAL are usually buffered to prevent loading by a
large number of AND gate inputs to which they are connected. On the diagram, the
triangle symbol represents a buffer that produces both the variable and its complement.
The fixed connections of the input variables and buffers are shown using standard dot
notation.
PALs and GALs have a large number of programmable interconnection lines, and each
AND gate has multiple inputs. Typical PAL and GAL logic diagrams represent a multipleinput AND gate with an AND gate symbol having a single input line with a slash and a
digit representing the actual number of inputs. Figure 10–4 illustrates this for the case of
2-input AND gates.
Programmable links in an array are indicated in a diagram by a red X at the cross
point for an intact fuse or other type of link and the absence of an X for an open fuse
or other type of link. In Figure 10–4, the 2-variable logic function AB + AB + A B is
programmed.
EXAMPLE 10–1
Show how a PAL is programmed for the following 3-variable logic function:
X = ABC + ABC + A B + AC
Solution
The programmed array is shown in Figure 10–5. The intact fusible links are indicated by small red Xs. The absence of an X
means that the fuse is open.
Simple Programmable Logic Devices (SPLDs)
A
A
B
B
C
565
C
A
B
C
3
ABC
3
ABC
X = ABC + ABC + AB + AC
3
AB
AC
3
FIGURE 10–5
Related Problem*
Write the expression for the output if the fusible links connecting input A to the top row and to the bottom row in
Figure 10–5 are open.
*Answers are at the end of the chapter.
PAL/GAL General Block Diagram
A block diagram of a PAL or GAL is shown in Figure 10–6. Remember, the basic difference
is that a GAL has a reprogrammable array and the PAL is one-time programmable.
Macrocells
OR array
I1
I2
I3
OR
gate
Output
logic
O1
OR
gate
Output
logic
O2
OR
gate
Output
logic
O3
OR
gate
Output
logic
Om
I4
Programmable
AND array
PAL: One-time
programmable
GAL: Reprogrammable
In
FIGURE 10–6
General block diagram of a PAL or GAL.
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Programmable Logic
The programmable AND array outputs go to fixed OR gates that are connected to additional output logic. An OR gate combined with its associated output logic is typically called
a macrocell. The complexity of the macrocell depends on the particular device, and in
GALs it is often reprogrammable.
Generally, SPLD package configurations range from 20 pins to 28 pins. Two factors that
you can use to help determine whether a certain PAL or GAL is adequate for a given logic
design are the number of inputs and outputs and the number of equivalent gates or density.
Other parameters to consider are the maximum operating frequency, delay times, and dc
supply voltage. Two common types of SPLD are the 16V8 and the 22V10. Various SPLD
manufacturers may have different ways of defining density, so you have to use the specified
number of equivalent gates with this in mind.
Macrocells
A macrocell generally consists of one OR gate and some associated output logic. The
macrocells vary in complexity, depending on the particular type of PAL or GAL. A macrocell can be configured for combinational logic, registered logic, or a combination of both.
Registered logic means that there is a flip-flop in the macrocell to provide for sequential
logic functions. The registered operation of macrocells is covered in Section 10–3.
Figure 10–7 illustrates three basic types of macrocells with combinational logic. Part
(a) shows a simple macrocell with the OR gate and an inverter with a tristate control that
can make the inverter like an open circuit to completely disconnect the output. The output
of the tristate inverter can be either LOW, HIGH, or disconnected. Part (b) is a macrocell
that can be either an input or an output. When it is used as an input, the tristate inverter
is disconnected, and the input goes to the buffer that is connected to the AND array. Part
(c) is a macrocell that can be programmed to have either an active-HIGH or an activeLOW output, or it can be used as an input. One input to the exclusive-OR (XOR) gate
can be programmed to be either HIGH or LOW. When the programmable XOR input is
HIGH, the OR gate output is inverted because 0 ! 1 = 1 and 1 ! 1 = 0 . Similarly,
when the programmable XOR input is LOW, the OR gate output is not inverted because
0 ! 0 = 0 and 1 ! 0 = 1 .
From AND
gate array
Tristate control
From AND
gate array
Input/Output (I/O)
Output
(a) Combinational output (active-LOW). An active-HIGH
output would be shown without the bubble on the tristate
gate symbol.
(b) Combinational input/output (active-LOW)
From AND
gate array
Input/Output (I/O)
Programmable
fuse
(c) Programmable polarity output
FIGURE 10–7 Basic types of PAL/GAL macrocells for combinational logic.
Complex Programmable Logic Devices (CPLDs)
SECTION 10–1 CHECKUP
Answers are at the end of the chapter.
1. What does PAL stand for?
2. What does GAL stand for?
3. What is the difference between a PAL and a GAL?
4. Basically, what does a macrocell contain?
10–2 Complex Programmable Logic Devices (CPLDs)
The complex programmable logic device (CPLD) is basically a single device containing
multiple SPLDs and providing more capacity for larger logic designs. In this section, the
focus is the concepts of traditional CPLD architecture, keeping in mind that CPLDs may
vary somewhat in architecture and/or in parameters such as density, process technology,
power consumption, supply voltage, and speed.
After completing this section, you should be able to
◆
Describe a typical CPLD
◆
Discuss the basic CPLD architecture
◆
Explain how product terms are generated in CPLDs
The CPLD
A CPLD (complex programmable logic device) consists basically of multiple SPLD arrays
with programmable interconnections. Although the way CPLDs are internally organized
varies with the manufacturer, Figure 10–8 illustrates a generic CPLD. We will refer to each
I/O
I/O
I/O
I/O
Logic array
block (LAB)
Logic array
block (LAB)
SPLD
SPLD
Logic array
block (LAB)
Logic array
block (LAB)
SPLD
SPLD
Logic array
block (LAB)
PIA
Logic array
block (LAB)
SPLD
SPLD
Logic array
block (LAB)
Logic array
block (LAB)
SPLD
SPLD
FIGURE 10–8 Basic block diagram of a generic CPLD.
I/O
I/O
I/O
I/O
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Programmable Logic
SPLD array in a CPLD as a LAB (logic array block). Other designations are sometimes
used, such as function block, logic block, or generic block. The programmable interconnections are generally called the PIA (programmable interconnect array) although some
manufacturers, such as Xilinx, use the term AIM (advanced interconnect matrix) or a similar designation. The LABs and the interconnections between LABs are programmed using
software. A CPLD can be programmed for complex logic functions based on the SOP
structure of the individual LABs (actually SPLDs). Inputs can be connected to any of the
LABs, and their outputs can be interconnected to any other LABs via the PIA.
Most programmable logic manufacturers make a series of CPLDs that range in density,
process technology, power consumption, supply voltage, and speed. Manufacturers usually
specify CPLD density in terms of macrocells or logic array blocks. Densities can range
from tens of macrocells to over 1500 macrocells in packages with up to several hundred
pins. As PLDs become more complex, maximum densities will increase. Most CPLDs are
reprogrammable and use EEPROM or SRAM process technology for the programmable
links. Power consumption can range from a few milliwatts to a few hundred milliwatts. DC
supply voltages are typically from 2.5 V to 5 V, depending on the specific device.
Several manufacturers, (for example, Altera, Xilinx, Lattice, and Atmel) produce
CPLDs. As you will learn, CPLDs and other programmable logic devices are really a combination of hardware and software.
Classic CPLD Architecture
The architecture of a CPLD is the way in which the internal elements are organized and
arranged. The architecture of specific CPLDs is similar to the block diagram of a generic
CPLD (shown in Figure 10–8). It has the classic PAL/GAL structure that produces SOP
functions. The density ranges from 2 LABs to 16 LABs, depending on the particular device
in the series. Remember, a LAB is roughly equivalent to one SPLD, and package sizes for
CPLDs vary from 44 pins to 208 pins. Typically, a series of CPLDs uses the EEPROM-based
process technology. In-system programmable (ISP) versions use the JTAG standard interface.
Figure 10–9 shows a general block diagram of a typical CPLD. Four LABs are shown,
but there can be up to sixteen, depending on the particular device in a series. Each of
the four LABs consists of sixteen macrocells, and multiple LABs are linked together via
the PIA, which is a programmable global (goes to all LABs) bus structure to which the
general-purpose inputs, the I/Os, and the macrocells are connected.
The Macrocell
A simplified diagram of a typical macrocell is shown in Figure 10–10. The macrocell contains a small programmable AND array with five AND gates, an OR gate, a product-term
selection matrix for connecting the AND gate outputs to the OR gate, and associated logic
that can be programmed for input, combinational logic output, or registered output. This
macrocell is covered in more detail in Section 10–3.
Although based on the same concept, this macrocell differs somewhat from the macrocell
discussed in Section 10–1 in relation to SPLDs because it contains a portion of the programmable AND array and a product-term selection matrix. As shown in Figure 10–10, five AND
gates feed product terms from the PIA into the product-term selection matrix. The product term
from the bottom AND gate can be fed back inverted into the programmable array as a shared
expander for use by other macrocells. The parallel expander inputs allow borrowing of unused
product terms from other macrocells to expand an SOP expression. The product-term selection
matrix is an array of programmable connections that is used to connect selected outputs from
the AND array and from the expander inputs to the OR gate.
Shared Expanders
A complemented product term that can be used to increase the number of product terms in
an SOP expression is available from each macrocell in a LAB. Figure 10–11 illustrates how
a shared expander term from another macrocell can be used to create additional product
terms. In this case, each of the five AND gates in a macrocell array is limited to four inputs
General-purpose inputs
8–16 I/O
pins/LAB
I/O
control
block
8–16
Logic array block
(LAB A)
Logic array block
(LAB B)
Macrocell 1
Macrocell 1
Macrocell 2
36
36
16
16
Macrocell 2
I/O
control
block
8–16
Macrocell 16
Macrocell 16
8–16
8–16
PIA
I/O
control
block
8–16
Logic array block
(LAB C)
Logic array block
(LAB D)
Macrocell 1
Macrocell 1
Macrocell 2
36
36
16
16
Macrocell 16
Macrocell 2
I/O
control
block
8–16
Macrocell 16
8–16
8–16
FIGURE 10–9 Basic block diagram of a typical CPLD.
Parallel expanders
from other
macrocells
Product-term
selection
matrix
Associated
logic
To I/O
control
block
Shared
expander
36 lines from PIA
FIGURE 10–10
15 expander
product terms
from other
macrocells
Simplified diagram of a macrocell in a typical CPLD.
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A
B
C
A
B
C
D
ABC(E + F) = ABCE + ABCF
ABCD
E+F
EF
Product term from another
macrocell in same LAB
(b) AND gate is expanded to produce two product terms.
(a) A 4-input AND array gate can produce
one 4-variable product term.
FIGURE 10–11 Example of how a shared expander can be used in a macrocell
to increase the number of product terms.
and, therefore, can produce up to a 4-variable product term, as illustrated in part (a). Figure
10–11(b) shows the expansion to two product terms.
Each macrocell can produce up to five product terms generated from its AND array.
If a macrocell needs more than five product terms for its SOP output, it can use an
expander term from another macrocell. Suppose that a design requires an SOP expression that contains six product terms. Figure 10–12 shows how a product term from
Macrocell 1
ABCD + ABCD + ABCD
+ ABCD + ABCE + ABCF
Product-term
selection
matrix
Expander terms
Macrocell 2
ABCD + ABCD + ABCD
EF
Product-term
selection
matrix
Expander term E + F
to Macrocell 1
A
B
C
D
E
F
FIGURE 10–12 Simplified illustration of using a shared expander term from another
macrocell to increase an SOP expression. The red Xs and lines represent the connections
produced in the hardware by the software compiler running the programmed design.
Complex Programmable Logic Devices (CPLDs)
another macrocell can be used to increase an SOP output. Macrocell 2, which is underutilized, generates a shared expander term (E + F) that connects to the fifth AND gate
in macrocell 1 to produce an SOP expression with six product terms.
Parallel Expanders
Another way to increase the number of product terms for a macrocell is by using parallel expanders in which additional product terms are ORed with the terms generated by a
macrocell instead of being combined in the AND array, as in the shared expander. A given
macrocell can borrow unused product terms from neighboring macrocells. The basic concept is illustrated in Figure 10–13 where a simplified circuit that can produce two product
terms borrows three additional product terms.
ABCD + ABCD + EFGH
Parallel expander terms
A
B
C
D
ABCD + EFGH + ABCD + ABCD + EFGH
E
F
G
H
FIGURE 10–13
Basic concept of the parallel expander.
Figure 10–14 shows how one macrocell can borrow parallel expander terms from
another macrocell to increase the SOP output. Macrocell 2 uses three product terms from
macrocell 1 to produce an eight-term SOP expression.
LUT CPLD Architecture
This architecture differs from the classic CPLD previously discussed. As shown by the
block diagram in Figure 10–15, this device contains logic array blocks (LABs) each with
multiple logic elements (LEs). An LE is the basic logic design unit and is analogous to the
macrocell. The programmable interconnects are arranged in a row and column arrangement running between the LABs, and input/output elements (IOEs) are oriented around
the perimeter. The architecture of this type of CPLD is similar to that of FPGAs, which we
discuss in Section 10–4.
A main difference between this type of CPLD and the classic AND/OR array CPLD
previously discussed is the way in which a logic function is developed. Look-up tables
(LUTs) are used instead of AND/OR arrays. An LUT is basically a type of memory that
can be programmed to produce SOP functions (discussed in more detail in Section 10–4).
These two approaches are contrasted in Figure 10–16.
As mentioned, the LUT CPLD has a row/column arrangement of interconnects instead
of the channel-type interconnects found in most classic CPLDs. These two approaches
are contrasted in Figure 10–17 and can be understood by comparing Figure 10–9 and
Figure 10–15.
Most CPLDs use a nonvolatile process technology for the programmable links. The
LUT CPLD, however, uses a SRAM-based process technology that is volatile—all programmed logic is lost when power is turned off. The memory embedded on the chip stores
the program data using nonvolatile memory technology and reconfigures the CPLD on
power up.
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Programmable Logic
Macrocell 1
ABCD + ABCD + ABCD
Parallel expander terms
loaned to Macrocell 2
Product-term
selection
matrix
Macrocell 2
ABCD + ABCD + ABCD
+ ABCD + ABCD +
ABCD + ABCD + ABCD
Product-term
selection
matrix
A
B
C
D
E
F
FIGURE 10–14 Simplified illustration of using parallel expander terms from another
macrocell to increase an SOP expression. The red Xs and lines represent the connections
produced in the hardware by the software complier running the programmed design.
PLA (Programmable Logic Array)
As you have learned, the architecture of a CPLD is the way in which the internal elements are organized and arranged. The architecture of some PLDs is based on a PLA
(programmable logic array) structure rather than on a PAL (programmable array logic)
structure, which we have discussed. Figure 10–18 compares a simple PAL structure with
a simple PLA structure. The PAL has a programmable AND array followed by a fixed
OR array and produces an SOP expression, as shown by the example in Figure 10–18(a).
The PLA has a programmable AND array followed by a programmable OR array, as
shown by the example in Figure 10–18(b).
Specific CPLD Devices
Several manufacturers produce CPLDs. Table 10–1 lists device families from selected
companies. As time passes, a series may become obsolete or a new series may be added.
You can check the websites for the most current information.
CPLDs vary greatly in terms of complexity. Table 10–2 lists some of the parameter
ranges that are available. Keep in mind that these numbers are subject to change as technology advances.
IOE
IOE
FIGURE 10–15
IOE
IOE
IOE
LAB
LAB
LAB
Logic element
Logic element
Logic element
Logic element
Logic element
Logic element
Logic element
Logic element
Logic element
LAB
LAB
LAB
Logic element
Logic element
Logic element
Logic element
Logic element
Logic element
Logic element
Logic element
Logic element
Simplified block diagram of an LUT CPLD.
A0 A1 A 2
A0
A1
A2
LUT
1
0
0
1
1
A n–1
SOP
output
SOP
output
A n–1
(a) Look-up table logic. A 1 is stored at
each product term address.
FIGURE 10–16
(b) AND/OR array logic
Two types of logic function generation in CPLDs.
LABs
(a) Row/column interconnects
(b) Channel-type interconnect
FIGURE 10–17 LUT CPLDs have row/column interconnects. Classic CPLDs have
channel-type interconnects.
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Programmable Logic
AB + AB + AB + AB
A A B B
A A B B
(a) PAL-type array
AB + AB
AB + AB
AB + AB
AB + AB
(b) PLA-type array
FIGURE 10–18 Comparison of a basic PLA to a basic PAL type PLD architecture.
TABLE 10–1
CPLD manufacturers.
Manufacturer
Series Name
Design Software
Website
Altera
Xilinx
Lattice
Atmel
MAX
Coolrunner
ispMACH
ATF
Quartus II
ISE Design Suite
ispLEVER classic
ProChip Designer
Altera.com
Xilinx.com
Latticesemi.com
Atmel.com
TABLE 10–2
Selected CPLD parameters.
Feature
Range
Number of macrocells
Number of LABs
Maximum operating frequency
Number of I/Os
DC operating voltage
10–1700
10–221
20.4 MHz–400 MHz
10–1156
1.8 V, 2.5 V, 3.3 V, 5 V
SECTION 10–2 CHECKUP
1. What is a CPLD?
2. What does LAB stand for?
3. Describe a LAB in a typical CPLD.
4. What is the purpose of a shared expander?
5. What is the purpose of a parallel expander?
6. How does a PLA differ from a PAL?
10–3 Macrocell Modes
CPLD macrocells were introduced previously. A macrocell can be configured for combinational logic or registered logic outputs and inputs by programming. The term registered refers
to the use of flip-flops. In this section, you will learn about the typical macrocell, including
the combinational and the registered modes of operation. Although macrocell architecture
varies among different CPLDs, a typical macrocell architecture is used for illustration.
Field-Programmable Gate Arrays (FPGAs)
SECTION 10–3 CHECKUP
1. Explain the purpose of the XOR gate in the macrocell.
2. What are the two major modes of a macrocell?
3. What does the term registered refer to?
4. Besides the OR gate, XOR gate, and flip-flop, what other logic element is commonly
used in a macrocell?
10–4 Field-Programmable Gate Arrays (FPGAs)
As you have learned, the classic CPLD architecture consists of PAL/GAL or PLA-type logic
blocks with programmable interconnections. Basically, the FPGA (field-programmable gate
array) differs in architecture, does not use PAL/PLA type arrays, and has much greater
densities than CPLDs. A typical FPGA has many times more equivalent gates than a typical
CPLD. The logic-producing elements in FPGAs are generally much smaller than in CPLDs,
and there are many more of them. Also, the programmable interconnections are generally
organized in a row and column arrangement in FPGAs.
After completing this section, you should be able to
◆
Describe the basic structure of a field-programmable gate array (FPGA)
◆
Compare an FPGA to a CPLD
◆
Discuss look-up tables (LUTs)
◆
Discuss the SRAM-based FPGA
◆
Define the FPGA core
The three basic elements in an FPGA are the configurable logic block (CLB), the interconnections, and the input/output (I/O) blocks, as illustrated in Figure 10–23. The configurable logic blocks (CLBs) in an FPGA are not as complex as the LABs or function blocks
(FBs) in a CPLD, but generally there are many more of them. When the CLBs are relatively
simple, the FPGA architecture is called fine grained. When the CLBs are larger and more
complex, the architecture is called coarse grained. The I/O blocks around the perimeter
of the structure provide individually selectable input, output, or bidirectional access to the
outside world. The distributed matrix of programmable interconnections provide for interconnection of the CLBs and connection to inputs and outputs. Large FPGAs can have tens
of thousands of CLBs in addition to memory and other resources.
Most programmable logic manufacturers make a series of FPGAs that range in density,
power consumption, supply voltage, speed, and to some degree vary in architecture. FPGAs
are reprogrammable and use SRAM or antifuse process technology for the programmable
links. Densities can range from hundreds of logic modules to hundreds of thousands of logic
modules in packages with up to over 1,000 pins. DC supply voltages are typically 1.8 V to
5 V, depending on the specific device.
Configurable Logic Blocks
Typically, an FPGA logic block consists of several smaller logic modules that are the basic
building units, somewhat analogous to macrocells in a CPLD. Figure 10–24 shows the
fundamental configurable logic blocks (CLBs) within the global row/column programmable interconnects that are used to connect logic blocks. Each CLB (also known as logic
array block, LAB) is made up of multiple smaller logic modules and a local programmable
interconnect that is used to connect logic modules within the CLB.
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Programmable
interconnections
I/O
block
I/O
block
I/O
block
I/O
block
I/O
block
I/O
block
CLB
CLB
CLB
CLB
I/O
block
I/O
block
CLB
CLB
CLB
CLB
I/O
block
I/O
block
CLB
CLB
CLB
CLB
I/O
block
I/O
block
FPGA
I/O
block
I/O
block
I/O
block
I/O
block
FIGURE 10–23 Basic structure of an FPGA. CLB is configurable logic block, also known
as logic array block (LAB).
CLB
CLB
Logic module
Logic module
Logic module
Logic module
Logic module
Logic module
Local
interconnect
Local
interconnect
Logic module
Global column
interconnect
Logic module
Global row
interconnect
FIGURE 10–24 Basic configurable logic blocks (CLBs) within the global row/column
programmable interconnects.
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Field-Programmable Gate Arrays (FPGAs)
Logic Modules
A logic module in an FPGA logic block can be configured for combinational logic, registered logic, or a combination of both. A flip-flop is part of the associated logic and is used
for registered logic. A block diagram of a typical LUT-based logic module is shown in
Figure 10–25. As you know, an LUT (look-up table) is a type of memory that is programmable and used to generate SOP combinational logic functions. The LUT essentially does
the same job as the PAL or PLA does.
SOP output
A0
A1
A2
LUT
A n–1
FIGURE 10–25
Associated
logic
I/O
Logic module
Basic block diagram of a logic module in an FPGA.
Generally, the organization of an LUT consists of a number of memory cells equal to 2n,
where n is the number of input variables. For example, three inputs can select up to eight
memory cells, so an LUT with three input variables can produce an SOP expression with
up to eight product terms. A pattern of 1s and 0s can be programmed into the LUT memory
cells, as illustrated in Figure 10–26 for a specified SOP function. Each 1 means the associated product term appears in the SOP output, and each 0 means that the associated product
term does not appear in the SOP output. The resulting SOP output expression is
A2A1A0 + A2A1A0 + A2A1A0 + A2A1A0
Selection logic
Memory
cells
A2 A 1 A0
1
A2 A 1 A0
0
A2 A 1 A0
0
A0
A1
A2 A 1 A0
1
A2
A2 A 1 A0
0
A2 A 1 A0
1
A2 A 1 A0
0
A2 A 1 A0
1
SOP output
LUT
FIGURE 10–26
The basic concept of an LUT programmed for a particular SOP output.
EXAMPLE 10–2
Show a basic 3-variable LUT programmed to produce the following SOP function:
A2A1A0 + A2A1A0 + A2A1A0 + A2A1A0 + A2A1A0
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Programmable Logic
Solution
A 1 is stored for each product term in the SOP expression, as shown in Figure 10–27.
Selection logic
A0
A1
A2
Memory
cells
A2 A1 A0
0
A2 A1 A0
1
A2 A1 A0
0
A2 A1 A0
1
A2 A1 A0
1
A2 A1 A0
1
A2 A1 A0
1
A2 A1 A0
0
SOP output
FIGURE 10–27
Related Problem
How many memory cells would be in an LUT with four input variables? What would be
the maximum possible number of product terms in the SOP output?
Operating Modes of a Logic Module
Typically, a logic module (LM) can be programmed for the following modes of operation:
฀
฀
฀
฀
฀
฀
฀
฀
฀
฀
In addition to these four modes, a logic module can be utilized as a register chain to create counters and shift registers. In this section, we will discuss the normal mode and the
extended LUT mode.
The normal mode is used primarily for generating combinational logic functions. A
logic module can implement one or two combinational output functions with its two
LUTs. Examples of four LUT configurations are illustrated in Figure 10–28. Generally, two SOP functions, each with four variables or less, can be implemented in an
LM without sharing inputs. For example, you can have two 4-variable functions, one
4-variable function and one 3-variable function, or two 3-variable functions. By sharing inputs, you can have any combination of a total of eight inputs up to a maximum
of six inputs for each LUT. In the normal mode, you are limited to 6-variable SOP
functions.
The extended LUT mode allows expansion to a 7-variable function, as illustrated in Figure 10–29. The multiplexer formed by the AND-OR circuit with a complemented input is
part of the dedicated logic in a logic module.
Field-Programmable Gate Arrays (FPGAs)
FIGURE 10–28
4-input
LUT
6-input
LUT
4-input
LUT
2-input
LUT
5-input
LUT
5-input
LUT
4-input
LUT
5-input
LUT
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Examples of possible LUT configurations in a logic module (LM) in the
normal mode.
LM
5-input
LUT
7 input
variables
SOP output
5-input
LUT
Expansion of a logic module (LM) to produce a 7-variable SOP function
in the extended LUT mode.
FIGURE 10–29
EXAMPLE 10–3
A logic module is configured in the extended LUT mode, as shown in Figure 10–30. For the specific LUT outputs shown,
determine the final SOP output.
Solution
The SOP output expression is as follows:
A5A4A3A2A1A0 + A5A4A3A2A1A0 + A5A4A3A2A1A0 + A6A5A4A3A2A0 + A6A5A4A3A2A0 + A6A5A4A3A2A0
Related Problem
Show an LM configured in the normal mode to produce one SOP function with five product terms from one LUT and three
product terms from the other LUT.
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Programmable Logic
A5 A4 A3 A2 A1 + A5 A4 A3 A2 A1 + A5 A4 A3 A2 A1
A0
LM
A1
A2
A3
A4
A5
5-input
LUT
5-input
LUT
A6
A6 A5 A4 A3 A2 + A6 A5 A4 A3 A2 + A6 A5 A4 A3 A2
FIGURE 10–30
SRAM-Based FPGAs
FPGAs are either nonvolatile because they are based on antifuse technology or they are
volatile because they are based on SRAM technology. (The term volatile means that all
the data programmed into the configurable logic blocks are lost when power is turned
off.) Therefore, SRAM-based FPGAs include either a nonvolatile configuration memory
embedded on the chip to store the program data and reconfigure the device each time power
is turned back on or they use an external memory with data transfer controlled by a host
processor. The concept of on-the-chip memory is illustrated in Figure 10–31(a). The concept of the host processor configuration is shown in part (b).
CLB
Programming
data
Reprograms CLBs on
power up or reset
Nonvolatile
configuration
memory
(a) Volatile FPGA with on-the-chip nonvolatile configuration memory
Host
processor
Programming
data
Nonvolatile
configuration
memory
Volatile
FPGA
(b) Volatile FPGA with on-board memory and host processor
FIGURE 10–31 Basic concepts of volatile FPGA configurations.
Field-Programmable Gate Arrays (FPGAs)
FPGA Cores
FPGAs, as we have discussed, are essentially like “blank slates” that the end user can program for any logic design. FPGAs are available that also contain hard-core logic. A hard
core is a portion of logic in an FPGA that is put in by the manufacturer to provide a specific
function and that cannot be reprogrammed. For example, if a customer needs a small microprocessor as part of a system design, it can be programmed into the FPGA by the customer
or it can be provided as hard core by the manufacturer. If the embedded function has some
programmable features, it is known as a soft-core function. An advantage of the hard-core
approach is that the same design can be implemented using much less of the available capacity of the FPGA than if the user programmed it in the field, resulting in less space on the
chip (“real estate”) and less development time for the user. Also, hard-core functions have
been thoroughly tested. The disadvantage of the hard core is that the specifications are fixed
during manufacturing and the customer must be able to use the hard-core logic “as is.” It
cannot be changed later.
Hard cores are generally available for functions that are commonly used in digital systems, such as a microprocessor, standard input/output interfaces, and digital signal processors. More than one hard-core function can be programmed in an FPGA. Figure 10–32
illustrates the concept of a hard core surrounded by configurable logic programmed by the
user. This is a basic embedded system because the hard-core function is embedded in the
user-programmed logic.
Remaining CLBs
are programmed
by user.
Hard core:
portion of CLBs
programmed during
manufacturing for a
specific function
FIGURE 10–32
Basic idea of a hard-core function embedded in an FPGA.
Hard core designs are generally developed by and are the property of the FPGA
manufacturer. Designs owned by the manufacturer are termed intellectual property
(IP). A company usually lists the types of intellectual property that are available on its
website. Some intellectual properties are a mix of hard core and soft core. A processor
that has some flexibility in the selection and adjustment of certain parameters by the
user is an example.
Those FPGAs containing either or both hard-core and soft-core embedded processors
and other functions are known as platform FPGAs because they can be used to implement
an entire system without the need for external support devices.
Embedded Functions
A block diagram of a typical FPGA is shown in Figure 10–33. The FPGA contains
embedded memory functions as well as digital signal processing (DSP) functions. DSP
functions, such as digital filters, are commonly used in many systems. As you can see
in the block diagram, the embedded blocks are arranged throughout the FPGA interconnection matrix and input/output elements (IOEs) are placed around the FPGA perimeter.
583
584
Programmable Logic
Embedded
memory
blocks
I/O elements
Embedded
DSP
blocks
Embedded
memory
blocks
I/O
elements
IOEs
IOEs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
Embedded
memory
block
LABs
LABs
LABs
FIGURE 10–33 Example FPGA block diagram.
Specific FPGA Devices
Several manufacturers produce FPGAs as well as CPLDs. Table 10–3 lists device families
from selected companies. Check the website for the most current information.
TABLE 10–3
FPGA manufacturers.
Manufacturer
Series Name(s)
Design Software
Website
Altera
Stratix
Aria
Cyclone
Quartus II
Altera.com
Xilinx
Spartan
Artix
Kintex
Virtex
ISE Design Suite
Xilinx.com
Lattice
iCE40
MachX02
Lattice ECP3
LatticeXP2
LatticeGC/M
Lattice Diamond
iCEcube2
Latticesemi.com
Atmel
AT40
IDS
Atmel.com
FPGAs vary greatly in terms of complexity. Table 10–4 lists some of the parameter
ranges that are available. Keep in mind that these numbers are subject to change as technology advances.
Programmable Logic Software
TABLE 10–4
Selected FPGA parameters.
Feature
Range
Number of LEs
Number of CLBs
Embedded memory
Number of I/Os
DC operating voltage
1,500–813,000
26–359,000
26 kb–63 Mb
18–1200
1.8 V, 2.5 V, 3.3 V, 5 V
SECTION 10–4 CHECKUP
1. How does an FPGA differ from a CPLD?
2. What does CLB stand for?
3. Describe an LUT and discuss its purpose.
4. What is the difference between a local interconnect and a global interconnect in an
FPGA?
5. What is an FPGA core?
6. Define the term intellectual property in relation to an FPGA manufacturer.
7. What produces combinational logic functions in an LM?
8. Name the two types of embedded functions.
10–5 Programmable Logic Software
In order to be useful, programmable logic must have both hardware and software components combined into a functional unit. All manufacturers of SPLDs, CPLDs, and FPGAs
provide software support for each hardware device. These software packages are in a
category of software known as computer-aided design (CAD). In this section, programmable logic software is presented in a generic way using the traffic signal controller from
Chapters 6 and 7 Applied Logic for illustration. Tutorials for two types of software, Altera
Quartus II and Xilinx ISE, are provided on the website.
After completing this section, you should be able to
◆
Explain the programming process in terms of design flow
◆
Describe the design entry phase
◆
Describe the functional simulation phase
◆
Describe the synthesis phase
◆
Describe the implementation phase
◆
Describe the timing simulation phase
◆
Describe the download phase
The programming process is generally referred to as design flow. A basic design flow
diagram for implementing a logic design in a programmable device is shown in Figure
10–34. Most specific software packages incorporate these elements in one form or another
and process them automatically. The device being programmed is usually referred to as the
target device.
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