EXPERIMENT -3
DD LAB
Dated: 31-01-22
AJAY GUPTA
2K20/EC/17
AIM: To write Verilog code for D-flipflop and T-flipflop using behavioral modeling.
SIMULATION PLATFORM:
Xilinx ISE Suite
THEORY:
Code for D flipflop:
module d_flipflop(d, clk, clear, q, qbar);
input d;
input clk;
input clear;
output reg q;
output qbar;
always@(posedge clk)
begin
if(clear)
q<=1'b0;
else
q<=d;
end
assign qbar=~q;
Endmodule
Schematics:
RTL Schematics:
Technology Schematic:
UTILISATION AND DELAY:
========================================================================
HDL Synthesis Report
Macro Statistics
# Registers
1-bit register
:1
:1
========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Registers
Flip-Flops
:1
:1
CPU : 1.77 / 2.15 s | Elapsed : 2.00 / 2.00 s
Total memory usage is 180680 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Code for T-flip flop:
module TFF ( input clk, input rstn, input t, output reg q);
always @ (posedge clk)
begin
if (!rstn)
q <= 0;
else
if (t)
q <= ~q;
else
q <= q;
end
endmodule
Schematics:
RTL Schematic:
Technology Schmatic:
UTILISATION & DELAY
========================================================================
HDL Synthesis Report
Macro Statistics
# Registers
1-bit register
:1
:1
*
Advanced HDL Synthesis
*
========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Registers
Flip-Flops
:1
:1
========================================================================
CPU : 1.56 / 1.70 s | Elapsed : 2.00 / 2.00 s
-->
Total memory usage is 180168 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)