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Marvell switch chip 88E6321/88E6320 driver summary-hardware articles
Chip characteristics
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Marvell 88E6321/88E6320 is a 7-Port Gigabit Ethernet switching chip. Support the latest
IEEEE802.1 Audio Video Bridging standard.
The chip includes two 10, 100, and 1000 three-speed Ethernet transceivers (PHYs), two
Gigabit SERDES, and three digital interfaces (GMII\RGMII\MII combination).
The chip uses Marvell dynamic queue limit (Dynamic Queue Limit) to achieve a highspeed non-blocking 4-level QOS exchange structure. Contains a high-performance
address query engine, up to 8K nodes and 1Mbit frame buffer.
The internal MAC unit complies with the standard IEEE802.3 and supports a maximum
frame length of 10KByte.
Contains a TCAM-based Policy Control List (TCAM-based Policy Control List) engine
that supports 256 rules (only 88E6321 supports).
The chip's RGMII (or MII/RMII) interface supports direct connection to the management
device or router CPU as a MAC. 2. 6Port can be set to support a complete GMII
interface.
Gigabit SERDES interface supports SGMII, 1000BASE-X, 100BASE-FX.
The PHY unit supports 802.3az Energy Efficient Ethernet (Energy Efficient Ethernet).
Both the internal PHY unit and the MAC unit support the complete IEEE802.3 standard.
Support frame wake-up and frame time detection wake-up functions, allowing to enter
sleep mode when connected to the cpu, in order to achieve the purpose of reducing
system power consumption.
Up to 6 LEDs, corresponding functions can be configured through registers.
The chip can be configured using the SMI interface and Ethernet frames, or it can be
configured using EEPROM.
Support 8K MAC address automatic learning and aging function.
Support 25MhzXTAL clock source.
Structure diagram
can be seen from the structure diagram:
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Port 2, 5, and 6 can be configured as MAC mode or PHY mode, and all support
RGMII/RMII/MII. Port 2, 6 also support GMII.
Port 3 and 4 support 10, 100, 1000M adaptive Ethernet interface.
Port 0 and 1 support 100M and 1000M optical ports (SFP).
Pin definition
It can be seen from the pin definition that many pins have multiple functions. Most of these
multiplexed functions are valid when RESETn is low and latched on the rising edge of RESETn.
1. NO_CPU mode selection:
In the reset state (RESETn = low), after setting the NO_CPU pin level, the rising edge of
RESETn will latch the pin level. If NO_CPU=0 means that the chip is controlled by the CPU at
this time, NO_CPU=1 means that the chip is not controlled by the CPU. In the NO_CPU=0
mode, all ports are closed during initialization, and the power supply of the PHY is turned off, so
that the CPU can be started and configured before the chip works. This pin is internally pulled
up, and all ports are turned on by default.
For convenience, you can set NO_CPU to 1 for debugging. After debugging, when considering
low-power processing, you can use the NO_CPU=0 mode to shield ports that do not need to be
opened.
2. Mode selection of P5 and P2, 6 (take P5 as an example):
P5_OUT[3:0] is a multi-function pin. In the reset state (RESETn = low), the pin is in the input
state. At this time, the pin level (P5_MODE[2:0]) can be set to determine the work of the port
Mode (see the figure below), after setting the pin level, the pin level will be latched during the
rising edge of RESETn and enter the corresponding working mode.
This pin is internally pulled up, and the default working mode is RGMII. For other modes, you
can directly connect a 4.7K resistor to GND for configuration. I set it to 0x04RMII mode here,
so P5_MODE[1:0] pin Ground through a 4.7K resistor.
in NO_CPU=1 mode, P5_CRS, P5_COL are used as MDC_PHY, MDIO_PHY function is used
to manage the external SMI slave device (such as external PHY), otherwise it is used as
GPIO[8:7].
3. Addressing mode
Because 88E6321 itself is powerful, it can be used as MAC, PHY (2 Port), SERDES (2 Port), so
although it is only one chip, it can be regarded as multiple devices, which will face the problem
of address determination , How to assign addresses to the on-chip PHY, SERDES, and MAC. To
solve this problem, 88E6321 has two chip addressing modes: single-chip addressing and multichip addressing. The device address can be set by setting the level of the ADDR[4:0]n pin in the
reset state ( note that the address set by ADDR is the inverse of the actual SMI address, that
is, the actual SMI address corresponding to ADDR=0x1F It is 0x00, and ADDR=0x00
corresponds to the actual SMI address 0x1F, which needs to be noted below ).
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Single-chip addressing mode: when ADDR[4:0]n=0x1F, enter the single-chip addressing
mode, at this time through the internal address direct access, in this mode, 88E6321 will
respond to all 32 SMI addresses, so it must Make sure it is the only SMI slave device. In
the device register map, the SMI device address 0X10-0X16 (corresponding to Port0Port7), 0X1B-0X1D (corresponding to the special register Global1-3) can be directly
accessed, and the address 0X03, 0X04 (corresponding to Port3, 4 PHY), 0X0C, 0X0D
(corresponding to Port0, 1 SERDES), you need to use the Global2 address SMI PHY
Command and SMI PHY Data two registers for indirect access.
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Multi-chip addressing mode: When ADDR[4:0]n!=0x1F, it enters the multi-chip
addressing mode. At this time, 88E6321 will only respond to the inverse code of the
address set by ADDR, and only two registers can directly Access (SMI Command
register and SMI Data register), and other registers are accessed indirectly through these
two registers (including the registers accessed indirectly in the single-chip addressing
mode).
4. Slave SMI interface
When the 88E6321 is used as an SMI slave device, the master can manage the 88E6321 through
this interface (MDC_CPU and MDIO_CPU). MDC_CPU supports up to 20MHz, MDIO_CPU
needs an external pull-up resistor from 4.7K to 10K. It should be noted that this interface can
only communicate when INTn is low.
INTn is an interrupt pin, used to indicate whether an interrupt that is not masked by a mask is
generated. Since this pin is an open-drain output and low-level is active, it must be pulled up
externally so that it is not high-level at all times when there is no interruption. At the same time,
when the pin is active at low level, it also means that the SMI interface can be used. (During the
power-on process, the chip will load the register settings from the external EEPROM (if
any), then issue an EEPROM processing completion interrupt, and pull down INTn)
5.PHY interface
Port3 and Port4 support 10/100/1000 three-speed PHY, and support 10BASE-T, 100BASE-TX,
and 1000BASE-T in the IEEE standard.
6. SERDES interface
Port0 and Port1 are SERDES interfaces, and their working modes can be selected through
configuration:
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The three-speed PHY SERDES connected to Marvell can be configured as a three-speed
PHY interface for connecting to an external PHY. At this time, the SERDES uses the
SGMII protocol.
Fiber optic module connected to 1000BASE-X
SGMII interface The SERDES working mode can be configured by setting the
Px_SMODE pin level:
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Cascading with other Marvell exchange chips
LED interface
88E6321 adopts matrix LED interface, so that each PHYPort can be assigned 2 LEDs. The
cathodes of the LEDs are connected to a row signal line (Rx_LED), and the anodes are
connected to the column signal line (Cx_LED). The LED pins can form a matrix of LEDs with 3
rows and 2 columns. The LED mapping is as follows:
typical circuit connection diagram:
LED line signal (Cx_LED) is shared with EEPROM, and time division multiplexing is used to
avoid mutual interference between LED and EEPROM operations.
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LED options By configuring the LED Control register (offset=0x16) of the respective
Port, you can set the function of each LED:
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Power-on parameter settings The initialization function of the LED after power-on can be
configured by LED_SEL[1:0]. These hardware are internally pulled up, the default is 0x03, and
the initial configuration can be changed by externally pulling down a 4.7K resistor in the reset
state.
1.LED_SEL[1:0]=0x03
One LED displays the network connection (Link) and network activity (Activity), and the other
LED is used to display the higher rate connection (Gig Link).
2.LED_SEL[1:0]=0x02
One LED displays the gigabit network connection and network activity, and the other LED is
used to display the 10/100M network connection and network activity.
3.LED_SEL[1:0]=0x01
Used for two-color or three-color LED, different colors display network connection and network
activity under different network speeds.
4.LED_SEL[1:0]=0x00
used for single LED display. Different flashing frequencies are used to indicate different network
speeds, connections, and network activities. The default flashing frequency is as follows: 1Gbps:
84ms, 100Mbps: 170ms, 10M: 340ms.
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above is the introduction of 88E6321 about hardware.
Here I use stm32 to connect to Port5 of 88E6321 through RMII, Port4 to electrical port Ethernet,
and Port5 to SFP optical port Ethernet.
Different from general PHY devices with single function (such as LNA8720A), the
operation of 88E6321's PHY-related registers is relatively complicated. Please refer to the
following introduction for specific operation methods.
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