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16-QAM transmitter and receiver design based on FPGA
Conference Paper · January 2010
DOI: 10.1109/DELTA.2010.34 · Source: DBLP
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2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
16-QAM Transmitter and Receiver Design Based on FPGA
Xuan-Thang Vu
Electronics& Telecommunication Faculty
College of Technology, VNU
Hanoi, Vietnam
thangvx@vnu.edu.vn
Nguyen Anh Duc
Electronics&Telecommunication Faculty
Hanoi University of Technology
Hanoi, Vietnam
ducnv-fet@mail.hut.edu.vn
In communication, synchronization which consists of
both carrier and symbol level is the most challenging task.
There have been several researchers paying attention to solve
synchronization problem in particular, hence build a whole
communication system. The authors in [1] present a diagram
for carrier synchronization which uses phase-difference
detecting technique applied to QPSK signal, and the
principle of time recovery is mentioned as well. In [2], the
authors deal with the more challenging issues, say QAM
models. Because QAM signal has multiple amplitude levels,
a much more complex phase-difference detector is required.
The paper [5] provides a demo diagram for 16-QAM in
System Generator, which implements an adaptive equalizer
deploying LMS algorithm. However, this diagram is just fit
to a special phenomenon, thus cannot apply to practical
QAM systems.
In this paper, we present a diagram of a complete 16QAM scheme and the implementing results based on Xilinx
Virtex 4 FPGA Kit as well. The modulator and the
demodulator are performed in the two separated Kits. Both
carrier synchronization and symbol synchronization are
taken into account in this model using fast computing tool
(CORDIC) and LMS algorithm. The remaining of this paper
is presented as follow: section II denotes the demo diagram
for 16-QAM developed by [5], which consists of two
important bocks which are Adaptive Equalizer bock and
Carrier Recovery block. Section III states the 16-QAM
transmitter design. The most important part, the receiver, is
demonstrated in the section IV, and the implementing results
and conclusion are discussed in the section V.
Abstract— The FPGA technology has been playing a
considerable role in portable and mobile communication. This
is due to the features of
flexibility, accuracy and
configurability in designing and implementation. The paper
presents a complete design for a 16-QAM transmitter and
receiver based on the Virtex4 FPGA Kit. The implemented
system can be applied in particle. Based on the principles of
carrier synchronization, time synchronization, core tools for
phase-different detecting as well as adaptive equalization
processing in System Generator (a software of Xilinx), the
authors have designed a complete baseband IF 16-QAM
system, in which the baseband signal is upconverted into IF
frequency (up to 12MHz) at the transmitter and then is
downconverted at the receiver. After timing synchronizing, the
adaptive equalizing and phase recovering, the received
baseband signal is displayed in the oscilloscope’s screen. These
accurate experiments conducted in Virtex 4 FPGA board kit
have shown a promising foundation for developing coding,
algorithms in 16-QAM modulation scheme.
Keywords: FGPA design, Carrier Synchronization, Symbol
Recovery, 16-QAM Modulation.
I. INTRODUCTION
The
development
of
mobile
and
portable
communications requires not only high performance of
hardware systems but also affectivity and flexibility in
design and implementation. In such situation, silicon
technology is one of the best choices which allow us to
produce high execution, high integrated density and
dedicated purpose integrated circuits (IC). However, silicon
solution is not sufficient for incessantly developing wireless
communication at the moment and in the future. Fortunately,
FPGA and ASIC technology has been merging as a suitable
selection for the next communication systems design. With
flexibility in design and precision in timing control, FPGA
makes it easier and more accurate in simulating, testing,
validating and implementing components. In addition,
system-level design which has being developed recently,
such as System Generator (Sysgen), makes design tasks
much easier than it has ever been before. Designers can
easily test algorithms, perform the whole system or modify
and update diagram shortly [1, 2, 3]. For this reason, systemlevel design is playing a considerable role in designing and
implementing.
978-0-7695-3978-2/10 $26.00 © 2010 IEEE
DOI 10.1109/DELTA.2010.34
Trinh Anh Vu
Electronics& Telecommunication Faculty
College of Technology, VNU
Hanoi, Vietnam
vuta@vnu.edu.vn
A BASE-BAND DEMODULATOR DEMO OF SYSTEM
GENERATOR [5]
The System Generator library provides a demo for 16QAM baseband demodulator which consists of two main
blocks: Adaptive Equalizer and Carrier Recovery (figure 1).
The Adaptive Equalizer operates based on LMS algorithm
and uses a 32-tap filter. Fast computing techniques using
CORDIC is employed to correct the phase error. This demo
uses a standard constellation as a training sequence. The
adaptive algorithm does work to minimize errors, hence
adjusts the constellation correct. However, because of these
features, this design can not be applied to deep fading
channels phenomenon
II.
95
complex Mult which output format is fixed 14 bits with 12
bits binary point. These IF waves are transmitted through
two integrated DACs on Virtex-4 XtreamDSP Development
Kit.
Figure 1. 16-QAM demolator demo from Xilinx
Figure 3. Data Transmitter for 16-QAM
The Carrier Recovery block shown in figure 2 uses the
Phase-difference Detector as well as the Local Oscillator
(DDS) method [2]. The Phase-Different Signal Filter is
appropriately selected with the spectrum in which we detect
the difference. In this diagram, DDS will mimic Doppler
frequency (which is low compared with data rate) then
eliminate it.
However, when we change the delay in transmission line,
i.e. the channel, this demo does not work correctly at all. So
this scheme can not be applied in practice due to the lack of
the time-synchronized sampler and the IF up-converter
which are required to be compatible with real propagations.
Figure 4. IF up-converter
IV.
16-QAM RECEIVER DESIGN
The [5] has already provided a demo for 16-QAM receiver.
However, since this design just composes of Adaptive
Equalizer, it works properly in a particular phenomenon in
which Doppler takes effect directly on baseband signal
without carrier wave. To cope with general cases, a LO is
created to down-convert IF signal to baseband one. In
addition, Timing Synchronization block, considerably, is
added as well as some other blocks.
Figure 2. PLL for carrier phase synchronization.
III. 16-QAM TRANSMITTER DESIGN
The transmitter can be designed easily from the principle
block diagram of 16-QAM which consists of two main parts:
data block and IF block. The data source is denoted in figure
3. In this paper, we use random data source to capture all
possibilities of data statistic. However, that can be from file
without any trouble. Two four – level random data sequences
are generated corresponding to I and Q signal of 16-QAM at
the rate of 4 clock periods. These signals then go to the
mapping block to create the standard constellation which will
be used as pilot in the receiver. A 28 – tap, 4 – interpolated
factor raised cosine filter is deployed to shape baseband
signal and degrade spectrum.
The up-converter is described in the figure 4. A counter
clocking at rate of 1/64 manages two lookup tables to
produce 6-bit width sine and cosine IF wave. These signals
are then multiplied with baseband data by a low-complexity
Figure 5. 16-QAM demodulator diagram
Figure 5 shows the block diagram of the 16-QAM
receiver. The received analogue signals are sampled at the
Nyquist rate before coming to down-converter block. A LO
at the receiver generates sine and cosine wave which are
multiplied with arrival signals. By that way, the different
phase between transmit LO and receive LO in carrier domain
is shifted to baseband domain. The error phase will be
96
processed in Adaptive Equalizer and Phase Recovery right
after Interpolator (Filters and Upsample) and Timing
Synchronization blocks.
The details of Filter and Upsample are denoted in figure
6. The quality of the receiver depends significantly on how
accurately the sampler clocks in centre of symbol’s period
(where the amplitude is large). Therefore, the base-band
signal is up-sampled 4 times, then going through the second
filter for smoothing the signal and detecting the accurate
sample point, leading to fast convergent process on the next
steps.
V.
RESULTS AND CONCLUSIONS
After testing model on simulation, the simulation design
is compiled to ISE file before generating the programming
file, bit file. Figure 9 shows the resources used in this model
which just takes a small part in Xilinx Virtex-4 Kit.
The mother clock period is set 1/1024 corresponding to
9ns, hence the data rate is approximately 100kbps. The
higher rate can be reached by changing the mother clock
period or degrading the width of IF wave.
Figure 6. Filter and Up-sampler
Figure 9. Resources used
The Timing Synchronization block operates based on
minimum differential detection (figure 7). Incoming signal is
passed through differential. This differential signal will
controls sampler to clock at the point corresponding to peak
of baseband signal. The time synchronized signal is then go
to the Adaptive Equalizer and Phase detector.
Figure 10 plots the received data after timing
synchronization but non phase recovery. The rotated signal is
shown in figure 11. It is clear that our receiver demodulates
correctly.
Figure 7. Timing Synchronization Diagram
Figure 10. The rotated signal
Signal equalization could be implemented in pass-band
or base-band domain [4]. In this design, the Adaptive
Equalizer and Carrier Recovery blocks are after the Downconverter, i.e. equalizing is performed in the base-band
domain as shown in the schematic diagram below (figure 8).
Figure 11. The de-rotated signal at the receiver on the oscilloscope
Figure 8. Principle of Baseband Equalizer
These results is corresponding to merely 16-QAM
without coding technique, and the LMS uses standard
constellation as pilot sequence. The performance can be
97
improved if we employ known pilot sequence. This system is
a good platform to test and develop coding techniques,
algorithms and other further QAM systems.
ACKNOWLEDGMENT
This paper is supported by the Project QC 09.10 in
College of Technology, VNUH.
REFERENCES
[1]
[2]
[3]
[4]
[5]
C. Dick, F.Harris, M.Rice, Synchoronization in Software RadiosCarrier and Timing Recovery Using FPGAs, Proceeding of 2000
IEEE Symposium on Field-Programmable Custom Computing
Machines.
C.Dick, F.Harris, M.Rice,
FPGA Implementation of Carrier
Synchronization for QAM Receivers, Journal of VLSI Signal
Processing, Vol 36, p 57-71,2004.
Joaquin Garcia, Rene Cumplido, On the design of an FPGA-Based
OFDM modulator for IEEE 802.11a, Proceeding of ICEEE,
September 7-9, 2005, Mexico.
John G. Proakis, Digital Communication, McGraw-Hill 1993.
http://www.xilinx.com
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