UNESCO-NIGERIA TECHNICAL &
VOCATIONAL EDUCATION
REVITALISATION PROJECT-PHASE II
NATIONAL DIPLOMA IN
ELECTRICAL ENGINEERING TECHNOLOGY
ELECTRONICS (II)
COURSE CODE: EEC 234
YEAR II- SEMESTER III
THEORY
Version 1: December 2008
1
TABLE OF CONTENTS
Week 1
----------------------------------------------------------------------------------------1
1.1 FIELD EFFECT TRANSISTOR(FET
1.2 INTRODUCTION
1.3 Basic Operation
Week 2-------------------------------------------------------------------------------------------------4
1.4 JFET Transfer Characteristic
Week 3-------------------------------------------------------------------------------------------------6
1.5 MUTUAL CONDUCTANCE
Week 4-------------------------------------------------------------------------------------------------10
1.6 Handling Precautions
Week 5-------------------------------------------------------------------------------------------------12
1.6 Input Resistance
1.6.1Basic MOSFET Structure and Symbol
1.6.2 Depletion-mode MOSFET
1.6.3 Depletion-mode N-Channel MOSFET and circuit Symbols
1.6.4 Enhancement-mode MOSFET
1.6.5 Enhancement-mode N-Channel MOSFET and circuit Symbols
1.6.6 INPUT RESISTANCE/CAPACITANCE
Week 6----------------------------------------------------------------------------------------------17
2. BIASING, AC EQUIVALENT CIRCUIT AND GAIN OF STAGES
2.1 DC BIASING
2.1.1 DC Load Line
Week 7------------------------------------------------------------------------------------------------21
2.2 INTRODUCTION
2.2.1 r- Parameters
Week 8------------------------------------------------------------------------------------------------26
2.3 COMMON EMITTER CONFIGURATION
2. 3.1 Power Gain
2.3.2 Voltage Gain
2.3.3Current Gain
Week 9--------------------------------------------------------------------------------------------29
2.4.3 COMMON COLLECTOR CONFIGURATION
2.4.1 Voltage Gain
2.4.2 Current Gain
2.4.3 Power Gain
Week 10-------------------------------------------------------------------------------------------31
2.5 COMMON BASE
CONFIGURATION
2.5.1 Voltage Gain
2.5.2 Current Gain
2.5.3 Power Gain
Week 11-------------------------------------------------------------------------------------------33
3. TRANSFORMER COUPLING, POWER AND MULTISTAGE OF AMPLIFIERS
3.1 INTRODUCTION
3.1.1 TRANSFORMER COUPLING
3.1.2 Complementary Symmetry Transistors
3.1.3 Crossover Distortion
Week 12--------------------------------------------------------------------------------------------36
3.2
3.2.1
3.2.2
INTRODUCTION
RESISTANCE – CAPACITANCE COUPLING (RC)
FREQUENCY RESPONSE AND BANDWIDTH
Week 13--------------------------------------------------------------------------------------------39
3.3 AMPLIFIERS & SMALL SIGNAL ANALYSIS
Week 14--------------------------------------------------------------------------------------------44
3.4 MULTISTAGE AMPLIFIERS
3.4.1Multistage Voltage Gain
3.4.2 Voltage Gain Expressed in Decibels
3.4.3 Loading Effects
Week 15----------------------------------------------------------------------------------------------47
3.5 COMPLEX AMPLIFIER CIRCUIT
FIELD EFFECT TRANSISTOR(FET)
Week 1
1.1 INTRODUCTION
FETs are unipolar devices because, unlike BJTs that use both electron and hole current, they
operate only with one type of charge carrier.
The two main types of FETs are the junction field-effect transistor (JFET) and the metal oxide
semiconductor field- effect transistor (MOSFET).
Recall that a BJT is a current-controlled device; that is, the base current controls the amount of
collector current. A FET is different. It is a voltage-controlled device, where the voltage between
two of the terminals (gate and source) controls the current through the device. As you will learn, a
major feature of FETs is their very high input resistance.
The JFET (junction field-effect transistor) is a type of FET that operates with a reverse-biased p-n
junction to control current in a channel. Depending on their structure, JFETs fall into either of two
categories, n channel or p channel.
Figure 1-1 (a) shows the basic structure of an n-channel JFET (junction field-effect transistor). Wire
leads are connected to each end of the n-channel; the drain is at the upper end, and the source is at
the lower end. Two p-type regions are diffused in the n type material to form a channel, and both ptype regions are connected to the gate lead. For simplicity, the gate lead is shown connected to only
one of the p regions. A p-channel JFET is shown in Figure 1.l(b).
FIGURE 1.1 Basic STRUCTURE OF THE TYPES OF FET’S
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FIELD EFFECT TRANSISTOR(FET)
Week 1
1.2 Basic Operation
To illustrate the operation of a JFET, Figure 1.2 shows dc bias voltages applied to an nchannel device. V dd provides a drain-to-source voltage and supplies current from drain to source. V
GG sets the reverse-bias voltage between the gate and the source, as shown. The JFET is always
operated with the gate-source pn junction reverse-biased. Reverse- biasing of the gate-source
junction with a negative gate voltage produces a depletion region along the pn junction, which
extends into the n channel and thus increases its resistance by restricting the channel width. The
channel width and thus the channel resistance can be controlled by varying the gate voltage. thereby
controlling the amount of drain current, Id Figure 1.3 illustrates this concept. The white areas
represent the depletion region created by the reverse bias. It is wider toward the drain end of the
channel because the reverse-bias voltage between the gate and the drain is greater than that between
the gate and the source. We will discuss JFET characteristic curves and some important
CHARACTERISTICS AND PARAMETERS
FIGURE 1.2 A BIASED N-CHANNEL JFET
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FIELD EFFECT TRANSISTOR(FET)
Week 1
FIGURE 1.3 EFFECT OF VGS ON CHANNEL WIDTH,AND DRAIN CURRENT(VGG = VGG)
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FIELD EFFECT TRANSISTOR(FET)
Week 2
1.3 JFET Transfer Characteristic
You have learned that a range of VGS values from zero to VGS(off) controls the amount of
drain current. For an n-channel JFET. V GS(offj is negative. and for a p-channel JFET. V GS off) is
positive_ Because V GS does control ID' the relationship between these two quantities is very important. Figure 2.1 is a general transfer characteristic curve that illustrates graphically the
relationship between V GS and ID'
FIGURE 2.1 Transfer Characteristic Curve (n – channel)
Notice that the bottom end of the curve is at a point on the V GS axis equal to VGS (Off) and
the top end of the curve is at a point on the ID axis equal to loss. This curve, of course. shows
that the operating limits of a JFET are
ID = 0 when V GS = VGS(off)
and
ID = IDss when V GS = 0
The transfer characteristic curve can be developed from the drain characteristics curves
by plotting values of 10 for the values of V GS taken from the family of drain curves at pinchoff, as illustrated in Figure 1 for a specific set of curves. Each point on the transfer characteristic curve corresponds to specific values of V GS and ID on the drain curves. For
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FIELD EFFECT TRANSISTOR(FET)
Week 2
FIGURE 2.2 EXAMPLE OF THE DEVELOPMENTAL OF AN n-channel JFET TRANFER
CHARACTERISTIC CURVE(BLUE) FROM THE JFET DRAIN CHARACTERISTIC
CURVES(GREEN)
example, when V GS = -2 V, 10 = 4.32 mA. Also, for this specific JFET, VGS(off) = -5 V
and loss = 12 mA.
A JFET transfer characteristic curve is expressed as
With Equation above,ID can be determined for any V GS if VGS(off) and loss are known. These
quantities are usually available from the data sheet for a given JFET. Notice the squared
term in the equation. Because of its form, a parabolic relationship is known as a square law
and therefore, JFETs and MOSFETs are often referred to as square-law devices.
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FIELD EFFECT TRANSISTOR(FET)
Week 3
1.4 MUTUAL CONDUCTANCE
The forward transconductance (transfer conductance), gm' is the change in drain current
(∆ID )for a given change in gate-to-source voltage ( ∆V Gs ) with the drain-to-source voltage
constant. It is expressed as a ratio and has the unit of siemens (S).
Other common designations for this parameter are gfs and Yfs (forward transfer admittance).
As you will see, gm is imponant in FET amplifiers as a major factor in determining the voltage gain.
Because the transfer characteristic curve for a JFET is nonlinear. Gm varies in value depending on the location on the curve as set by VGs ' The value for gm is greater near the top of
the curve (near VGS = 0) than it is near the bottom (near VGS(off)' as illustrated in Figure 3.1
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FIELD EFFECT TRANSISTOR(FET)
Week 3
FIGURE 3.1 Illusration of Mutual Conductance
A data sheet normally gives the value of gm measured at VGS = 0 V (gmo). For example, the
data sheet for the 2N5457 JFET specifies a minimum gmo (Yrs) of 1000 S with VDS = 15 V.
Given gmo, you can calculate an approximate value for gm at any point on the transfer
characteristic curve using the following formula:
When a value of gmo is not available, you can calculate it using values of lDss and VGS(off)'
The vertical lines indicate an absolute value (no sign).
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FIELD EFFECT TRANSISTOR(FET)
Week 3
EXAMPLE 3.1
The following information is included on the data sheet for a 2N5457
JFET: typically. IDss = 3.0 mA. VGS(off) = -6 V maximum, and Yfs(max)= 5000 µS.
Using these values, determine the forward transconductance for VGS = -4 V, and find
ID at this point.
1.3.1 Drain-to-Source Resistance
You learned from the drain characteristic curve that, above pinch-off, the drain current is
relatively constant over a range of drain-to-source voltages. Therefore, a large change in VDS
produces only a very small change in ID. The ratio of these changes is the drain-to-source
resistance of the device, Data sheets often specify this parameter in terms of the output conductance,
gas, or output admittance,
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FIELD EFFECT TRANSISTOR(FET)
Week 3
Data sheets often specify this parameter in terms of the output conductance, gas, or output
admittance, Yos'
4
FIELD EFFECT TRANSISTOR(FET)
Week 4
1.5 Handling Precautions
All MOS devices are subject to damage from electrostatic discharge (ESD). Because the gate
of a MOSFET is insulated from the channel, the input resistance is extremely high (ideally infinite). The gate leakage current, IGss, for a typical MOSFET is in the pA range, whereas the
gate reverse current for a typical JFET is in the nA range. The input capacitance results from
the insulated gate structure. Excess static charge can be accumulated because the input capacitance combines with the very high input resistance and can result in damage to the device.
To avoid damage from ESD, certain precautions should be taken when handling MOSFETs:
1. MOS devices should be shipped and stored in conductive foam.
2. All instruments and metal benches used in assembly or test should be connected
to earth ground (round or third prong of 110 V wall outlets).
3. The assembler's or handler's wrist should be connected to earth ground with a
length of wire and a high-value series resistor.
4. Never remove a MOS device (or any other device. for that matter) from the circuit
while the power is on. 3. The assembler's or handler's wrist should be connected to earth ground
with a
length of wire and a high-value series resistor.
4. Never remove a MOS device (or any other device. for that matter) from the circuit
while the power is on.
5. Do not apply signals to a MOS device while the dc power supply is off.
1.4.1 GENERAL PRECAUTIONS
•Always preheat the FET (150oC for 2 minutes) to minimize the thermal shock and mechanical
stress.
•The temperature variation from the preheat stage to the maximum temperature should be less than
100oC.
•Never exceed 230oC for 20 seconds, 220oC for 30 seconds and 200 oc for 60 seconds.
•The device should be allowed to cool naturally for at least 3 minutes. Forced cooling may result in
failure due to
mechanical stress.
1.4.2 HANDLING
The package has a source pad (base) at the bottom of the package and two source leads. Both
the source leads and source pad should be soldered to the heat sink for better performance. The RF
input and output leads should be soldered to the microwave circuit onthe PC board.
AMCOM's Plastic Packaged Power FETs are very sensitive to electrostatic
discharge (ESD). AMCOM ships all Power FETs in electrostatic protection
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FIELD EFFECT TRANSISTOR(FET)
Week 4
packaging. Users must be very careful when handling the FETs and should
be properly grounded by a wrist strap or equivalent technique.
AMCOM's Plastic Packaged Power FETs have four pre-tinned copper leads
and a pre-tinned base. Two of the copper leads are RF input and output
leads. The other two are the grounding leads. The base of the package
serves simultaneously as DC ground, RF ground, and thermal path. Personnel handling the FETs should be very careful to avoid the destruction of
the coplanarity between the leads and the base. The FETs are shipped in
a tray as shown in Figure 1. Be sure to pay careful attention to the
handling precautions during removal.
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FIELD EFFECT TRANSISTOR(FET)
Week 5
1.6 Input Resistance
As well as the Junction Gate FET their is another type of FET transistor available
whose gate is insulated from the main current carrying channel. The most common type of
insulated gate FET or IGFET is the Metal Oxide Semiconductor Field Effect Transistor
or MOSFET for short.
The MOSFET type of field effect transistor has a "Metal Oxide" gate (usually silicon dioxide
commonly known as glass), which is electrically insulated from the main semiconductor N
or P-channel. This isolation of the controlling gate makes the input resistance of the
MOSFET extremely high in the Mega-ohms region and almost infinite. As the gate terminal
is isolated from the main current carrying channel "NO current flows into the gate" and like
the JFET acts like a voltage controlled resistor. Also like the JFET, this very high input
resistance can easily accumulate large static charges resulting in the MOSFET becoming
easily damaged unless carefully handled or protected.
1.6.1Basic MOSFET Structure and Symbol
We also saw previously that the gate of a JFET must be biased in such a way as to
forward-bias the PN junction but in a MOSFET device no such limitations applies so it is
possible to bias the gate in either polarity. This makes MOSFET's specially valuable as
electronic switches or to make logic gates because with no bias they are normally nonconducting and the high gate resistance means that very little control current is needed.
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FIELD EFFECT TRANSISTOR(FET)
Week 5
Both the P-channel and the N-channel MOSFET's are available in two basic forms, the
Enhancement type and the Depletion type
1.6.2 Depletion-mode MOSFET
The Depletion-mode MOSFET, which is less common than the enhancement types
is normally switched "ON" without a gate bias voltage but requires a gate to source voltage
(Vgs) to switch the device "OFF". Similar to the JFET types. For N-channel MOSFET's a
"Positive" gate voltage widens the channel, increasing the flow of the drain current and
decreasing the drain current as the gate voltage goes more negative. The opposite is also
true for the P-channel types. The depletion mode MOSFET is equivalent to a "Normally
Closed" switch.
1.6.3 Depletion-mode N-Channel MOSFET and circuit Symbols
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FIELD EFFECT TRANSISTOR(FET)
Week 5
Depletion-mode MOSFET's are constructed similar to their JFET transistor counterparts
where the drain-source channel is inherently conductive with electrons and holes already
present within the N-type or P-type channel. This doping of the channel produces a
conducting path of low resistance between the drain and source with zero gate bias.
1.6.4 Enhancement-mode MOSFET
The more common Enhancement-mode MOSFET is the reverse of the depletionmode type. Here the conducting channel is lightly doped or even undoped making it nonconductive. This results in the device being normally "OFF" when the gate bias voltage is
equal to zero.
A drain current will only flow when a gate voltage (Vgs) is applied to the gate terminal. This
positive voltage creates an electrical field within the channel attracting electrons towards
the oxide layer and thereby reducing the overall resistance of the channel allowing current
to flow. Increasing this positive gate voltage will cause an increase in the drain current, Id
through the channel. Then, the Enhancement-mode device is equivalent to a "Normally
Open" switch.
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FIELD EFFECT TRANSISTOR(FET)
Week 5
1.6.5 Enhancement-mode N-Channel MOSFET and circuit Symbols
Enhancement-mode MOSFET's make excellent electronics switches due to their low "ON"
resistance and extremely high "OFF" resistance and extremely high gate resistance.
Enhancement-mode MOSFET's are used in integrated circuits to produce CMOS type
Logic Gates and power switching circuits as they can be driven by digital logic levels.
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FIELD EFFECT TRANSISTOR(FET)
Week 5
Enhancement-mode MOSFET's make excellent electronics switches due to their low "ON"
resistance and extremely high "OFF" resistance and extremely high gate resistance.
Enhancement-mode MOSFET's are used in integrated circuits to produce CMOS type
Logic Gates and power switching circuits as they can be driven by digital logic levels.
1.6.6 INPUT RESISTANCE/CAPACITANCE
As you know, a JFET operates with its gate-source junction reverse-biased. which makes
the input resistance at the gate very high. This high input resistance is one advantage of the
JFET over the BJT. (Recall that a bipolar junction transistor operates with a forward-biased
base-emitter junction.) JFET data sheets often specify the input resistance by giving a value
for the gate reverse current, IGss, at a certain gate-to-source voltage. The input resistance
can then be determined using the following equation, where the vertical lines indicate an
absolute value (no sign)
5
2. BIASING,AC EQUIVALENT CIRCUIT AND Week 6
GAINOF STAGES
2.1 DC BIASING
Bias establishes the dc operating point for proper linear operation of an
amplifier. If an amplifier is not biased with correct dc voltages on the input and
output. It can go into saturation or cutoff when an input signal is applied. Figure 6-1
shows the effects of proper and improper de biasing of an inverting amplifier. In part
(a), the output signal is an amplified replica of the input signal except that it is
inverted, which means that it is 1800 out of phase with the input. The output signal
swings equally above and below the dc bias level of the output, V DC(out). Improper
biasing can cause distortion in the output signal, as illustrated in parts (b) and (c). Part
(b) illustrates limiting of the positive portion of the output voltage as a result of a Qpoint (dc operating point) being too close to cutoff. Part (c) shows limiting of the
negative portion of the output voltage as a result of a dc operating point being too
close to saturation.
FIGURE 6.1 Examples of linear and nonLinear operation of inverting Amplifier
Graphical Analysis The transistor in Figure 6-2(a) is biased with variable voltages Vcc
and VBB to obtain certain values of lB' Ic, IE, and VCE ' The collector characteristic
curves for this particular transistor are shown in Figure 6-2(b); we will use these
curves to graphically illustrate the effects of dc bias.
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2. BIASING,AC EQUIVALENT CIRCUIT AND Week 6
GAINOF STAGES
FIGURE 6.2 A dc-biased transistor circuit with variable bias voltages (VBB and Vcc )
for generating the collector characteristic curves shown in part (b).
In Figure 6-3, we assign three values to IB and observe what happens to Ic and VCE '
First. V BB is adjusted to produce an I B of 200 /-LA, as shown in Figure 6-3(a).
Since IC = βDCIB, the collector current is 20 mA, as indicated, and
2.1.2 DC Load Line
Notice that when I B increases, Ic increases and V CE decreases. When IB
decreases, Ic decreases and V CE increases. As VBB is adjusted up or down, the dc
operating point of the transistor moves along a sloping straight line, called the dc load
line, connecting each separate Q-point. At any point along the line, values of IB' Ic,
and VCE can be picked off the graph, as shown in Figure 6-4.
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2. BIASING,AC EQUIVALENT CIRCUIT AND Week 6
GAINOF STAGES
The dc load line intersects the VCE axis at 10 V. the point where VCE = Vcc . This is
the transistor cut-off point because I B and Ic are zero (ideally). Actually. there is
small leakage current, I CBO , at cut off as indicated, and therefore VCE is slightly less
than 10V but nomally this can be neglected.
FIGURE 6.3Illusration of Q Point Adjustment
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2. BIASING,AC EQUIVALENT CIRCUIT AND Week 6
GAINOF STAGES
FIGURE 6.4 the DC LOAD LINES
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2. BIASING,AC EQUIVALENT CIRCUIT AND GAIN OF Week 7
STAGES
2.2 INTRODUCTION
Dc quantities were identified by nonitalic uppercase (capital) sub- scripts such as Ic, IE, VC
and VCE Lowercase italic subscripts are used to indicate ac quantities of rms, peak, and peak-topeak currents and voltages: for example, IC, Ie, Ib,VC, and VCE (rms values are assumed unless
otherwise stated). Instantaneous quantities are represented by both lowercase letters and subscripts
such as iC,ie, iB, and vCE . Figure 7.1 illustrates these quantities for a specific voltage waveform.
FIGURE 7.1 SHOWING PARAMETERS
In addition to currents and voltages, resistances often have different values when a circuit is
analyzed from an ac viewpoint as opposed to a dc view point. Lowercase subscripts are used to
identify ac resistance values. For example. R, is the ac collector resistance, and R c is the dc collector
resistance. You will see the need for this distinction later. Resistance values internal to the transistor
use a lowercase r'. An example is the internal ac emitter resistance, r´e
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2. BIASING,AC EQUIVALENT CIRCUIT AND GAIN OF Week 7
STAGES
To visualize the operation of a transistor in an amplifier circuit. it is often useful to
represent the device by an equivalent circuit. An equivalent circuit uses various
internal transistor parameters to represent the transistor's operation. Equivalent circuits are described
in this section based on resistance or r parameters. Another system of parameters, called h
parameters, are briefly described.
After completing this section, you should be able to
· Identify and apply internal transistor parameters
· Define the r parameters
. Represent a transistor by an r-parameter equivalent circuit
. Distinguish between the dc beta and the ac beta
. Define the h parameters
2.2.1 r- Parameters
The resistance, r; parameters are the most commonly used for BJTs. The five r parameters are given
in Table 7-1. The italic lowercase letter r with a prime denotes resistances internal to the transistor.
TABLE 7.1 r - PARAMETER
An r-parameter equivalent circuit for a bipolar junction transistor is shown in Figure
7.2(a). For most general analysis work, it can be simplified as follows: The effect of
the ac base resistance (r) is usually small enough to neglect, so it can be replaced by a
short. The ac collector resistance (r;) is usually several hundred kilohms and can be
replaced by an open. The resulting simplified r-parameter equivalent circuit is shown
in Figure 7.2(b)_ The interpretation of this equivalent circuit in terms of a transistor's
ac operation is as follows: A resistance (r;) appears between the emitter and base
terminals. This is the resistance "seen" looking into the emitter of a forward-biased
transistor. The collector effectively acts as a current source of αacIC, or, equivalently, '
βacIbThese factors are shown with a transistor symbol in Figure 7.3.
2
2. BIASING,AC EQUIVALENT CIRCUIT AND GAIN OF Week 7
STAGES
FIGURE 7.2 r PARAMETER OF EQUIVALENT CIRCUIT
FIGURE 7.3 RELATION OF TRANSISTOR SYMBOL TO r PAREMETER
Figure 7.4 shows a common-emitter amplifier with voltage-divider bias and coupling
capacitors, C1 and C 3 , on the input and output and a bypass capacitor, C2 , from
emitter to ground. The circuit has a combination of dc and ac operation, both of which
must be considered. The input signal, Vin , is capacitively coupled into the base, and
the output signal, Vout is capacitively coupled from the collector. The amplified output
is 1800 out of phase with the input.
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2. BIASING,AC EQUIVALENT CIRCUIT AND GAIN OF Week 7
STAGES
FIGURE 7.4 COMMON EMITTER CONFIGURATION
An emitter-follower circuit with voltage-divider bias is shown in Figure 2-10. Notice
that the input signal is capacitively coupled to the base, the output signal is
capacitively coupled from the emitter, and the collector is at ac ground. There is no
phase inversion, and the output is approximately the same amplitude as the input.
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2. BIASING,AC EQUIVALENT CIRCUIT AND GAIN OF Week 7
STAGES
FIGURE 7.5 COMMON – COLLECTOR CONFIGURATION
A typical common-base amplifier is shown in Figure 7.6. The base is the common
terminal and is at ac ground because of capacitor C 2 ' The input signal is capacitively
coupled to the emitter. The output is capacitively coupled from the collector to a load
resistor.
FIGURE 7.6 COMMOM BASE CONFIGURATION WITH VOLTAGE DIVIDER
BIAS
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BIASING,AC EQUIVALENT CIRCUIT AND
GAINOF STAGES
WEEK 8
2.3 COMMON EMITTER CONFIGURATION
2.3.1 Voltage Gain
The ac voltage gain expression for the common-emitter amplifier is developed
using the equivalent circuit in Figure 8.1 The gain is the ratio of ac output voltage
at the collector (Vc) to ac input voltage at the base (Vb)'
8.1EQUIVALENT CIRCUIT FOR OBTAINING VOLTAGE GAIN
BIASING,AC EQUIVALENT CIRCUIT AND
GAINOF STAGES
WEEK 8
Equation Above is the voltage gain from base to collector. To get the overall gain
of the amplifier from the source voltage to collector, the attenuation of the input
circuit must be included. Attenuation means that the signa voltage is reduced as it
passes through a circuit.
The attenuation from source to hase multiplied by the gain from base to collector
is the overall amplifier gain. Suppose the source produces 10m V and the source
resistance and input resistance is such that the base voltage is 5 m V. The
attenuation is therefore 5 mV/10 mV = 0.5. Now assume the amplifier has a
voltage gain from base to collector of 20. The output voltage is 5 m V x 20 = 100 m
V. Therefore, the overall gain is 100 m V /10 m V = 10 and is equal to the
attenuation times the gain (0.5 x 20 = 10).
2.3.2Current Gain
The current gain from base to collector is Ie/lb or βac However. the overall current
gain of the common-emitter amplifier is
BIASING,AC EQUIVALENT CIRCUIT AND
GAINOF STAGES
WEEK 8
2.3.3 Power Gain
The overall power gain is the product of the overall voltage gain (Av) and the
overall current gain (Ai).
BIASING,AC EQUIVALENT CIRCUIT AND
GAINOF STAGES
WEEK 9
2.4 COMMON COLLECTOR CONFIGURATION
2.4.1 Voltage Gain
As in all amplifiers. the voltage gain is Av = Vout/Vin The capacitive reactances are
assumed to be negligible at the frequency of operation. For the emitter-follower,
as shown in the ac equivalent model.
Since the output voltage is at the emitter, it is in phase with the base voltage, so
there is no inversion from input to output. Because there is no inversion and
because the voltage gain is approximately 1, the output voltage closely follows
the input voltage in both phase and amplitude; thus the term emitter-follower.
2.4.2 Current Gain
The overall current gain for the emitter-follower is Ie/Iin ,You can calculate Iin as
Vin/Rin(tot). If the resistance of the parallel combination of the voltage-divider bias
resistors RI and R2 is much greater than Rin(base). then most of the input current
BIASING,AC EQUIVALENT CIRCUIT AND
GAINOF STAGES
WEEK 9
goes into the base; thus. the current gain of the amplifier approaches the current
gain of the transistor, βacwhich is equal to Ic/Ib This is because very little signal
current is diverted to the bias resistors. Stated concisely. If
2.4.3 Power Gain
The common-collector power gain is the product of the voltage gain and the
current gain. For the emitter-follower. the overall power gain is approximately
equal to the current gain because the voltage gain is approximately 1.
Ap= AvAi
Since Av = 1 the overall power gain is
Ap=Ai
BIASING,AC EQUIVALENT CIRCUIT AND
GAINOF STAGES
WEEK
10
2.5 COMMON BASE CONFIGURATION
2.5.2 Current Gain
The current gain is the output current divided by the input current. ICis the ac
output current, and Ie is the ac input current. Since IC =Ie, the current gain is
approximately I. Ai= I
2.5.3 Power Gain
BIASING,AC EQUIVALENT CIRCUIT AND
GAINOF STAGES
WEEK
10
Since the current gain is approximately 1 for the common-base amplifier and Ap =
AvAi' ,the power gain is approximately equal to the voltage gain.
Ap=:Av.
TRANSFORMER COUPLING,POWER AND MULTISTAGE OF
AMPLIFIERS
WEEK
11
3.1 INTRODUCTION
Power amplifiers are large-signal amplifiers. This generally means that a much larger portion of
the load line is used during signal operation than in a small-signal amplifier. In this section, we will cover
two classes of power amplifiers: class A, and class B, These amplifier classifications are based on the
percentage of the input cycle for which the amplifier operates in its linear region. Each
class has a unique circuit configuration because of the way it must be operated. The emphasis is on
power amplification. Power amplifiers are normally used as the final stage of a communications receiver
or transmitter to provide signal power to speakers or to a transmitting antenna.
3.1.1 TRANSFORMER COUPLING
Transformer coupling is illustrated in Figure 11.1 The input transformer has a center-tapped secondary
that is connected to ground, producing phase inversion of one side with respect to the other. The input
transformer thus converts the input signal to two out-of-phase signals for the transistors. Notice that
both transistors are npn types. Because of the signal inversion, Q1 will conduct on the positive part of
the cycle and Q2 will conduct on the negative part. The output transformer combines the signals by
permiting current in both directions, even though one transistor is always cut off. The positive power
supply signal is connected to the center tap of the output transformer.
11.1 Transformer coupled push-pull amplifiers
TRANSFORMER COUPLING,POWER AND MULTISTAGE OF
AMPLIFIERS
WEEK
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3.1.2 Complementary Symmetry Transistors
Figure 11.1 shows one of the most popular types of push-pull class B amplifiers using two emitterfollowers and both positive and negative power supplies. This is a complementary amplifier because one
emitter-follower uses an npn transistor and the other a pnp, which conduct on opposite alternations of
the input cycle. Notice that there is no dc base bias voltage (VB = 0). Thus, only the signal voltage drives
the transistors into conduction. Transistor Q1, conducts during the positive half of the input cycle. and Q2
conducts during the negative half.
3.1.3 Crossover Distortion
When the dc base voltage is zero, both transistors are off and the input signal voltage must
exceed VBE before a transistor conducts. Because of this, there is a time interval between the positive and
negative alternations of the input when neither transistor is conducting, as shown in Figure 3-3 The
resulting distortion in the output waveform is called crossover distortion.
FIGURE 11.2 CLASS B PUSH PULL AC OPERATION
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FIGURE 11.3 CROSSOVER DISTORSION IN CLASS B PUSH PULL AMPLIFIER
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PRINCIPLE AND METHOD OF INTER STAGE COUPLING IN
MULTISTAGE AMPLIFIERS
3.2 INTRODUCTION
The three various of the signal stage transistor amplifier, namely the
common emitter, common – safe and common collector have seen
analyzed and discussed in previous chapter. How ever, a signal stages by
insect may not provide enough gain or the input and output resistances
may be unsuitable for a particular application. In these situations, the
required performance can be obtained by coupling two or more single –
stages together to form a multistage amplifiers .
The most important of any method of coupling stages together is
that it most not interfere with the d.c operating points set for each stages.
This applies, of course not only to bipolar transistors but also to all active
devices,
3.2.1 RESISTANCE – CAPACITANCE COUPLING (RC)
The RC coupling method simple means the connection of a capacitor at the
input of am amplifier. The connection of the capacitor is series with the
input impedance of the amplifier give use to how frequenting response
while that of the parallel connection given rise to high frequency response
of the amplifier.
3.2.2 FREQUENCY RESPONSE AND BANDWIDTH.
The term frequency response refers to the gain of an amplifier over a band
or range of frequencies. A plot of gain verses frequency is commonly called
a frequency – response curve.
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Gain (voltage current)
Frequency
F1
F0
F2
Figure 12.1 Frequency response curve
Fig 12.1 above shows a frequency – response curve for an audio frequency
amplifies. Note that the gain appears reasonable flat or level over much of
the cover but falls off at how and high frequency.
There are three important point (frequencies) on he response curve .
i.
ii.
iii.
iv.
Mid frequencies point (Fo) :- this is the point where the gain is
maximum. In audio either 400 or 1000 HZ are commonly used in
proactive as to, the mild – frequencies point to which the nest of the
response work is referenced.
The low frequency half power point (F1):- this is the low – frequency
point at which the output power falls to one – half its valve at the
mid frequency point. It is further identified as the point at which the
output voltage (and current) falls to 70.7% of it’s mid frequency
value. Hart – power point and -3db point are used interchange easly.
The hight frequency half – power point:- this is the high frequency
point at which the output falls to one –half its mid frequency value.
As at the low frequency that –power point voltage and current are
70.7% of this mid frequency values.
Bandwidth:- this is the difference in frequency between the halfpower points. That is
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Bw = F2 – F1
Where
F1 = the frequency that power point
F2 = the high – frequency half power- point
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3.3 AMPLIFIERS & SMALL SIGNAL ANALYSIS
The great majority of amplifiers, whether transistor or vacuum tube type, may be
considered as three-terminal devices from the signal standpoint, this is true even though other
terminals often exist, to bring to the device special voltage that aid or improve the basic
amplification function.
Another basic fact about electronic systems; the vast majority of electronic systems consist
functionally of an input transducer, a signal processor, and an output transducer. A transducer is
a device that changes energy from one form to another. An input transducer in an electronics
system changes energy (sound, motion, temperatures, etc.) into on electrical signal. Some
examples are microphone, a phonograph pickup and a thermocouple). The signal processor
amplifies or modifies the signal in some desired way.
Finally, the output transducer (load) changes the electrical energy coming from the signal
processor into what ever form serves the purpose of the equipment.
Let us illustrate and clarify the concept of gain through the following example:
Example 1.0
If signal source from a microphone that produces an output of 50mv and 20µA (ac. Effective
value). The output of the amp to the speaker is 3V and 300mA. Find (a) the voltage gain (b) the
current gain (c) the power gain
Solution
(a) voltage gain
= Vout = 30
Vin
(b) current gain
(c) power gain
=
= 60
50 x 10-3
50mV
= Iout = 300mA
3
= 300x10-3
Iin
20µA
= Pout =
Vout . Iout
Pin
Vin . Iin
20 x 10-6
= 3 x 300 x 10-3
50 x 10-3x 20 x 10-6
= 15, 000
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= 0.9
1 x 10-6
= 9 x 105
Another approach
For power gain = voltage gain x current gain
= 60 x 15000 = 9 x 105
In almost all acts in order to obtain amplification a d.c voltage of appropriate level must first be
brought (from one or more power source) to the transistor or vacuum tube terminals i.e. proper
d.c static conditions must be established as a prerequisite to designed signal amplification.
Subsequently, variations are created in the applied dc level by the input transudes; these variation
late introduce fluctuations in the previously established state d.c conditions and are called
rippling on top of the d.c component a resort source what reminiscent of the ripple voltage in the
d.c output of a filtered power supply. It is this as signal component that is usually of primary
importance and that we will amplify to higher power levels.
3.3.1 BETA (B) AND ALPHA ()
In all the three basic transistor circuit configuration; common – base, common – emitter
and Common –collector (as already discussed above emitter current (IE) divides in the transistor
with part flowing through the base (IB) and part flowing through the collection (IC). Thos, JE is
always equal to the sum of IB and IC ie.
IE = IB + IC
This relationship is fundamental and a very important one to mention because it is true for
solution D.C static conditions and for are , signal conditions. In typical transistors, IC is 20=200
times larger than IB. ie. Approximately 95-99.5% of IE goes to the collection and only 0.5 – 5%
of IE goes to IB.
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Another most important characteristic of every transistor is the ratio of IC to IB. this ratio is
called beta (), and it should be thoroughly understood by every one working with electrums.
Since values of d,c and a.c currents differ in both base and collector, we find there are two value
of beta for every transistor. To hind the d.c value of beta, we use static conditions and fixed
points,
B d.c. = IC/IB
Where IC is the d.c collector current at fixed point and
IB is the corresponding d.c base current.
Another important characteristic, alpha () is the ratio of collector current to emitted current
since IE = IC + IB, it is clean that IC will always be less than IE as long as any IB exists. We
recall that IC is typically 20 – 2% limits large than IB. the d.c value of alpha is defined as
d.c = IC/IE = IC
IC + IB
Thus, the value of alpha () is very near (d.t always less than) unity, or 1 for example. If IB of
40NA produce IC of 4mA,
d.c = Ic
=
IC + IB
40 x 10-3
4 x 10-3 x 40 x 10-6
 0.99
And  d.c = IC/IB = 4 x 10-3
40 x 10-3 = 100
Also under action operating or signal concditions, we have veriational or are value for  and.
These values do not usually have precisely the same values as for direct correction because now
we are dealing with a range of values rather than fixed points. A.C valve of  and  are written
without subscript. Ie
 = ΔIC/ΔIB
Or
 = ic /ib
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Where DIC is he small change in d.c collection current from one value to another, and DIB is the
small change in d.c base comment that lased DIC.
Ic is the collector current and
Ib is the base current that produce it (ic)
We also define are alpha as
 = ΔIC /ΔIB
As before  1 but always less than one ( < 1) there is a numerical relationship between  and
 that is often useful,
=

and  = 
1-
1 +
Example II
In an operating transistor cct, a change of 16µA in IB causes a change of 1.6mA in IC. Find 
and.
Solution
 = DIC/DIB = 1.6 x 10-3
= 100
1.6 x 10-6
 IC
- =
IE
Ie
Ie + IB  =  - 100
= 0.99
1 +  7 + 100
Example III
Specification of a transistor called for minimum  = 20, maximum  = 60. Calculate minimum
and maximum values of.
Solution
min = 
=
20
= 0.952
TRANSFORMER COUPLING,POWER AND MULTISTAGE OF
AMPLIFIERS
1 +  1 + 20
max = 
= 60
1+
= 0.984
1 + 60
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3.4 MULTISTAGE AMPLIFIERS
Two or more amplifiers can be connected in a cascaded arrangement with the output of
one amplifier driving the input of the next. Each amplifier in a cascaded arrangement
is known as a stage. The basic purpose of a multistage arrangement is to increase the
overall voltage gain. Although discrete multistage amplifiers are not as common as
they once were, a familiarization with this area provides insight into how some circuits
affect each other when they are connected together.
3.4.1Multistage Voltage Gain
The overall voltage gain, A;.. of cascaded amplifiers, as shown in Figure 14.1, is the product of the individual voltage gains.
A = AVIAv2AV3 .. - AVN
where n is the number of stages.
FIGURE 14.1 CASCADED AMPLIFIERS
3.4.2 Voltage Gain Expressed in Decibels
Amplifier voltage gain is often expressed in decibels (dB) as follows:
AV(dB) = 20 log AV
This is particularly useful in multistage systems because the overall voltage gain in dB is the
Sum of the individual voltage gains in dB.
Av'(dB) = AV1(dB) + A v2 (dB) + ... + AVN(dB)
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A certain cascaded amplifier arrangement has the following voltage gains: Av 1= 10, AV2 = 15,
andAV3, = 20. What is the overall voltage gain? Also express each gain in decibels (dB) and
determine the total voltage gain in dB.
AV = AV1Av2,AV3 = (10)(15)(20) = 3000
AV1(dB) = 20 log 10 = 20.0 dB
AV2(dB) = 20 log 15 = 23.5 dB
AV3(dB) = 20 log 20 = 26.0 dB
AV'(dB) = 20.0 dB + 23.5 dB + 26.0 dB = 69.5 dB
For purposes of illustration, we will use the two-stage capacitively coupled amplifier in
Figure 14.2 Notice that both stages are identical common-emitter amplifiers with the output of the first stage capacitively coupled to the input of the second stage. Capacitive coupling prevents the de bias of one stage from affecting that of the other but allows the ac
signal to pass without attenuation because Xc ≈ 0Ω at the frequency of operation. Notice,
also, that the transistors are labeled Q1, and Q2'
FIGURE 14.2 TWO STAGE AMPLIFIER
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3.4.3 Loading Effects
In determining the voltage gain of the first stage, you must consider the
loading effect of the second stage. Because the coupling capacitor C) effectively appears as
a short at the signal frequency, the total input resistance of the second stage presents an ac
load to the first stage.
Looking from the collector of Q1 the two biasing resistors in the second stage, R5and
R6 appear in parallel with the input resistance at the base of Q2' In other words, the signal
at the collector of Q. seesR3 R5, R6, and Rinbase of the second stage all in parallel to ac
ground. Thus. the effective ac collector resistance of Q1 is the total of all these resistances
in parallel.
COMPLEX AMPLIFIER CIRCUIT
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3.5 INTRODUCTION
Power amplifiers are large-signal amplifiers. This generally means that a much larger portion
of the load line is used during signal operation than in a small-signal amplifier. In this section, we
will cover two classes of power amplifiers: class A, and class B, These amplifier classifications are
based on the percentage of the input cycle for which the amplifier operates in its linear region. Each
class has a unique circuit configuration because of the way it must be operated. The emphasis is on
power amplification. Power amplifiers are normally used as the final stage of a communications
receiver or transmitter to provide signal power to speakers or to a transmitting antenna.
FIGURE 12.1 COMPLEX AMPLIFIER CIRCUIT
1
COMPLEX AMPLIFIER CIRCUIT
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