Introducing HardwareBased Intelligence and
Reconfigurability on
Industrial IoT
Edge Nodes
Apostolos P. Fournaris, Christos Alexakos,
Christos Anagnostopoulos, Christos Koulamas,
and Athanasios Kalogeras
ATHENA Research and Innovation Center
draining a node from battery,
memory, or p
­rocessing power.
Editor’s note:
Operations related to statistical
Industrial automation is an important application area for the
manipulation of collected senInternet-of-Things (IoT) technologies. In this article, Fournaris et al.
discuss IoT system architectures for computing at the edge of the
sor data on the time domain
Internet and the use of FPGAs as edge devices.
(like Pearson’s Convolution, Kur—Marilyn Wolf, Georgia Institute of Technology
tosis) as well as industrial process anomalies and embedded
 The need for advanced intelligence in the machine-learning algorithms may introduce a very
industrial environment may lead to moving intelli- high toll on an edge node’s expected behavior (e.g.,
gence from the cloud down to the local network level long life cycle, fast responsiveness, etc.). Also, addior directly into embedded devices. Thus, fog or edge tional edge node features, like security strengthencomputing emerges as a serious research challenge ing, introduce additional performance and hardware
on edge nodes. This highlights the need for nodes that resource overhead that cannot always be handled by
are capable of handling complex functions beyond the IIoT edge device without compromises in other
simple sensing and actuation loops. Functionality device nonfunctional requirements.
for local and embedded processing of collected
In this article, we present a system architecture
data to extract possible industrial decisions with- that can handle the overall manufacturing chain of
out the need for cloud communication is becoming an Industry 4.0 plant and divide it into different laya reality in current and future edge-based Industrial ers, focusing on the level of intelligence that each
Internet-of-Things (IIoT) deployments. However, this layer can handle. For this system, we propose a
high edge node intelligence may have a considera- mechanism that can efficiently migrate IIoT comble footprint on a device’s hardware resources, thus putational functionality and edge intelligence to
the system end node devices. Since such devices
Digital Object Identifier 10.1109/MDAT.2019.2908547
do not always have the resources to support comDate of publication: 1 April 2019; date of current version:
plex operations, we propose the executions of
these operations through hardware means inside
22 July 2019.
July/August 2019
Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC
2168-2356/19©2019 IEEE
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SI: Circuits and Systems for VLSI Internet-of-Things Devices
the node SoC. To bypass the lack of flexibility that
ASICs have, we propose the use of FPGA technology
on the end-node device. Recent advancements in
FPGA technology enable us to use SoC core designs
that merge powerful Advanced RISC Machine
(ARM)-embedded processors with FPGA fabric. As
an example of our proposed approach, we introduce a prototype concept of an edge node for our
system that has hardware support for a statistical feature extraction mechanism and for detecting outlier
behavior through novelty vector extraction using the
extracted features and a training set of known good
values. The nearest neighbor machine-learning
algorithm is used for novelty extraction. Using this
concept, we can support condition monitoring operations for industrial assets on the edge level. This
approach was prototyped on an actual embedded
system setting (Smartfusion2 SoC board combined
with the CC2538-based Openmote board for wireless communication) and the two procedures (i.e.,
feature and novelty extraction) were realized in pure
software and the proposed hardware or software
codesigned way (using the Smartfusion2 SoC FPGA
fabric). The experimental results confirmed that the
proposed approach had considerable savings in
consumed energy and led to very small time delays
compared to traditional purely software solutions.
Related works
During the past years, the dominance of cloud
computing was mainly driven by two main factors
[1]. First, the exploitation of centralized resources
guaranteed the reduction of administrative and
operative costs. Second, companies preferred to
consume services provided by large providers via
the Internet than invest in acquiring a data center
due to additional cost. However, the advent of the
Internet of Things (IoT), with the continuous deployment of smart networking devices that generate large
volumes of data, in conjunction with the physical
separation of cloud services and end devices has, in
many cases, increased the average network latency
and jitter to unacceptable levels [2]. As a result, a
new trend emerged that dictates the migration of
cloud functionalities toward the network edges and
the company premises [3]. Many attempts in the
literature propose architectures that implement
the aforementioned paradigm and introduce new
terms like mobile cloud computing (MCC), cloudlet [4] fog computing, edge computing [5], which
16
is now called multiaccess edge computing, and mist
computing [6]. All of these share their common
effort to bring the computational resources nearer to
the end user and differ in the targeted use cases. It
must be noted that the edge computing acts complementary to the cloud and not competitively. Living
in the dawn of a new cyber world, we realize that
proximity matters, and its importance can be summarized into four reasons [1]: highly responsively
services due to low latency and jitter, scalability via
edge analytics, improved security and privacy, and
enforcement of cloud redundancy policies.
Industry 4.0 and the Industrial Internet Consortium (IIC)i reference architectures strongly support
the inclusion of smart edge devices in an IIoT infrastructure. This means that edge devices should be
able to handle intelligent functions beyond sensing
and actuating. Also, edge devices must be able to
collect data from multiple sensors in a real-time
fashion. As indicated in [7] and [8], using an edge
node micro control unit (MCU) for multiple sensor
data acquisitions (acting as a multisensor core controller) may be a difficult task since MCUs are not
focused on offering parallelism. Fully migrating all
node functionality on FPGA technology (with no
MCUs) tended to be problematic, since FPGAs do
not have analog-to-digital and digital-to-analog converters (ADC and DAC) or floating point units. For
this reason, the use of FPGA or complex programmable logic device (CPLD) in combination with MCUs
(in the form of SoCs) has been proposed in order to
migrate parallel processing for multisensory control
to dedicated hardware components in the FPGA or
CPLD fabric [7], [8]. This concept was expanded in
[9], where a solid FPGA SoC-based solution is proposed. In that work, the main functionality of the
embedded edge node is left to an ARM processor
inside the FPGA SoC, while the device communication (using IEEE 802.15.4) is handled by a dedicated
IP core inside the SoC’s FPGA fabric. Although the
design in [9] is interesting, several aspects of the overall concept were not actually implemented, while
the edge node intelligence is constrained on efficient
communication management and realization. Similarly, in [7], the node intelligence is only focused on
optimizing, through FPGA hardware components,
the parallelism of a multiple sensor data acquisition
core controller. Our view is that FPGA technology
i
https://www.iiconsortium.org/
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can be used to considerably increase the edge node
intelligence, beyond the previously presented works.
Overall architecture supporting edge
detection
The aim of the proposed approach is the introduction of hardware-assisted, yet reconfigurable, intelligence in integrated system IIoT edge nodes that will
implement the Industry 4.0 aspects in a manufacturing environment. Such a system provides an overall
solution for IIoT in manufacturing, by addressing the
challenges at the various level of the automation pyramid. It supports an infrastructure for collecting data
from the IIoT sensors while it permits the processing
of this data using different algorithms with different
complexity in different layers. The proposed overall
system architecture is based on the IIoT Volume G1:
Reference Architecture (IIRA) introduced by IIC in
2017 while defining the structural components of a
system that follows the principles of Industry 4.0. IIRA
separates the applications and systems into three
tiers. First is the edge tier that collects data from the
edge nodes and comprises IIoT sensors or ­actuators
as well as controllers (end nodes) of the manufacturing devices at the plant level. Second is the platform
tier whose applications are responsible to preprocess, transform, and analyze the data from the edge
tier in order to forward specific information to the
next tier or to reference behaviors and events on
the manufacturing execution environment. Furthermore, these tier systems can execute commands to
actuators or control devices for making changes in
the production chain. Third is the enterprise tier that
implements domain-specific applications and enterprise decision support systems that issue control
commands to the platform tier and edge tier. With
reference to the IIRA architecture, the proposed
overall system architecture consists of various functional components distributed in the three tiers, as
depicted in Figure 1.
In our approach, the edge tier consists of IIoT
sensors or actuators, either simple or smart, and controllers like programmable logic controllers (PLCs)
for the operation of the actual industrial devices or
machines in the plant. This tier hosts the proposed
smart edge IIoT nodes, which can both collect data
Figure 1. Overall architecture.
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SI: Circuits and Systems for VLSI Internet-of-Things Devices
and process it for timely event detection using hardware-assisted decision-making algorithm implementations. With the proposed edge nodes, we can
execute at the end node level, fast calculations of
statistical and machine-learning models on the collected raw data, inferencing accurately for the detection of an anomaly. Also, the nodes can execute predefined commands realizing the system response on
the detected event. The response can include either
automatic actions, such as a device shut down, where
the interconnection with the device controllers is
used, or signals through human interaction devices
that inform the human employees about how to react
in the case of a detected event or just passing the
event to the platform tier in order to process it and
react in a wider segment of production process.
Apart from the intelligence that the edge tier has
obtained, its nodes can preprocess data and send
only specific and valuable information to the other
two tiers, minimizing the size of the transmitted
data, and eventually the time of the transmission. For
example, instead of a raw time series data segment
that has been sampled with some kilohertz sampling
frequency, the edge node is able to do calculations
and send values, such as mean and peak values,
statistical moments, spectral components, etc., and
far more intelligent information like malfunctioning
events and machine anomalies. Furthermore, the
edge tier could consist of classical IIoT sensors that
monitor various variables and send values to the
systems of the platform tier. Also, human interaction
devices, such as buttons, that are used in case of
alarm can propagate an event at this layer. In some
cases, wherever IIoT sensors are not possible to interconnect immediately with the edge IIoT platform,
due to the incompatibility of communication or data
exchange protocols, gateways are used. These gateways are responsible for establishing the connection
between sensors and systems at the next layer.
The platform tier contains two main systems:
1) the IIoT platform and 2) the manufacturing control mediator (MCM). The IIoT platform collects data
from different sensors, processes them, and infers
event detection and diagnosis. The difference here
from the edge tier is that the event detection utilizes
the combined processing of data from different
edge nodes. The IIoT platform is hosted in servers,
physical or virtual, installed in the factory premises
or on the cloud. In any case, IIoT platforms have
more available computational power than the edge
18
nodes, permitting the execution of more complex
algorithms for event detection and diagnosis that
make use of more data.
The MCM is a centralized integrated system interoperating with both the IIoT infrastructure systems
and industrial systems in the plant. The main responsibility of this system is the execution of a command
that consists of a flow of actions that must be executed in the production chain when an event is
detected. In each case, the MCM must orchestrate
the necessary changes in the process workflow of
the production systems in order to make applicable
required event-related changes in the production.
Alexakos et al. [10] used a multiagent system decentralizing manufacturing execution system to play the
role of MCM. The Visetak multiagent system (MAS),
as the system is called, is based on the logic that each
order coming from the enterprise resource system
(ERP) layer is processed by an order agent which, by
communicating with other agents, binds the appropriate factory resources (production devices and
machines) that are controlled by their own resource
agent. The scope is that, when a change is made in
the plant, i.e., a machine stops, or its configuration
changes, the MAS will reschedule the production
chain with alternative flows and factory resources
that are available. As agents define a distributed system architecture and do not require any predefined
information about other agents, such an approach
introduces fault tolerance features [11].
The enterprise tier hosts the classical enterprise
information systems (ERP, CRM, etc.) in combination with modern systems for data analytics, mainly
for big data that are finally collected by the IIoT
and industrial systems infrastructure. The role of
enterprise tier systems is to provide tools to the business analysts for analyzing data received from the
factory, in order for the latter to infer abnormalities
that affect the whole pro­duction line. This inference will lead to the changes in decision making at
the enterprise level but will also define or update
rules that are used for decision making in the other
two tiers. Apart from the manual definition of rules
for decision making, as already mentioned, the
other two tiers (i.e., the edge nodes and IIoT platform) can provide resources for the execution of
complex decision making or prediction algorithms.
Thus, at this layer, using machine-learning or statistical methods on big data, new predictive models
can be generated that can be forwarded to IIoT
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platforms or the smart edge nodes to be used for
data processing and inference.
Hardware-based reconfigurable smart
edge node for IIoT
Focusing on the edge tier of Figure 1 system architecture, this article proposes an edge node architecture that utilizes hardware-based intelligence.
Thus, an edge node can evaluate its data locally and
provide appropriate responses without the need to
always transmit data to the IIoT cloud, creating local
intelligence loops without cloud or fog intervention.
In several cases, where computer intensive or memory demanding intelligent operations are performed
at the edge level, it would be impossible to retain high
responsiveness when relying solely on software implementations. The same reason prohibits the inclusion
of advanced features in the IIoT end nodes, such as
strong security and privacy services. Hardware-assisted edge nodes, as proposed, can become a viable
solution to the previously mentioned issues since
commercial SoCs that include an MCU along with an
FPGA fabric have been launched in the market.
The edge node proposed architecture is structured
around a synchronous SoC solution that includes
an MCU processor and an FPGA fabric. The MCU
has an advanced microcontroller bus architecture
(AMBA) bus (APB, AHB, or AXI) that can communicate with all MCU peripherals [RAM–ROM memory,
I/O interfaces (CAN, I2C, SPI)], which can also be
used for the interconnection of dedicated IP Core
peripherals, implemented in the FPGA fabric for specific tasks, thus boosting the edge node intelligence.
We assume that the main software functionality, like
operating systems (OSs) and communication, is handled by the edge node MCU. However, the edge node
software stack includes specific drivers that can be
used by an IIoT developer to utilize the FPGA fabric
dedicated peripherals. In terms of hardware, each
peripheral must be able to communicate with the interconnection bus, thus it includes a bus slave interface.
The internal hardware structure of the FPGA peripherals is related to the peripheral’s actual f­unctionality.
Determining what kind of peripherals need
to be implemented in FPGA technology instead of
software is highly relevant to the actual tasks that
the edge node needs to perform. Analyzing the functional and nonfunctional requirements of the edge
node behavior and extracting needed, achievable,
performance indicators is the first step that we follow
to match the previous goal. Components and functions needed for handling the edge node intelligence
are described and modeled in software and are evaluated against the performance indicators. Those
components that cannot match the indicators need
to be hardware accelerated are described in hardware description language (HDL) and are implemented as IP cores in the FPGA fabric of the SoC.
Through its SoC FPGA fabric, apart from hardware
performance, the node gains the ability to reconfigure its hardware functionality over time according
to the IIoT infrastructure needs. Thus, IIoT designers
can update the edge tier functionality at the end node
hardware level without changing the actual nodes
themselves. The overall process of deploying both
hardware and software on an edge node, along with
the overall architecture of the node itself, is described
in Figure 2. Initially, the desired edge tier functionality
Figure 2. Design and deployment of reconfigurable hardware-assisted edge node
intelligence on FPGA SoC-based architectures.
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SI: Circuits and Systems for VLSI Internet-of-Things Devices
that we want to deploy is defined in the enterprise tier.
At this level, the hardware accelerated intelligence
that needs to be deployed is decided. Then, the IIoT
designer uses an edge node device architecture model
and its connection with deployed sensors or actuators
to describe the needed intelligence. The description
is a mixture of block design, software code, and HDL
development, which is determined by the SoC vendor
toolset. The needed functionality described modeling
is then simulated using SoC provider toolset, following SoC FPGA design and verification approaches,
to validate the description compliance with the functional and nonfunctional edge node requirements.
Successful verification leads to the actual hardware
and software code implementation for edge node
deployment. This set consists of application updates,
new software drivers for the deployed hardware
peripheral in the edge node FPGA fabric as well as
the actual FPGA configuration file. This information
is transmitted to the platform tier in the IIoT Platform
that forward it to the appropriate edge tier device.
When the deployment set reaches the edge node, it
is installed to the SoC fabric. The actual installation is
highly dependent on the SoC manufacturer provided
technology. Currently, each SoC FPGA manufacturer
provides his/her toolset for the installation procedure
and supports different installation mechanisms that
may need manual user intervention.
Adaptive manufacturing and condition-based
maintenance use case
To further refine and describe the proposed
generic methodology, using the proposed system
architecture in the previous section, we focus on the
design of a smart edge node capable of detecting
malfunctions of an associated industrial asset (i.e., a
production machine), offering basic condition monitoring services for preventive and predictive maintenance operational scenarios. Typically, an IIoT edge
node sensor mechanism is installed on the industrial
machine to collect data and transmit them to a fog
gateway or the cloud for processing. Then, a cloud
service will determine, from the collected data, some
training data set (known good values), the health status of the machine, and detect or predict possible malfunction events. End node data are collected sparsely
within a day (once per day) and can be used only for
predicting long-term machine malfunctions, since, at
this data acquisition rate, no short-term conclusions
can be made. Part of the previously described func-
20
tionality can be transferred to the edge node if this
node is capable of executing statistical analysis or
machine-learning algorithms, thus extracting novelty
features locally and evaluating them. This approach,
showcased in [12], suffers from several implementation issues when software is used for event detection.
RAM must be reserved on the edge node for collecting a considerable amount of data. Feature extraction
and event detection execution have a significant execution latency while the detection window is small
due to the reduced size of available memory for
collecting sensor data. The overall software computation process remains power consumption-hungry,
and thus, can only be executed a few times a week
in order not to drain the edge node battery (in battery-powered systems). Therefore, the condition monitoring time-step can only support long-term maintenance prediction windows and cannot be exploited
for other relevant and safety-related scenarios, such
as to trigger a device response to remedy in real time
other acute machine problems.
In light of these issues, in this article, we apply the
proposed architecture approach and transfer some
of the edge node smart functionality from software
to hardware. More specifically, we implement a dedicated hardware peripheral for extracting features
from collected sensory data and extract novelty
or outlier behavior using stored well-known good
values (training set). These hardware components
implement the same method utilized in [12], which
processes the collected data in the time domain.
Furthermore, an additional hardware component is
used for data integrity code generation and validation using the hash-based message authentication
code (HMAC) algorithm.
As a prototype design of the mentioned class
of edge nodes, we are using a two-processor board
system structure, separating the application from
the com­munication processor, coupled with several
exchangeable sensor interface boards. The sampling,
signal processing, and detection components are
executed in an AVNET SmartFusion 2 kickstart development kit board featuring the Microsemi Smartfusion 2 SoC consisting of an ARM Cortex M3 processor and an FPGA fabric. The IoT networking stack,
namely, the IEEE-802.15.4 wireless interface and the
Internet Protocol version 6 (IPv6), Routing Protocol
for Low-Power and Lossy Networks (RPL), and Constrained Application Protocol (CoAP) components,
are implemented on a Contiki OS-based CC2538
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Figure 3. The embedded edge node prototype architecture.
Openmote board that is connected through an Xbee
shield to the AVNET system and communicates over
using universal asynchronous receiver–transmitter
(UART) (Figure 3).
Using the dedicated peripherals on the FPGA
fabric shown in Figure 3 architecture, we can collect sensor data on the dedicated storage area of
the FPGA and feed them directly to the feature
extraction (FE) unit that calculates seven different Features for windows of 1024 samples. The
FE peripheral employs a direct memory access
(DMA)-like mechanism for sample collection (16bit sample storage on dedicated FIFO memory) and
using a software-based triggering, processes samples
to extract rms, kurtosis, skewness, peak, crest factor,
shape factor, and impulse factor features. The FPGA
fabric also has a novelty extraction (NE) peripheral
using a stored training dataset, and the extracted feature values are calculated using the nearest neighbor
machine-learning algorithm (implementing matrix
multiplication), outlier, and abnormal behavior for a
sampled industrial device [12].
Figure’s 3 edge node functionality was prototyped using VHDL code (FPGA fabric) and
C code software (ARM core) on the Smartfusion2 SoC. In Table 1, experimental results of the
above-mentioned implementations are provided
and comparisons are made when using only software (SW) and software–hardware (SW/HW)
codesign for the FE window and NE window procedure. The ARM Cortex M3 datasheet specifies a
power consumption of 31 μW/MHz, which results
in 4.96-mW power consumption at ARM’s 160-MHz
chip. The FPGA fabric without the FE/NE peripheral (pure SW) consumes 121.681 mW. The FE/NE
peripheral inclusion adds 32.292 mW to Fabric’s
power consumption. In Table 1, we can observe
that the time delay for FE and NE on HW/SW solu-
Table 1. Experimental results.
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SI: Circuits and Systems for VLSI Internet-of-Things Devices
tion is considerably decreased compared to pure
SW solution. Also, energy consumption is considerably reduced using HW acceleration. The NE HW
implementation has excessively low values due
to the utilization of FPGA fabric’s dedicated multiplier units, which reduce time delay and energy
consumption. Smartfusion 2 SoC has a dedicated
hardware HMAC peripheral that we can use with
no additional cost on HW resources and thus does
not appear in Table 1.
By using dedicated FPGA peripherals and considering the low power consumption specifications of
the SmartFusion 2 SoC, we can achieve considerable
energy consumption reduction compared to a pure
software use case implementation. This enables us
to increase the number of data acquisition and processing operations within a day (compared to the
software solution of [12]) and monitor an industrial
machine on the short term to achieve timely respond
without IIoT cloud involvement.
Long-term malfunction prediction using advanced
data analytics performed at the enterprise tier using
cloud mechanism is still supported in the above use
case. Edge node devices must transmit processed
data, such as novelty vectors and malfunction events,
to the cloud infrastructure but since preprocessing
of events is done locally cloud communication happens sparsely. Edge intelligence can be also enhanced
by guaranteeing the integrity of data reaching the
cloud by utilizing the SmartFusion 2 SoC dedicated
HMAC peripheral.
The proposed architectural interventions
exploit all available reconfigurability mechanisms to
improve the overall system intelligence and enhance
its adaptability to the rapidly changing conditions
in the modern manufacturing environment. The latest SoC approaches where reconfigurable logic is
combined with hardcoded MCUs introduces a lot
of capabilities on introducing adaptable hardware
assisted intelligence on an IIoT end node and the
IIoT system. In this article, we proposed such an
approach that permits the processing of data using
different algorithms with different complexity at
different layers. Through a specific test case and its
provided experimental results, we demonstrated that
introducing intelligence on the IIoT edge using our
approach is feasible and has significant benefits in
condition-based maintenance by reducing detection speed and energy consumption.

22
Acknowledgments
This work was supported in part by the Project
“I3T—Innovative Application of Industrial Internet
of Things (IIoT) in Smart Environments” under Grant
MIS 5002434 through the Action for the Strategic
Development on the Research and Technological
Sector, in part by the Operational Programme
“Competitiveness, Entrepreneurship, and Innova­
tion” under Grant NSRF 2014-2020, and in part by the
Greece and the European Union through the European Regional Development Fund.

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works, and serious gaming. Anagnostopoulos has a
Diploma in electrical and computer engineering from
the University of Patras, Greece (2004).
Factory Autom., pp. 1–8.
Apostolos
P.
Fournaris is a Principal
Researcher with the Industrial Systems Institute (ISI),
ATHENA Research and Innovation Center, Patras,
Greece. His research interests include hardware and
software codesign, hardware attack resistance, WSN
security, and trusted systems. He is a member of the
IACR, the IEEE, the IEEE Computer Society, and the
IEEE Circuits and Systems Society.
Christos Alexakos is a Research Associate with
the Industrial Systems Institute, ATHENA Research
and Innovation Center, Patras, Greece. His research
interests include knowledge management, information
integration, and systems architecture in enterprise
interoperability, manufacturing automation, Industrial
Internet of Things, and cloud manufacturing. He is a
program committee member of several international
conferences and workshops.
Christos Anagnostopoulos is a Collaborating Researcher with the Industrial Systems Institute,
ATHENA Research and Innovation Center, Patras,
Greece (since 2007). His current research interests include manufacturing systems, industrial net-
July/August 2019
Christos Koulamas is a Research Director
with the Industrial Systems Institute (ISI), ATHENA
Research and Innovation Center, Patras, Greece.
His research interests include real-time distributed
embedded systems, industrial networks, wireless
sensor networks and their applications in industrial
and building automation, transportation, and energy
sectors. He is a Senior Member of the IEEE and a
member of the Technical Chamber of Greece.
Athanasios Kalogeras is a Research Director
with the Industrial Systems Institute, ATHENA
Research and Innovation Center, Patras, Greece. His
research interests include cyber-physical systems,
Industrial Internet of Things, flexible manufacturing
systems, collaborative manufacturing, industrial
integration, and interoperability. He has a PhD
in electrical and computer engineering from the
University of Patras, Greece. He is a Senior Member
of the IEEE.
Direct questions and comments about this
article to Apostolos P. Fournaris, Industrial Systems
Institute, ATHENA Research and Innovation Center,
Patra, Greece; fournaris@isi.gr.

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