DBH CONFIDENTIAL
1830AN18BA High Voltage Analog CMOS
0.18um 1P6M 1.8V/5.0V/30V DESIGN RULE
1830AN18BA-A-DRB ( Rev 2.0 )
(The red-colored characters are the differences from the previous version)
The information of this document is the exclusive property
of Dongbu Hitek and shall be kept confidential. Do not disclose, reproduce,
or distribute this information without prior written permission of Dongbu Hitek.
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DBH CONFIDENTIAL
Contents
1. Introduction ........................................................................................................................................ 5
1. Objective ......................................................................................................................................................... 5
2. 1830AN18BA PROCESS ................................................................................................................................ 5
2. Coding Layer Information.................................................................................................................. 6
1. Drawn Mask Layers (used to construct database) ..................................................................................... 6
2. Definitions (used in Rules) ............................................................................................................................ 9
3. Definition of the layout layer ....................................................................................................................... 10
4. Mask Flow ..................................................................................................................................................... 11
5. Component versus Mask mapping table ................................................................................................... 12
3. Layout Design Rules........................................................................................................................ 16
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
NWELL (NW; rule# 2) .............................................................................................................................. 16
PWELL (PW; rule# 1) .............................................................................................................................. 17
Deep-NWELL (DNW; rule# 22) ............................................................................................................... 19
SD-NWELL (SDNW; rule# 24) ................................................................................................................ 20
SD-PWELL (SDPW; rule# 23) ................................................................................................................. 22
NDT (NDT; rule# 100) .............................................................................................................................. 24
DWELL (DWELL; rule# 102) ................................................................................................................... 25
DIFFUSION (DIFF; rule# 3) ..................................................................................................................... 27
Thick Gate Oxide (TGOX50; rule# 111) ................................................................................................. 31
POLY (POLY; rule# 6) ............................................................................................................................. 32
N+ S/D Implant (NIMP; rule# 8) .............................................................................................................. 34
P+ S/D Implant (PIMP; rule# 7) .............................................................................................................. 36
High Resistor Implant (HRI; rule# 90) ................................................................................................... 38
SALICIDE BLOCK (SAB; rule# 47) ........................................................................................................ 39
CONTACT (CONT; rule# 9)..................................................................................................................... 40
METAL-1 (M1; rule# 10) .......................................................................................................................... 42
VIA 1 (VIA1; rule# 11) ............................................................................................................................. 43
METAL-2 (M2; rule# 12) .......................................................................................................................... 44
VIA2 (VIA2; rule# 13) .............................................................................................................................. 45
METAL-3 (M3; rule# 14) .......................................................................................................................... 46
VIA3 (VIA3; rule#15) ............................................................................................................................... 47
METAL-4 (M4; rule#16) ........................................................................................................................... 48
VIA4 (VIA4; rule#17) ............................................................................................................................... 49
METAL-5 (M5; rule#18) ........................................................................................................................... 50
VIA5 (VIA5; rule#19) ............................................................................................................................... 51
Top metal (M6; rule#20) ......................................................................................................................... 52
Protective Overcoat Removal (POR; rule# 21) .................................................................................... 54
Block Well for Low VT NMOS (BLKWELL; rule#92) ............................................................................ 58
MiM Capacitor Top Metal (MTM; rule#87) ............................................................................................. 60
Voltage Tag (VTAG; VTAG).................................................................................................................... 63
DIE SEAL (SEALRING; rule#38) ............................................................................................................ 64
Antenna Effect Prevention rule (ANT; rule# 51) .................................................................................. 67
Current Density Specification ............................................................................................................... 69
Metal Stress Relief (METAL SLOT; MS) ............................................................................................... 70
Chip Corner, Dummy Pads, Power line Rules (CDP; CDP) ................................................................ 72
Layout Guideline for Latch-Up Prevention (LU; LU) ........................................................................... 74
Dummy Layer Guideline and Generation Rule .................................................................................... 76
4. Component Design Rule ................................................................................................................. 80
1. CMOS ............................................................................................................................................................. 80
1.1 5.0V Standard VT NMOS (nch_svt_5p0v) ......................................................................................... 80
1.2 5.0V Standard VT PMOS (pch_svt_5p0v) .......................................................................................... 81
1.3 5.0V Low VT NMOS (nch_lvt_5p0v) .................................................................................................. 82
1.4 5.0V Isolated Standard VT NMOS (nch_svt_iso_5p0v) ..................................................................... 83
1.5 5.0V Isolated Standard VT PMOS (pch_svt_iso_5p0v) ..................................................................... 85
1.6 1.8V Standard VT NMOS (nch_svt_1p8v) ......................................................................................... 87
1.7 1.8V Standard VT PMOS (pch_svt_1p8v) .......................................................................................... 88
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DBH CONFIDENTIAL
1.8 1.8V Low VT NMOS (nch_lvt_1p8v) .................................................................................................. 89
1.9 1.8V Isolated Standard VT NMOS (nch_svt_iso_1p8v) ..................................................................... 90
1.10 1.8V Isolated Standard VT PMOS (pch_svt_iso_1p8v) ................................................................... 92
2. DE-CMOS ...................................................................................................................................................... 94
2.1 7V Asymmetric DE-NMOS (nch_dea_7v) .......................................................................................... 94
2.2 7V Asymmetric DE-PMOS (pch_dea_7v) .......................................................................................... 96
2.3 7V Isolated Asymmetric DE-NMOS (nch_dea_iso_7v) ...................................................................... 98
2.4 12V Asymmetric DE-NMOS (nch_dea_12v) .................................................................................... 100
2.5 12V Asymmetric DE-PMOS (pch_dea_12v) .................................................................................... 102
2.6 20V Asymmetric DE-NMOS (nch_dea_20v) .................................................................................... 104
2.7 20V Asymmetric DE-PMOS (pch_dea_20v) .................................................................................... 106
2.8 24V Asymmetric DE-NMOS (nch_dea_24v) .................................................................................... 108
2.9 24V Asymmetric DE-PMOS (pch_dea_24v) .................................................................................... 110
2.10 30V Asymmetric DE-NMOS (nch_dea_30v) .................................................................................. 112
2.11 30V Asymmetric DE-PMOS (pch_dea_30v) .................................................................................. 114
3. BJTs ............................................................................................................................................................. 116
3.1 8V vertical NPN (npn_v_8v) ............................................................................................................. 116
3.2 20V Substrate PNP (pnp_s_20v) ..................................................................................................... 118
3.3 5V Vertical NPN w/ SDNW and SDPW (npn_v_hv_5v) ................................................................... 120
3.4 5V Vertical PNP w/ SDNW and SDPW (pnp_v_hv_5v) ................................................................... 122
3.5 10V Lateral PNP (pnp_l_10v) ........................................................................................................... 124
3.6 5V Vertical NPN (npn_v_5v)............................................................................................................. 126
3.7 5V Vertical PNP (pnp_v_5v) ............................................................................................................. 128
4. Resistors ..................................................................................................................................................... 130
4.1 High Sheet Resistance Poly Resistor (res_pp1_hsr, res_pp1_hsr_1k) ........................................... 130
4.2 Low Sheet Resistance Poly Resistor (res_pp1_lsr) ......................................................................... 131
4.3 P+ Poly Non-salicided Resistor (res_pp1) ....................................................................................... 132
4.4 N+ Poly Non-salicided Resistor (res_np1) ....................................................................................... 133
4.5 P+ Diff Non-salicided Resistor (res_pdiff) ........................................................................................ 137
4.6 N+ Diff Non-salicided Resistor (res_ndiff) ........................................................................................ 138
4.7 P+ Diff Silicided Resistor in SDNW (res_pdiff_lsr_sdnw)................................................................. 139
4.8 SDNW Resistor (res_sdnw).............................................................................................................. 140
4.9 P+ Diff Silicided Resistor (res_pdiff_lsr) ........................................................................................... 141
4.10 NWELL Resistor (res_nw) .............................................................................................................. 142
4.11 Poly fuse (res_p1f) ......................................................................................................................... 143
4.12 Metal-1 Resistor (res_m1) .............................................................................................................. 144
4.13 Metal-2 Resistor (res_m2) .............................................................................................................. 145
4.14 Metal-3 Resistor (res_m3) .............................................................................................................. 146
4.15 Metal-4 Resistor (res_m4) .............................................................................................................. 147
4.16 Metal-5 Resistor (res_m5) .............................................................................................................. 148
4.17 Top Metal Resistor (res_top) .......................................................................................................... 149
4.18 Top Thick Metal Resistor (res_top_thick) ....................................................................................... 150
5. Capacitors ................................................................................................................................................... 151
5.1 NPOLY-SDNW Capacitor with thick oxide (cap_sdnwnp1_5p0v).................................................... 151
5.2 MIM Capacitor (cap_mim, cap_mim_1f) .......................................................................................... 152
5.3 NPOLY-NWELL Capacitor with thin oxide (cap_nwnp1_1p8v)........................................................ 154
6. Diodes ......................................................................................................................................................... 155
6.1 NSD-SDPW Diode (dio_nsd_sdpw) ................................................................................................. 155
6.2 PSD-SDNW Diode (dio_psd_sdnw) ................................................................................................. 156
6.3 MV Zener Diode (dio_z_mv)............................................................................................................. 157
6.4 NSD-PWELL Diode (dio_nsd_pw) ................................................................................................... 158
6.5 PSD-NWELL Diode (dio_psd_nw) ................................................................................................... 159
6.6 LV Zener Diode (dio_z_lv) ................................................................................................................ 160
7. NVMs ........................................................................................................................................................... 162
7.1 Single Poly EEPROM_Thick Oxide (nch_ee_5p0v) ......................................................................... 162
7.2 Single Poly EEPROM_Thin Oxide (nch_ee_5p0v_to) ..................................................................... 163
7.3 Single Poly EPROM (pch_eprom_5p0v) .......................................................................................... 164
8. nLDMOS ...................................................................................................................................................... 166
8.1 7V nLDMOS LSD (nch_ldmls_7v) .................................................................................................... 166
8.2 7V nLDMOS HSD (nch_ldmhs_7v) .................................................................................................. 168
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DBH CONFIDENTIAL
8.3 12V nLDMOS LSD (nch_ldmls_12v) ................................................................................................ 171
8.4 12V nLDMOS HSD (nch_ldmhs_12v) .............................................................................................. 173
8.5 20V nLDMOS LSD (nch_ldmls_20v) ................................................................................................ 176
8.6 18V nLDMOS HSD (nch_ldmhs_18v) .............................................................................................. 178
8.7 24V nLDMOS LSD (nch_ldmls_24v) ................................................................................................ 181
8.8 30V nLDMOS LSD (nch_ldmls_30v) ................................................................................................ 183
9. I/O ESD Protection Circuit Design and Layout Guideline ...................................................................... 185
9.1 1.8V & 5.0V ESD Protection Device ................................................................................................. 185
9.2 7V ESD Protection Device (esd_hv_pig_7v) .................................................................................... 195
9.3 7V ESD Protection Device (esd_hv_gc_7v) ..................................................................................... 197
9.4 12V ESD Protection Device (esd_hv_12v)....................................................................................... 198
9.5 12V ESD Protection Device (esd_hv_gg_12v)................................................................................. 200
9.6 12V ESD Protection Device (esd_hv_gc_12v) ................................................................................. 201
9.7 20V ESD Protection Device (esd_hv_gg_20v)................................................................................. 202
9.8 20V ESD Protection Device (esd_hv_gc_20v) ................................................................................. 203
9.9 24V ESD Protection Device (esd_hv_gc_24v) ................................................................................. 204
9.10 20V and 24V ESD Protection Device (esd_hv_24v) ...................................................................... 205
9.11 24V ESD Protection Device (esd_hv_gg_24v) .............................................................................. 207
9.12 30V ESD Protection Device (esd_hv_gg_30v) .............................................................................. 208
9.13 30V ESD Protection Device (esd_hv_gc_30v) ............................................................................... 209
9.14 NSD-PWELL Diode (dio_nsd_pw_esd) .......................................................................................... 210
9.15 PSD-NWELL Diode (dio_psd_nw_esd) .......................................................................................... 211
9.16 ESD Protection Diode (dio_hv_esd) ............................................................................................... 212
10. CMOS & I/O Isolation ............................................................................................................................... 214
10.1 Isolating SDNW ring (nch_svt_iso_5p0v, pch_svt_iso_5p0v, nch_io_iso_5p0v_6t, pch_io_iso
_5p0v_5t, nch_pp_iso_5p0v_6t) ............................................................................................................ 214
10.2 Isolating NWELL ring (nch_svt_iso_1p8v, pch_svt_iso_1p8v, nch_io_iso_1p8v_6t,
pch_io_iso_1p8v_5t, nch_pp_iso_1p8v_6t) ........................................................................................... 216
11. Field Transistor ........................................................................................................................................ 218
11.1 20V P-Channel Field Transistor (pch_des_ftr_20v) ....................................................................... 218
12.Integrated backgate contact layout guideline for Power CMOS .......................................................... 220
5.Revision History.............................................................................................................................. 222
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DBH CONFIDENTIAL
1. Introduction
1. Objective
This document describes the physical layout design rules for the Dongbu HiTek (DBH) 0.18um high voltage
analog cmos process. 1830AN18BA is a high voltage analog cmos process. Minimum allowed drawn layer
dimensions and rules are tabulated. This includes 1P2M to 1P6M process. Among them, 1P6M process is treated
as a generic process in this document. For other process, please refer to following table for its usage of this
design rule.
Process
1P2M
Description
Metal 2 obey to Metal 6 design rule in this document,
Via 1 obey to Via 5 design rule in this document.
Note) MiM capacitor is not supported in this process.
1P3M
Metal 3 obey to Metal 6 design rule in this document,
Via 2 obey to Via 5 design rule in this document.
1P4M
Metal 4 obey to Metal 6 design rule in this document,
Via 3 obey to Via 5 design rule in this document.
1P5M
Metal 5 obey to Metal 6 design rule in this document,
Via 4 obey to Via 5 design rule in this document.
2. 1830AN18BA PROCESS
1830AN18BA is the process to address analog and high voltage applications combined with high performance
and high density ULSI applications. 1830AN18BA process flows support stacked vias/contact and have the option
of 2, 3, 4, 5 or 6 layers of metal. In addition, a salicide block mask is available for the use in resistor formation.
PROCESS
LOGIC (V)
Core
I/O
1830AN18BA 1.8/5.0 5.0
DEMOS (V)
LDMOS (V)
BIPOLAR (V)
7/12/20/24/30
7/12/20/24/30 5, 8, 10, 20
*FET POLY C.D. (m)
Core
I/O
0.18/0.50
0.50
*) Drawn Poly CD
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DBH CONFIDENTIAL
2. Coding Layer Information
1. Drawn Mask Layers (used to construct database)
Layer name
Purpose
Layer
#
1
Data
type
0
Description
PWELL
drawing
P-type well for N-channel devices of 1.8V.
PWELL
text
1
1
Pwell Text
NWELL
drawing
2
0
N-type well for P-channel devices of 1.8V.
NWELL
DIFF
DIFF
POLY
POLY
PIMP
NIMP
CONT
MET1
MET1
MET1
VIA1
MET2
MET2
MET2
VIA2
MET3
MET3
MET3
VIA3
MET4
MET4
MET4
VIA4
MET5
MET5
MET5
VIA5
MET6
MET6
MET6
POR
DNW
text
drawing
text
drawing
text
drawing
drawing
drawing
drawing
text
slot
drawing
drawing
text
slot
drawing
drawing
text
slot
drawing
drawing
text
slot
drawing
drawing
text
slot
drawing
drawing
text
slot
drawing
drawing
2
3
3
6
6
7
8
9
10
10
10
11
12
12
12
13
14
14
14
15
16
16
16
17
18
18
18
19
20
20
20
21
22
1
0
1
0
1
0
0
0
0
1
2
0
0
1
2
0
0
1
2
0
0
1
2
0
0
1
2
0
0
1
2
0
0
SDPW
drawing
23
0
SDNW
METTOP
RESIST
drawing
drawing
drawing
24
26
31
0
0
0
NWRES
drawing
32
0
BTAG
SDI
METRES
METRES
drawing
drawing
metres1
metres2
33
34
35
35
0
0
1
2
Nwell Text
Active regions
Active Text
First polysilicon layer
Poly Text
P+ source / drain.
N+ source / drain.
Contact
Metal-1 interconnect
Metal1 Text
Metal-1 Slot for metal stress relief
Vias between Metal-1 and Metal-2
Metal-2 interconnect
Metal2 Text
Metal-2 Slot for metal stress relief
Vias between Metal-2 and Metal-3.
Metal-3 interconnect
Metal3 Text
Metal-3 Slot for metal stress relief
Vias between Metal-2 and Metal-3.
Metal-4 interconnect
Metal4 Text
Metal-4 Slot for metal stress relief
Vias between Metal-3 and Metal-4
Metal-5 interconnect
Metal5 Text
Metal-5 Slot for metal stress relief
Vias between Metal-4 and Metal-5
Metal-6 interconnect
Metal6 Text
Metal-6 Slot for metal stress relief
Protective Overcoat openings for bond pads
High energy implanted deep n-type well.
P-type well for N-channel devices of 5.0V.
SDPW is also extracted as part of the high-voltage p-CHST strategy.
N-type well for P-channel devices of 5.0V.
Copper/Nickel/Gold (Cu BOAC) metal layer on PO
Resistor Marker for Active/Poly Resistor
Dummy layer to recognize the NWELL resistor (for LVS) & Blocking the
dummy diff generation.
Dummy layer to recognize the bipolar (for LVS)
I/O Device Marker
Metal-1 Resistor Marker
Metal-2 Resistor Marker
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DBH CONFIDENTIAL
METRES
METRES
METRES
METRES
POWPRO
HOTNW
SEALRING
POLY_CAP
DUMBLK
DUMBLK
DUMBLK
DUMBLK
DUMBLK
DUMBLK
DUMBLK
DUMBLK
DUMBLK
DUMMETBLK
ARTBOUNDRY
metres3
metres4
metres5
metres6
drawing
drawing
drawing
drawing
all
met1
met2
met3
met4
met5
met6
diff
poly
drawing
drawing
35
35
35
35
36
37
38
39
40
40
40
40
40
40
40
40
40
41
42
3
4
5
6
0
0
0
0
0
1
2
3
4
5
6
7
8
0
0
Metal-3 Resistor Marker
Metal-4 Resistor Marker
Metal-5 Resistor Marker
Metal-6 Resistor Marker
Dummy layer to recognize the 1.8V/5.0V Power Protection device (for LVS)
Hot-Nwell Marker for DRC
Sealring Marker
Dummy layer to recognize the mos capacitor (for LVS)
Blocks generation of all dummy layers
Blocks generation of dummy metal1
Blocks generation of dummy metal2
Blocks generation of dummy metal3
Blocks generation of dummy metal4
Blocks generation of dummy metal5
Blocks generation of dummy metal6
Blocks generation of dummy diff
Blocks generation of dummy poly
Blocks generation of all dummy metals
Artisan Cell Boundary
Dummy layer to recognize the PIP capacitor (effective capacitor area; for
LVS)
Dummy layers for comments
This layer defines the length and width at mos capacitor
Do not check grid rule
Salicide Blocking Area
DRC Exclude Marker
Guardring layer – This layer is reserved for future use to simplify guardring
extraction and verification.
This layer defines the bonding machine target coordinates and is used to
provide this info to the ARC software. It defines the Bondpad area for Top
Metal and Cu bondpads
Antenna diode marker
ESD implant layer. Reserved for 3.3v option
Cell Name Text
Dummy layer to recognize the varactor
Isolation pwell layer for multiple ground (for LVS)
Dummy layer to recognize the die boundary
Blocking dummy fill in ESD (option)
Marker layer for DBH I/O (ex:Artisan)
PIP
drawing
43
0
TXT
MCW
NOGRID
SAB
DRCDMY
text
drawing
drawing
drawing
drawing
44
45
46
47
48
0
0
0
0
0
GR
drawing
49
0
BOND
drawing
50
0
ANT
ESD
CELLNAME
VARDMY
ISPWELL
BOUNDARY
BLKIO
DASDMY
drawing
drawing
text
drawing
drawing
drawing
drawing
drawing63
51
52
53
54
55
56
57
63
0
0
0
0
0
0
0
63
SRAM
drawing
64
0
Dummy layer to recognize the SRAM cell array area (for DRC and to
generate special implant layer)
ESDMY
ESDMY2
DTAG
DRNTAG
ESDMY1
POLY2
MTM
FUSE
HRI
HRID
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
68
69
70
71
76
86
87
88
90
91
0
0
0
0
0
0
0
0
0
0
ESD dummy for LVS, DRC and generation by 1.8V or 3.3V nMOS
ESD dummy for only DBH IO (Reserved)
Dummy layer to recognize the diode (for LVS)
Dummy layer to recognize the ESD (for LVS)
ESD dummy for only DBH IO (Reserved)
Second polysilicon layer
Top electrode of MiM capacitor
Dummy layer to recognize poly fuse for LVS/DRC
High sheet rho resistor implant
Blocks LDD & S/D implant
BLKWELL
drawing
92
0
Dummy layer for blocking the NWELL/SDNW implant & PWELL/SDPW
implant to make the native MOS
LDMTAG
drawing
94
0
Dummy layer for LDMOS
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DBH CONFIDENTIAL
STD_B
NDT
PDT
DWELL
PCHSTBLK
SDBLK
TGOX50
V2
V5
V7
V12
V20
V30
ESDT45
ISO_V7
ISO_V30
CDM
FG
CVT
CSD
FC
CUP_DIA
MTM1
ZENER
EEPROM
EPROM
ANLGDMY
LDDBLK
NSDBLK
PSDBLK
LVGD
FUSOR
ESDSTK
ESDBOT
CUST1
CUST2
CUST3
CUST4
CUST5
OVERLAP
DBL
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
drawing
boundary
drawing
95
100
101
102
105
107
111
112
114
115
116
117
118
131
135
136
137
141
142
143
144
145
147
148
149
150
154
155
161
162
163
165
166
167
181
182
183
184
185
190
191
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Boundary layer for standard cell library.
N-type drift region for nLDMOS
P-type drift region for 30V DE-PMOS
Double-diffused well used for nLDMOS
Blocks generation of PCHST
N+SD/P+SD Implant blocking layer
5.0V gate oxide regions
This layer is used to define nodes that will not exceed 1.98v max.
This layer is used to define nodes that will not exceed 5.5v max.
This layer is used to define nodes that will not exceed 7.7v max.
This layer is used to define nodes that will not exceed 13.2v max.
This layer is used to define nodes that will not exceed 22v max.
This layer is used to define nodes that will not exceed 33v max.
Dummy layer to recognize the 4,5 terminal IO TR
Dummy layer to recognize the isolation
Dummy layer to recognize the isolation
Dummy layer to recognize the CDM device
Defines floating gate at cell array
Defines Vt adjust of cell & tunnel ox of flash cell
Defines floating cell source/drain implantation region
Defines logic area open
Dummy layer to recognize CUP with top via array like diamond shape
Top electrode of MiM1 capacitor at stacked MiM capacitor
Dummy layer for Zener diode.
Dummy layer to recognize the EEPROM (for LVS)
Dummy layer to recognize the EPROM (for LVS)
Dummy layer to recognize analog tr. used to LER
LDD Implant blocking layer
N+SD Implant blocking layer
P+SD Implant blocking layer
Dummy layer to recognize special low Vgs LDMOS
Define passivation opening region for metal fuse option
Dummy layer to recognize stacked esd device
Dummy layer to recognize the bottom device of stacked esd device
Reserved for customer’s usage
Reserved for customer’s usage
Reserved for customer’s usage
Reserved for customer’s usage
Reserved for customer’s usage
8 of 224
DBH CONFIDENTIAL
2. Definitions (used in Rules)
Name
Description
NDIFF
PDIFF
common area of DIFF and NIMP
common area of DIFF and PIMP
FIELD
reverse of DIFF
TAPDIFF
POLYDIFF
POLYGATE
GOX50GATE
CONTGOX50
DIFFGOX50
DIFFCONT
POLYCONT
LVNDIFF
HVNDIFF
LVPDIFF
HVPDIFF
LVDIFF
HVDIFF
common area of DIFF AND (NIMP in (NWELL OR SDNW) OR PIMP in (PWELL OR SDPW))
common area of POLY and DIFF
POLYDIFF common to NIMP in (PWELL OR SDPW) OR PIMP in (NWELL OR SDNW)
POLYGATE common to TGOX50
common area of CONT and TGOX50
common area of DIFF and TGOX50
common area of DIFF and CONT
common area of POLY and CONT
common area of NDIFF and (PWELL OR SDPW) outside TGOX50
common area of NDIFF and (PWELL OR SDPW) inside TGOX50
common area of PDIFF and (NWELL OR SDNW) outside TGOX50
common area of PDIFF and (NWELL OR SDNW) inside TGOX50
common area of LVNDIFF and LVPDIFF
common area of HVNDIFF and HVPDIFF
Common area of ((NIMP and (PWELL OR SDPW)) OR (PIMP and (NWELL OR SDNW))) outside
TGOX50
Common area of ((NIMP and (PWELL OR SDPW)) OR (PIMP and (NWELL OR SDNW))) inside
TGOX50
NWELL touching HVDIFF
POLY extension onto FIELD
Metal landing pad. A small area metal features that enclose only one contact or one via (often used
for stacking contacts and vias)
PWELL in DNW
LVIMP
HVIMP
HVNWELL
POLYEXT
MnLPAD (n=1-5)
RWELL
9 of 224
DBH CONFIDENTIAL
3. Definition of the layout layer
Width (W):
Width of a L1
Space (S):
Space between
two L1
Space between L1 and
L2 or
Space of L1 to L2
Extension (X):
Extension of L1
beyond L2
Enclosure (E):
Enclosure of L2
by L1
Overlap (O):
Overlap of L2 to
L1
Minimum Design Rule Increment
: 0.01um (Except the rule No. 10E9a)
Minimum Layout Coding Increment
: 0.005um
Minimum PG Grid Size
: 0.005um
10 of 224
DBH CONFIDENTIAL
4. Mask Flow
Serial No. Category
Mask Name
Description
Polarity
MOAT
Active region
D
N-type drift for nLDMOS
C
1
Basic
O-5
Option5
NDT
O-5
Option5
DWELL
2
Basic
SDPW
P-body for nLDMOS
P-type well for 5.0V CMOS and p-type drift / channel stop layer for HV
devices
N-type well for 5.0V CMOS and n-type drift layer for HV devices
C
C
3
Basic
SDNW
O-2
Option2
PDT
P-type drift for 30V DE-PMOS
C
C
4
Basic
DNW
Deep n-type well for isolating logic region from P-sub.
C
O-1
Option1
PWELL
P-type well for 1.8V CMOS
C
O-1
Option1
NWELL
N-type well for 1.8V CMOS.
C
O-4
Option4
FG
Tunneling oxide and floating gate region
D
O-1
Option1
TGOX
Thick gate oxide region
D
5
Basic
POLY
Gate Poly
D
O-1
Option1
LV-NLDD
NLDD implant for 1.8V n-channel devices
C
6
Basic
HV-NLDD
NLDD implant for 5.0V & HV n-channel devices
C
O-1
Option1
LV-PLDD
PLDD implant for 1.8V p-channel devices
C
7
Basic
HV-PLDD
PLDD implant for 5.0V & HV p-channel devices
C
8
Basic
NSD
N+ SD implant
C
9
Basic
PSD
P+ SD implant
C
O-3
Option3
HRI
HRI implant for high sheet rho resistor
C
10
Basic
SAB
Silicide blocking
D
11
Basic
CONT
Active or Poly to Metal-1 connection
C
12
Basic
METAL-1
Metal-1
D
13
Basic
VIA-1
Metal-1 to Metal-2 connection
C
14
Basic
METAL-2
Metal-2
D
15
Basic
VIA-2
Metal-2 to Metal-3 connection
C
16
Basic
METAL-3
Metal-3
D
17
Basic
VIA-3
Metal-3 to Metal-4 connection
C
18
Basic
METAL-4
Metal-4
D
19
Basic
VIA-4
Metal-4 to Metal-5 connection
C
O-3
Option3
MIM
Top electrode of MIM capacitor
D
20
Basic
METAL-5
Metal-5
D
21
Basic
VIA-5
Metal-5 to Metal-6 connection
C
22
Basic
METAL-6
Metal-6
D
23
Basic
POR
Passivation opening
C
Option1) 5-mask layers used for 1.8V CMOS
Option2) 1-mask layer used for 30V DE-PMOS
Option3) 2-mask layers used for each HSR poly resistor and MiM capacitor
Option4) 1-mask layer used for single poly EEPROM with dedicated tunnel oxide
Option5) 2-mask layers used for 7V to 30V nLDMOS
11 of 224
DBH CONFIDENTIAL
5. Component versus Mask mapping table
5V/HV device w/o option mask
5.0V CMOS
5.0V Std VT NMOS
nch_svt_5p0v
★
5.0V Std VT PMOS
pch_svt_5p0v
★
5.0V Low VT NMOS
nch_lvt_5p0v
★
★
5.0V Iso Std VT NMOS nch_svt_iso_5p0v
★
★ ★
5.0V Iso Std VT PMOS pch_svt_iso_5p0v
★
★
★
★
★ ★ ★
★ ★
★
★
★ ★ ★
★ ★
★
★
★ ★ ★
★ ★
★
★
★
★ ★ ★
★ ★
★
★
★
★
★ ★ ★
★ ★
★
DE-CMOS
7V Asym DE-NMOS
nch_dea_7v
★
★
★
★ ★ ★
★ ★ ★
7V Asym DE-PMOS
pch_dea_7v
★
★
★
★
★
★ ★ ★
★ ★ ★
7V Iso Asym DE-NMOS nch_dea_iso_7v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★
12V Asym DE-NMOS
nch_dea_12v
★
★ ★
★
★
★ ★ ★
★ ★ ★
12V Asym DE-PMOS
pch_dea_12v
★
★ ★
★
★
★ ★ ★
★ ★ ★
20V Asym DE-NMOS
nch_dea_20v
★
★ ★
★
★
★ ★ ★
★ ★
20V Asym DE-PMOS
pch_dea_20v
★
★ ★
★
★
★ ★ ★
★ ★
24V Asym DE-NMOS
nch_dea_24v
★
★ ★
★
★
★ ★ ★
★ ★
24V Asym DE-PMOS
pch_dea_24v
★
★ ★
★
★
★ ★ ★
★ ★
30V Asym DE-NMOS
nch_dea_30v
★
★ ★
★
★
★ ★ ★
★ ★
8V Vertical NPN
npn_v_8v
★
★ ★
★
★ ★ ★
★ ★
20V Substrate PNP
pnp_s_20v
★
★ ★
★
★ ★ ★
★ ★
5.0V Vertical NPN (HV) npn_v_hv_5p0v
★
★ ★
★
★ ★ ★
★ ★
5.0V Vertical PNP (HV) pnp_v_hv_5p0v
★
★ ★
★
★ ★ ★
★ ★
cap_sdnwnp1_5p0v ★
★ ★
★
★ ★ ★
★ ★
★
★
★
★
BJT
Capacitor
NPOLY-SDNW
Capacitor
Resistor
LSR Poly Resistor
(silicided)
P+ Poly Non-sal
Resistor
N+ Poly Non-sal
Resistor
NDIFF Resistor
PDIFF Resistor
★
★
★
res_pp1_lsr
★
★
★
★ ★
res_pp1
★
★
★
★ ★ ★
res_np1
★
★
★
★ ★ ★
res_ndiff
★
★
★ ★ ★
★ ★ ★
res_pdiff
★
★
★
★ ★ ★
★ ★ ★
★
★ ★
★
★ ★ ★
★ ★
★
★
★
★ ★ ★
★ ★
★
★
★ ★
SDNW Resistor
res_sdnw
PDIFF Silicided Resistor
res_pdiff_lsr_sdnw
in SDNW
Poly Fuse
res_p1f
★
★
Metal-1 Resistor
res_m1
Metal-2 Resistor
res_m2
Metal-3 Resistor
res_m3
Metal-4 Resistor
res_m4
Metal-5 Resistor
res_m5
★ ★ ★
Top Metal Resistor
res_top
★ ★ ★
★ ★ ★
★ ★ ★
★ ★ ★
★ ★
Top Thick Metal Resistor res_top_thick
★
★ ★ ★
Diode
NSD/SDPW Diode
dio_nsd_sdpw
★
PSD/SDNW Diode
dio_psd_sdnw
★
★
MV Zener Diode
dio_z_mv
★
★ ★
★
★
★
★ ★ ★
★
★ ★ ★
★ ★
★ ★
★
★ ★ ★
★ ★ ★
12 of 224
POR
MET6
VIA5
MET5
MIM(O3)
VIA4
MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1
CONT
SAB
HRI (O3)
PSD
NSD
HVPLDD
LVPLDD(O1)
HVNLDD
LVNLDD(O1)
POLY
FG (O4)
TGOX (O1)
NWELL(O1)
PWELL(O1)
DNW
PDT (O2)
SDNW
SDPW
DWELL(O5)
Name
MOAT
Component
NDT (O5)
Mask Name (O; Option)
DBH CONFIDENTIAL
Memory
single poly EEPROM w/
nch_ee_5p0v
thick tunnel oxide
single poly EPROM
pch_eprom_5p0v
★
★ ★
★
★
★ ★ ★
★ ★ ★
★
★ ★
★
★
★
★ ★ ★
★ ★ ★
Field Transistor
20V P-Channel Field
Transistor
I/O and ESD
★
★ ★
★
★
★
★ ★ ★
★ ★
5.0V Regular I/O NMOS nch_io_5p0v
★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
5.0V I/O PMOS
pch_io_5p0v
5.0V Power Protection
nch_pp_5p0v
NMOS
5.0V Regular I/O NMOS nch_io_5p0v_4t
★
★
★
★ ★ ★
★ ★ ★ ★ ★
5.0V I/O PMOS
5.0V Power Protection
NMOS
5.0V Iso. Regular I/O
NMOS
5.0V Iso. I/O PMOS
5.0V Iso. Power
Protection NMOS
7V ESD Protection
Device
7V ESD Protection
Device
12V ESD Protection
Device
12V ESD Protection
Device
12V ESD Protection
Device
20V ESD Protection
Device
20V ESD Protection
Device
24V ESD Protection
Device
20V and 24V ESD
Protection Device
24V ESD Protection
Device
30V ESD Protection
Device
20V ESD Protection
Device
pch_io_5p0v_5t
★
nch_pp_5p0v_4t
★
ESD Protection Diode
pch_des_ftr_20v
★
★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
★
★
★
★
★ ★ ★
★ ★ ★
★
★
★ ★ ★
★ ★ ★
★
★
★ ★ ★
★ ★ ★
★
★
nch_io_iso_5p0v_6t ★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
pch_io_iso_5p0v_5t ★
★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
nch_pp_iso_5p0v_6
★
t
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_pig_7v
★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_gc_7v
★
★ ★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_12v
★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_gg_12v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_gc_12v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_gg_20v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_gc_20v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_gc_24v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_24v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_gg_24v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_gg_30v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
esd_hv_gc_30v
★
★ ★
★
★
★
★ ★ ★
★ ★ ★ ★ ★
dio_hv_esd
★
★ ★
★
★ ★
★ ★ ★ ★
★
13 of 224
POR
MET6
VIA5
MET5
MIM(O3)
VIA4
MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1
CONT
SAB
HRI (O3)
PSD
NSD
HVPLDD
LVPLDD(O1)
HVNLDD
LVNLDD(O1)
POLY
FG (O4)
TGOX (O1)
NWELL(O1)
PWELL(O1)
DNW
PDT (O2)
SDNW
SDPW
DWELL(O5)
Name
MOAT
Component
NDT (O5)
Mask Name (O; Option)
DBH CONFIDENTIAL
1.8V device w/ option-1 mask
1.8V CMOS
1.8V Std VT NMOS
nch_svt_1p8v
★
1.8V Std VT PMOS
pch_svt_1p8v
★
1.8V Low VT NMOS
nch_lvt_1p8v
★
★
★
★ ★
★
★ ★
★
★
★ ★
★ ★
★ ★
★ ★
★
★ ★
★ ★
★ ★
★ ★
★ ★
★ ★
★ ★
1.8V Iso. Std VT NMOS nch_svt_iso_1p8v
★
★ ★ ★ ★
★ ★
1.8V Iso. Std VT PMOS pch_svt_iso_1p8v
★
★
★
★ ★
★
BJT
10V Lateral PNP
pnp_l_10v
★
5.0V Vertical NPN
npn_v_5p0v
★
5.0V Vertical PNP
pnp_v_5p0v
★
★ ★ ★
Capacitor
NPOLY-NWELL
Capacitor
Resistor
cap_nwnp1_1p8v
★
★ ★ ★
NWELL Resistor
res_nw
★
★
PDIFF Silicided Resistor res_pdiff_lsr
★
★ ★ ★
★
★ ★ ★
★ ★
★ ★ ★
★
★ ★ ★
★ ★
★ ★
★ ★
★ ★
★ ★
★ ★ ★
★ ★
★ ★
★ ★
★ ★ ★
★ ★
★ ★
★ ★
★
★ ★
Diode
NSD/PWELL Diode
dio_nsd_pw
★
PSD/NWELL Diode
dio_psd_nw
★
LV Zener Diode
dio_z_lv
★
★
★
★
★ ★
★
★
★ ★ ★
★
★ ★
★ ★
★ ★ ★
★ ★ ★
I/O and ESD
1.8V Regular I/O NMOS nch_io_1p8v
★
1.8V I/O PMOS
pch_io_1p8v
1.8V Power Protection
nch_pp_1p8v
NMOS
1.8V Regular I/O NMOS nch_io_1p8v_4t
★
1.8V I/O PMOS
1.8V Power Protection
NMOS
1.8V Iso. Regular I/O
NMOS
1.8V Iso. I/O PMOS
1.8V Iso. Power
Protection NMOS
NSD-PWELL Diode
pch_io_1p8v_5t
★
nch_pp_1p8v_4t
★
PSD-NWELL Diode
dio_psd_nw_esd
★
★
★ ★
★ ★
★
★
★ ★
★ ★ ★ ★ ★
★ ★
★ ★ ★ ★ ★
★
★
★
★ ★
★ ★
★ ★ ★ ★ ★
★
★
★
★ ★
★ ★
★ ★ ★
★ ★
★ ★ ★
★ ★
★ ★ ★
★ ★
★ ★ ★
★ ★
★ ★ ★
★ ★
★ ★
★ ★ ★
★
★ ★
★ ★
★ ★
★ ★
★ ★
★
★
★ ★
nch_io_iso_1p8v_6t ★
★ ★ ★ ★
★ ★
pch_io_iso_1p8v_5t ★
nch_pp_iso_1p8v_6
★
t
★
dio_nsd_pw_esd
★
★
★
★
★
★ ★
★ ★ ★ ★
★
★
★ ★
★
★
14 of 224
POR
MET6
VIA5
MET5
MIM(O3)
VIA4
MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1
CONT
SAB
HRI (O3)
PSD
NSD
HVPLDD
LVPLDD(O1)
HVNLDD
LVNLDD(O1)
POLY
FG (O4)
TGOX (O1)
NWELL(O1)
PWELL(O1)
DNW
PDT (O2)
SDNW
SDPW
DWELL(O5)
Name
MOAT
Component
NDT (O5)
Mask Name (O; Option)
DBH CONFIDENTIAL
30V DE-PMOS w/ option-2 mask
DE-CMOS
30V Asym DE-PMOS
pch_dea_30v
★
★ ★ ★
★
★
★ ★ ★
★ ★
HSR and MiM w/ option-3 mask
Capacitor
MIM Capacitor_2fF
cap_mim
★ ★ ★ ★ ★ ★
MIM Capacitor_1fF
cap_mim_1f
★ ★ ★ ★ ★ ★
Resistor
HSR Poly Resistor (HRI) res_pp1_hsr
HSR Poly Resistor
res_pp1_hsr_1k
(HRI)_1k
★
★
★ ★ ★ ★ ★
★
★
★ ★ ★ ★ ★
1P-E2PROM w/ option-4 mask
Memory
single poly EEPROM w/
nch_ee_5p0v_to
thin tunnel oxide
★
★ ★
★
★ ★
★
★ ★ ★
★ ★ ★
★
★
★ ★ ★
★ ★ ★ ★ ★
★
★
★ ★ ★
★ ★ ★ ★ ★
★
★
★ ★ ★
★ ★ ★ ★ ★
★
★
★ ★ ★
★ ★ ★ ★ ★
★
★
★ ★ ★
★ ★ ★ ★
★
★
★ ★ ★
★ ★ ★ ★
nLDMOS w/ option-5 mask
nLDMOS
7V nLDMOS LS
nch_ldmls_7v
★ ★ ★ ★
7V nLDMOS HS
nch_ldmhs_7v
★ ★ ★ ★ ★
12V nLDMOS LS
nch_ldmls_12v
★ ★ ★ ★
12V nLDMOS HS
nch_ldmhs_12v
★ ★ ★ ★ ★
20V nLDMOS LS
nch_ldmls_20v
★ ★ ★ ★
18V nLDMOS HS
nch_ldmhs_20v
★ ★ ★ ★ ★
24V nLDMOS LS
nch_ldmls_24v
★ ★ ★ ★
★
★
★ ★ ★
★ ★ ★ ★
30V nLDMOS LS
nch_ldmls_30v
★ ★ ★ ★
★
★
★ ★ ★
★ ★ ★ ★
★
★
★
15 of 224
POR
MET6
VIA5
MET5
MIM(O3)
VIA4
MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1
CONT
SAB
HRI (O3)
PSD
NSD
HVPLDD
LVPLDD(O1)
HVNLDD
LVNLDD(O1)
POLY
FG (O4)
TGOX (O1)
NWELL(O1)
PWELL(O1)
DNW
PDT (O2)
SDNW
SDPW
DWELL(O5)
Name
MOAT
Component
NDT (O5)
Mask Name (O; Option)
DBH CONFIDENTIAL
3. Layout Design Rules
1.NWELL (NW; rule# 2)
Rule No.
Description
2W2a
min. width of a NW
2S2a
2S2b
2S2c
2S2d
2S2e
2Na
2Ga
2Ra
Conditions
Different node (V2, V5, V7, ISO_V7,
including no voltage tag)
min. space between two NW
Different node (V12)
min. space between two NW
Different node (V20)
min. space between two NW
Different node (V30, ISO_V30)
min. space between two NW
Same node
Space rule between Layers with different voltage tag obey rule with higher
voltage tag.
Drawn NW must conform to a
Exception: If NOGRID layer exist, off-grid is
0.005um on-grid rule
ok.
NW and PDT must not be overlapped or coincident.
min. space between two NW
2W2a
Layout
Rule (um)
0.86
1.40
2.40
3.40
4.40
0.60
2S2a/b/c/d
2S2e
NWELL
16 of 224
DBH CONFIDENTIAL
2.PWELL (PW; rule# 1)
Rule No.
1W1a
1Ra
1S1a
1S1b
1S1c
1S1d
1S1e
1S2a
1S2b
1S2c
1S2d
1Na
1Rb
1Rc
1Ga
Description
Conditions
min. width of a PW
To use PW with different potential from substrate, at least one PW is enclosed
by DNW and surrounded by NW or SDNW.
Different node (V2, V5, V7,
min. space between two PW
including no voltage tag)
min. space between two PW
Different node (V12)
min. space between two PW
Different node (V20)
min. space between two PW
Different node (V30)
min. space between two PW
Same node
In V2, V5, V7, ISO_V7,
min. space PW to NW
including no voltage tag
In V12,
min. space PW to NW
Exception; pnp_l_10v
min. space PW to NW
In V20
In V30, ISO_V30
min. space PW to NW
Exception; Inner edge of NW
for iso-ring in ISO_V30
Space rule between Layers with different voltage tag obey rule with higher
voltage tag.
PW and NW must not be overlapped or coincident.
PW and PDT must not be overlapped or coincident.
Drawn PW must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
Layout
Rule (um)
0.86
1.40
2.40
3.40
4.40
0.60
0.00
0.50
1.00
1.50
17 of 224
DBH CONFIDENTIAL
1W1a
1S1a/b/c/d
1S1e
1S2a/b/c/d
NWELL
PWELL
DNW
ISO_V30
1S2d
18 of 224
DBH CONFIDENTIAL
3.Deep-NWELL (DNW; rule# 22)
Rule No.
Description
22W22a
22S22a
min. width of a DNW
min. space between two DNW
22X2a
min. extension of NW beyond DNW
22O2a
min. overlap of DNW to NW
22S2a
22Ra
22Rb
22Rc
22Ga
Layout
Rule (um)
3.00
5.00
Conditions
Exception; ESD components
with ESDMY
Exception; ESD components
with ESDMY
min. space of DNW to NW
DNW edge must be surrounded by NW or
Exception; nch_ee_5p0v_to
SDNW.
Not allowed to use one DNW layer as one well resistor.
Not allowed to use one SDNW layer connected to DNW as one resistor.
Drawn DNW must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
1.50
2.00
3.50
22X2a
22W22a
22O2a
22S22a
22S2a
NWELL
PWELL
DNW
19 of 224
DBH CONFIDENTIAL
4.SD-NWELL (SDNW; rule# 24)
Rule No.
Description
24W24a
min. width of a SDNW
24S24a
24S24b
24S24c
24S24d
24S24e
24X22a
24O22a
24S2a
24S2b
24S2c
24S2d
24S2e
24S2f
24S1a
24S1b
24S1c
24S1d
24Na
24Ra
24Rb
24Ga
Conditions
Different node (V2, V5, V7,
ISO_V7)
min. space between two SDNW
Different node (V12)
min. space between two SDNW
Different node (V20)
Different node (V30, ISO_V30
min. space between two SDNW
including no voltage tag)
min. space between two SDNW
Same node
min. extension of SDNW beyond DNW
Exception; nch_ee_5p0v_to
Exception;
esd_hv_24v,
esd_gc_7v,
esd_gc_12v,
esd_gc_20v,
esd_gc_24v,
min. overlap of DNW to SDNW
esd_gc_30v, esd_hv_gg_12v,
esd_hv_gg_20v,
esd_hv_gg_24v,
esd_hv_gg_30v
Different node (V2, V5, V7,
min. space of SDNW to NW
ISO_V7)
min. space of SDNW to NW
Different node (V12)
min. space of SDNW to NW
Different node (V20)
Different node (V30,
min. space of SDNW to NW
ISO_V30)
min. space of SDNW to NW
Different node (no voltage tag)
Same node
min. space of SDNW to NW
Overlap ok, Coincident ok,
Butting ok
min. space of SDNW to PW
In V2, V5, V7, ISO_V7
In V12
min. space of SDNW to PW
Exception; pnp_l_10v
min. space of SDNW to PW
In V20
In V30, ISO_V30, including no
voltage tag
min. space of SDNW to PW
Exception;
Inner edge of SDNW for isoring in ISO_V30
Space rule between Layers with different voltage tag obey rule with higher
voltage tag
SDNW and PW must not be overlapped or coincident.
SDNW and PDT must not be overlapped or coincident.
Drawn SDNW must conform to a 0.005um
Exception: If NOGRID layer
on-grid rule
exist, off-grid is ok.
min. space between two SDNW
Layout
Rule (um)
0.86
1.40
2.40
3.40
4.40
0.60
1.50
2.00
1.40
2.40
3.40
4.40
2.90
0.00
0.00
0.50
1.00
1.50
20 of 224
DBH CONFIDENTIAL
24W24a
24S24a/b/c/d
24S24e
24X22a
24O22a
24S2a/b/c/d/e/f
NWELL
24S1a/b/c/d
PWELL
DNW
SDNW
ISO_V30
24S1d
21 of 224
DBH CONFIDENTIAL
5.SD-PWELL (SDPW; rule# 23)
Rule No.
23W23a
23Ra
23S23a
23S23b
23S23c
23S23d
23S23e
23S2a
23S2b
23S2c
23S2d
23S1a
23S1b
23S1c
23S1d
23S1e
23S1f
23S24a
23Na
23Rb
23Rc
23Rd
23Ga
Description
Conditions
min. width of a SDPW
To use SDPW as different node, at least one SDPW is enclosed by DNW and
surrounded by NW or SDNW.
min. space between two SDPW
Different node (V2, V5, V7)
min. space between two SDPW
Different node (V12)
Different node (V20)
min. space between two SDPW
Exception; pch_des_ftr_20v
Different node (V30, including
min. space between two SDPW
no voltage tag)
min. space between two SDPW
Same node
min. space of SDPW to NW
In V2, V5, V7, ISO_V7
min. space of SDPW to NW
In V12
min. space of SDPW to NW
In V20
In V30, ISO_V30, including no
voltage tag
min. space of SDPW to NW
Exception; ESD components
with ESDMY, Inner edge of NW
for iso-ring in ISO_V30
min. space of SDPW to PW
Different node (V2, V5, V7)
min. space of SDPW to PW
Different node (V12)
min. space of SDPW to PW
Different node (V20)
min. space of SDPW to PW
Different node (V30)
min. space of SDPW to PW
Different node (no voltage tag)
Same node
min. space of SDPW to PW
Overlap ok, Coincident ok,
Butting ok
min. space of SDPW to SDNW
Overlap not ok
Space rule between Layers with different voltage tag obey rule with higher
voltage tag
SDPW and SDNW must not be overlapped or coincident.
SDPW and NW must not be overlapped or coincident.
SDPW and PDT must not be overlapped or coincident.
Drawn SDPW must conform to a 0.005um
Exception: If NOGRID layer
on-grid rule
exist, off-grid is ok.
Layout
Rule (um)
0.86
1.40
2.40
3.40
4.40
0.60
0.00
0.50
1.00
1.50
1.40
2.40
3.40
4.40
2.90
0.00
0.00
22 of 224
DBH CONFIDENTIAL
23W23a
23S23a/b/c/d
23S23e
23S24a
NWELL
PWELL
SDNW
23S2a/b/c/d
23S1a/b/c/d/e/f
SDPW
DNW
ISO_V30
23S2d
23 of 224
DBH CONFIDENTIAL
6.NDT (NDT; rule# 100)
Rule No.
100W100a
100S100a
100S100b
100S2a
100S1a
100S22a
100S24a
100S23a
100Ra
100Rb
100Rc
100Rd
100Ga
Description
Conditions
min. width of NDT
min. space of two NDT
Different node
min. space of two NDT
Same node
min. space of NDT to NW
Different node
min. space of NDT to PW
min. space of NDT to DNW
Different node
min. space of NDT to SDNW
Different node
min. space of NDT to SDPW
NDT should not be used for resistors.
NDT and PW must not be overlapped or coincident.
NDT and SDPW must not be overlapped or coincident.
NDT and PDT must not be overlapped or coincident.
Drawn NDT must conform to a 0.005um onException: If NOGRID layer exist,
grid rule
off-grid is ok.
Layout
Rule (um)
0.80
6.00
0.80
4.40
2.00
5.90
4.40
2.00
100W100a
NWELL
100S100b
100S1a
PWELL
SDNW
100S100a
SDPW
100S2a
DNW
NDT
100S24a
100S23a
100S22a
24 of 224
DBH CONFIDENTIAL
7.DWELL (DWELL; rule# 102)
Layout
Rule (um)
Rule No.
Description
Conditions
102W102a
min. width of DWELL
Exception: DUMDWELL,
All nch_ldm devices
1.28
All nch_ldm devices
1.28
All nch_ldm devices
1.28
All nch_ldm devices
0.48
All nch_ldm devices
0.55 ≤ #
≤ 0.58
102W102b
102W102c
102W102d
min./max. width of DWELL (straight center section
of finger)
min./max. width of DUMDWELL
min./max. width of a DWELL (edge of finger end,
in L-direction)
102W102e
min./max. width of a DWELL (for 45deg. edges)
102S102a
min. space of two DWELL
102S102b
102S2a
102S1a
max. space between DWELL and DUMDWELL
min. space of DWELL to NW
min. space of DWELL to PW
102S24a
min. space of DWELL to SDNW
102S23a
102S100a
23E102a
102Ra
102Rb
102Rc
102Rd
102Re
102Rf
102Rg
102Rh
102Ga
Different node, square
corner
All nch_ldm outer fingers
Different node
Exception: nch_ldmls_20v,
nch_ldmls_24v,
nch_ldmls_30v,
nch_ldmhs_18v
Different node
min. space of DWELL to SDPW
min. space of DUMDWELL to NDT
min. enclosure of DUMDWELL in P-SUB or ISO PSUB by SDPW
DUMDWELL must be enclosed by SDPW
45-degree segments must be used in finger ends for DWELL
DUMDWELL height (in W direction) must be equal to the DWELL height
DUMDWELL in ISO P-SUB must be connected to DWELL body by PDIFF
45-degree segments must not be used in common area of DIFF and DWELL
DWELL and NW must not be overlapped or coincident.
DWELL and SDNW must not be overlapped or coincident.
DWELL and NDT must not be overlapped or coincident.
Drawn DWELL must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
5.20
7.00
2.00
4.70
2.00
4.70
2.36
0.36
25 of 224
DBH CONFIDENTIAL
102W102a/b
NWELL
PWELL
SDNW
102S102a/b
SDPW
102S96a
102S24a
NDT
102S100a
DWELL
102S1a
102S2a
102S23a
26 of 224
DBH CONFIDENTIAL
8.DIFFUSION (DIFF; rule# 3)
Rule No.
3W3a
3W3b
3W3c
3S3a
3S3b
3S3c
Description
min. width of a DIFF to define the width of
NMOS/PMOS
min. width of a DIFF to define the width of
NMOS/PMOS
min. width of a DIFF for interconnect
min. space between two DIFF (NDIFF to
NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
min. space between two DIFF (NDIFF to
NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
min. space of NDIFF to PDIFF for butted
diffusion
3E2a
min. enclosure of NDIFF by NW
3E1a
min. enclosure of PDIFF by PW
3E24a
min. enclosure of NDIFF by SDNW
3E24b
min. enclosure of NDIFF by SDNW
3E24c
min. enclosure of NDIFF by SDNW
3E23a
min. enclosure of PDIFF by SDPW
3E23b
min. enclosure of PDIFF by SDPW
3E23c
min. enclosure of PDIFF by SDPW
3S2a
min. space of NDIFF to NW
Conditions
Layout
Rule (um)
1.8V CMOS
0.22
5.0V CMOS
0.22
Exception; SRAM BLOCK
Outside TGOX50, Exception;
SRAM BLOCK
0.22
Inside TGOX50
0.42
0.28
0.00
Coincident ok in case of
res_nw, Overlap ok in case of
NDIFF enclosed by NW or
SDNW
Overlap ok in case of PDIFF
enclosed by PW or SDPW
Overlap ok in case of NDIFF
enclosed by NW or SDNW, In
V2, V5, V7, ISO_V7, res_pdiff,
dio_psd_sdnw,
res_pdiff_lsr_sdnw
In V12
Exception; nch_dea_12v
In V20, V30, ISO_V30,
including no voltage tag
Exception; nch_dea_20v,
nch_dea_24v, nch_dea_30v,
res_pdiff, res_pdiff_lsr_sdnw,
esd_hv_24v,
dio_psd_sdnw, res_sdnw,
nch_ldmls_20v,
nch_ldmls_24v,
nch_ldmls_30v,
nch_ldmhs_18v
Overlap ok in case of PDIFF
enclosed by PW or SDPW, In
V2,
V5,
V7,
res_ndiff,
dio_nsd_sdpw
In V12
Exception; pch_dea_12v, Psub pickup of npn_v_8v
In V20, V30, including no
voltage tag
Exception; pch_dea_20v,
pch_dea_24v, res_ndiff, ESD
components with ESDMY,
dio_nsd_sdpw, nch_ldmls_20v,
nch_ldmls_24v,
nch_ldmls_30v,
nch_ldmhs_18v,
pch_des_ftr_20v, sealring
NDIFF in PW Exception; SRAM
BLOCK
0.12
0.12
0.12
0.50
1.00
0.12
0.50
1.00
0.43
27 of 224
DBH CONFIDENTIAL
3S2d
3E2c
3E1e
min. space of NDIFF to NW
min. enclosure of PDIFF by NW
min. enclosure of NDIFF by PW
3E24l
min. enclosure of PDIFF by SDNW
3E23i
min. enclosure of NDIFF by SDPW
3S24a
min. space of NDIFF to SDNW
3S24b
min. space of NDIFF to SDNW
3S1a
min. space of PDIFF to PW
3S1c
min. space of PDIFF to PW
3S23a
min. space of PDIFF to SDPW
3S23b
min. space of PDIFF to SDPW
min. space for the POLYGATE to the edge of
butted PDIFF or NDIFF
min. width of an butted NDIFF or PDIFF
min. area of a stand-alone DIFF(um2)
NDIFF and PDIFF areas may touch but never Exception;dio_z_lv, dio_z_mv,
overlap (i.e. intersect)
nch_ee_5p0v
Limit the short side dimension of DIFF
rectangular to no greater than 120um.
min. space between DNW and NDIFF which is
outside a (NW or SDNW) connected to DNW
min. space of common area of SDPW and PW Overlap not ok, Coincident not
to POLYGATE
ok
min. space of common area of SDNW and Overlap not ok, Coincident not
NW to POLYGATE
ok
All DIFF must be enclosed by (NW or PW or SDNW or SDPW or PDT or NDT or
DWELL). (coincident ok, overlap not ok, exception; all nch_ldmos)
All DIFF must be enclosed by (NIMP or PIMP) (exception; all nch_ldmos
devices, esd_hv_pig_7v)
Drawn DIFF must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
3S3d
3W3d
3A3a
3Ra
3Rb
3S22a
3Rc
3Rd
3Re
3Rf
3Ga
NDIFF in SDPW
Exception; SRAM BLOCK
Exception; SRAM BLOCK
Exception;
pch_dea_12v,
pch_dea_20v, pch_dea_24v,
pch_dea_30v, esd_hv_24v
Exception;
nch_dea_12v,
nch_dea_20v, nch_dea_24v,
nch_dea_30v, sealring
NDIFF in SDPW
Exception; nch_dea_12v,
nch_dea_20v, nch_dea_24v,
nch_dea_30v
NDIFF in PW
PDIFF in NW, Exception;
SRAM BLOCK
PDIFF in SDNW
PDIFF in SDNW
Exception; pch_dea_12v,
pch_dea_20v, pch_dea_24v,
ESD components with ESDMY
PDIFF in NW
0.70
0.43
0.43
0.70
0.70
0.70
0.43
0.43
0.70
0.70
0.43
0.32
0.42
0.2025
3.00
0.50
0.50
Note 1: Moat pattern density should be 30~50% within any local area (120 um * 120 um) after dummy generation.
28 of 224
DBH CONFIDENTIAL
3E2c
3E1e
3S1a
3W3d
3W3d
3S3a
3S3d
3S3d
3W3c
3W3c
3S3c
3S3c
3S3a
3W3a
3S3a
3S2a
3S3a
3W3a
3A3a
3A3a
3E2a
3E1a
3E24l
3E23i
3S23a
3W3d
3W3d
3S3b
3S3d
3S24a
3S3d
3W3c
3W3c
3S3c
3S3c
3S3b
3W3b
3S3b
3S3b
3W3b
3A3a
3A3a
3E24a/b/c
3E23a/b/c
NWELL
SDNW
DIFF
NIMP
PWELL
SDPW
POLY
PIMP
DNW
29 of 224
DBH CONFIDENTIAL
3S22a
30 of 224
DBH CONFIDENTIAL
9.Thick Gate Oxide (TGOX50; rule# 111)
Rule No.
Description
Conditions
111W111a
111S111a
min. width of a TGOX50
min. space between two TGOX50
111E3a
min. enclosure of DIFF by TGOX50
111S3a
min. space between DIFF and TGOX50
111S3b
min. space between TGOX50 and 1.8V
transistor POLYGATE
111E3b
min. enclosure of 5.0V transistor POLYGATE
by TGOX50
111Ga
Drawn TGOX50 must conform to a 0.005um
on-grid rule
Layout
Rule (um)
0.45
0.45
Overlap ok in case of DIFF for
a well pick-up
Exception; DIFF for a well pickup
1.8V CMOS
Check not into field direction
but into active direction
5.0V CMOS
Check not into field direction
but into active direction
Exception: If NOGRID layer
exist, off-grid is ok.
0.32
0.32
0.40
0.40
NWELL
111E3a
111S3a
PWELL
DNW
111S3b
111E3b
SDNW
SDPW
DIFF
111S111a
111W111a
TGOX50
POLY
NIMP
PIMP
31 of 224
DBH CONFIDENTIAL
10. POLY (POLY; rule# 6)
Rule No.
Description
6W6a
min. width of a POLY
6W6b
min. width of a POLY
6W6c
min. width of a POLY
6W6d
6W6e
min. width of a POLY
min. width of a POLY
6W6f
min. width of a POLY
6W6g
min. width of a POLY
min. space between two POLY on DIFF with
contacts in the spacing
min. space between two POLY on DIFF
without contacts in the spacing
min. space between two POLY on field oxide
area.
min. space between DIFF and POLY on field
oxide
min. extension from DIFF to related POLY
inside DIFF
6S6a
6S6b
6S6c
6S3a
6X3a
6X3b
6Ra
6Rb
6Re
6Ga
min. extension of a POLY beyond DIFF into
field oxide (ENDCAP)
Conditions
Interconnect , Exception;
SRAM BLOCK
1.8V NMOS gate length
1.8V NMOS gate length at 45’
bent
5.0V NMOS gate length
1.8V PMOS gate length
1.8V PMOS gate length at 45’
bent
5.0V PMOS gate length
Layout
Rule (um)
0.18
0.18
0.21
0.50
0.18
0.21
0.50
0.375
0.25
Exception; SRAM BLOCK
0.25
Exception; SRAM BLOCK
0.10
Exception; SRAM BLOCK
0.32
Exception; SRAM BLOCK,
nch_ldmls_20v,
nch_ldmhs_18v
0.22
The 90degree angle is not allowed for
Exception; nch_ee_5p0v
POLYGATE in DIFF
The 45degree POLY is not allowed to cross a DIFF edge.
Drawn POLY pattern density must be more than 12%.
Drawn POLY must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
Note : Dummy Poly will be inserted into customer layout to guarantee uniform poly density over chip. Generating
2
Poly dummy( Ex: a group of in-active poly lines) over large area( > 100um ) by customer can cause the large field
area and hinder dummy diffusion generation. DRC check will be applied to this restriction rule.
32 of 224
DBH CONFIDENTIAL
6X3b
6S3a
6W6b/e
6W6d/g
6S6b
6W6c/f
6S6a
6X3a
6S3a
6S6c
6S6a
6W6a
Not allowed.
DIFF
TGOX50
Not allowed.
POLY
CONT
33 of 224
DBH CONFIDENTIAL
11. N+ S/D Implant (NIMP; rule# 8)
Rule No.
Description
8W8a
min. width of NIMP
8S8a
min. space between two NIMP
8S3a
8S3b
8S6a
8S6b
8O3a
8E3a
8E3b
8S3c
8E3c
8X6a
8A8a
min. space between NIMP and PDIFF (inside
NW or SDNW)
min. space between NIMP and PDIFF
(outside NW or SDNW)
min. space between butted DIFF NIMP and
PCH POLYGATE
min. space between butted DIFF NIMP edge
and NCH POLYGATE
min. overlap from NIMP edge to NDIFF
min. enclosure of NDIFF (in PW or SDPW) by
NIMP
min. enclosure of (NW or SDNW) pick-up
NDIFF by NIMP
min. space between NDIFF and butted PDIFF
(inside PW or SDPW)
min. enclosure of the edge of a butted
NDIFF/PDIFF by NIMP
min. extension of NIMP beyond a POLY as a
resistor
min. area of NIMP (um2)
8Ra
NIMP overlapped with PIMP is not allowed
8Ga
Drawn NIMP must conform to a 0.005um ongrid rule
Conditions
Layout Rule
(um)
0.44
Merge if the space is less than
0.44um
0.44
exception; nch_ee_5p0v
0.26
Non-butted (PW or SDPW)
pick-up PDIFF
0.10
0.32
0.32
0.23
exception; in case of butting
with PDIFF, dio_z_lv,
dio_z_mv, esd_hv_pig_7v
Coincident ok in case of
butting with PDIFF
0.18
0.02
0.00
0.00
0.18
0.3844
exception; nch_ee_5p0v,
dio_z_lv, dio_z_mv
Exception: If NOGRID layer
exist, off-grid is ok.
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DBH CONFIDENTIAL
8W8a
8S3b
8O3a
8E3b
8S6b
8S6a
8S3a
8X6a
8E3a
8S8a
8E3c
8S3c
8E3b
SDNW
SDPW
8W8a
Field Poly
Resistor
DIFF
POLY
NIMP
DNW
PIMP
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DBH CONFIDENTIAL
12. P+ S/D Implant (PIMP; rule# 7)
Rule No.
Description
7W7a
min. width of PIMP
7S7a
min. space between two PIMP
7A7a
min. space between PIMP and NDIFF (inside
PW or SDPW)
min. space between PIMP and NDIFF
(outside PW or SDPW)
min. space between butted DIFF PIMP and
NCH POLYGATE
min. space butted DIFF PIMP edge and PCH
POLYGATE
min. overlap from a PIMP edge to an PDIFF
min. enclosure of PDIFF (in NW or SDNW) by
PIMP
min. enclosure of (PW or SDPW) pick-up
PDIFF by PIMP
min. space between PDIFF and butted NDIFF
(inside NW or SDNW)
min. enclosure of the edge of a butted
NDIFF/PDIFF by PIMP
min. extension of PIMP beyond a POLY as a
resistor
min. area of PIMP (um2)
7Ra
PIMP overlapped with NIMP is not allowed.
7Ga
Drawn PIMP must conform to a 0.005um ongrid rule
7S3a
7S3b
7S6a
7S6b
7O3a
7E3a
7E3b
7S3c
7E3c
7X6a
Conditions
Merge if the space is less than
0.44um
Layout Rule
(um)
0.44
0.44
0.26
Non-butted (NW or SDNW) pickup NDIFF
0.10
0.32
0.32
0.23
exception; in case of butting with
NDIFF, nch_ee_5p0v
Coincident ok in case of butting
with NDIFF
0.18
0.02
0.00
0.00
0.18
0.3844
exception; nch_ee_5p0v,
dio_z_lv, dio_z_mv
Exception: If NOGRID layer
exist, off-grid is ok.
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DBH CONFIDENTIAL
7W7a
7S3b
7E3b
7O3a
7S6a
7S6b
7X6a
7S3a
7E3a
7S7a
7E3c
7S3c
7E3b
Field Poly
Resistor
7W7a
SDNW
SDPW
DIFF
POLY
NIMP
DNW
PIMP
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DBH CONFIDENTIAL
13. High Resistor Implant (HRI; rule# 90)
Layout Rule
(um)
0.44
0.42
Condition
Rule No.
Description
90W90a
90W90b
min. width of HRI
min. width of HRI POLY Resistor
90S90a
min. space between two HRI.
90S3a
90S8a
90S7a
90S6a
90E6a
90A90a
90Ra
90Rb
min. space between a HRI and a DIFF
min. space between HRI and NIMP
min. space between HRI and PIMP
min. space between a HRI and POLY
min. enclosure of POLY resistor by HRI
min. area of a HRI (um2)
Overlap of a NIMP and a HRI on a DIFF region is not allowed
Overlap of a NIMP and a HRI on the same POLY is not allowed
Drawn HRI must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
90Ga
Merge if the space is less
than 0.44um.
0.44
0.50
0.50
0.50
2.00
0.26
0.3844
90S8a
90S7a
90E6a
90W90b
90S3a
90S90a
90S6a
90W90a
HRI
NIMP
PIMP
DIFF
POLY
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DBH CONFIDENTIAL
14. SALICIDE BLOCK (SAB; rule# 47)
Rule No.
Description
47W47a
47S47a
47S3a
47X3a
min. width of SAB
min. space between two SAB
min. space between SAB and DIFF
min. extension of SAB to related DIFF
47S6a
min. space between SAB and POLY
47X6a
min. extension of SAB to related Field POLY
47S9a
min. space between SAB and CONT
47X3b
47W47b
min. extension of DIFF to SAB
min. width of POLY resistor
47A47a
min. area of SAB (um2)
47Ra
47Ga
Conditions
Exception; esd_hv_24v
Exception; nch_pp_1p8v_4t,
nch_pp_5p0v_4t
Exception; esd_hv_24v
Exception; nch_ldmls_7v,
nch_ldmhs_7v, nch_ldmls_12v,
nch_ldmhs_12v
Layout
Rule (um)
0.43
0.43
0.22
0.22
0.45
0.22
0.22
0.22
0.42
Exception; nch_dea_7v,
nch_dea_iso_7v, pch_dea_7v,
nch_dea_12v, pch_dea_12v
CONT to pick up poly resistor should be a single column array.
Drawn SAB must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
2.00
47X3b
47S3a
47W47a
47X3a
47S47a
47S9a
47S6a
47S6a
47X6a
47S9a
CONT to pick up
poly resistor should
be a single column array
47W47b
POLY
SAB
NIMP
PIMP
CONT
DIFF
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DBH CONFIDENTIAL
15. CONTACT (CONT; rule# 9)
Rule No.
Description
9W9a
9S9a
min. & max. size of CONT
min. space between two CONT
9S9b
9S6a
9S3a
9E3a
9E6a
9E3b
9S3b
9Ra
9Rb
9Rc
9Rd
min. space between two CONT in a contact
array with both row and column numbers
equal to or larger than 4.
min. space between CONT on DIFF and
POLYGATE
min. space between CONT on POLY and
DIFF
min. enclosure of DIFF CONT by DIFF
min. enclosure of POLY CONT by POLY
min. enclosure of TAPDIFF CONT by
TAPDIFF
min. space between CONT and TAPDIFF
CONT on POLYGATE is forbidden
CONT must be salicided.
CONT must be enclosed by (DIFF and M1) or
(POLY and M1).
CONT on resistor body of DIFF/POLY/MET1
resistor is not allowed.
9Re
CONT on POLYDIFF is not allowed
9Ga
Drawn CONT must conform to a 0.005um ongrid rule
Conditions
As shown in shaded area, two
contact regions within 0.3um
distance are considered to be
in the same array. (ex. 2X8,
3X3 use 9S9a, and 4X4, 4X8
use 9S9b)
Layout
Rule (um)
0.22
0.25
0.28
0.16
0.20
Exception; SRAM BLOCK
Exception; SRAM BLOCK
0.10
0.10
0.10
0.10
In RESIST, METRES1
Exception: If NOGRID layer
exist, off-grid is ok.
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DBH CONFIDENTIAL
9S9b
Tap
Space <= 0.3um
4x4
9S9a
9S9b
Diode
9W9a
9S3a
Space > 0.3um
9E6a
1x4
9S9a
9S3b
9E3a
9E3b
9S6a
9E3a
CONT
NIMP
9E6a
PIMP
DIFF
POLY
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DBH CONFIDENTIAL
16. METAL-1 (M1; rule# 10)
Rule No.
Description
10W10a
10S10a
min. width of M1
Exception; SRAM BLOCK
min. space between M1 lines
min. space between M1 lines with one or both
M1 line width are greater than 10um
min. enclosure of CONT by M1
Exception; SRAM BLOCK
min. enclosure of CONT by M1 end-of-line
Exception; SRAM BLOCK
region
min. area of M1 (um2)
For CONT located at the 90 degree MET1 corner, at least one side should be
treated as end-of-line.
Drawn M1 pattern density must be more than 30%.
Drawn M1 must conform to a 0.005um on-grid
Exception: If NOGRID layer
rule
exist, off-grid is ok.
10S10b
10E9a
10E9b
10A10a
10Ra
10Rb
10Ga
Conditions
M1 Width =< 10um
Layout
Rule (um)
0.23
0.23
0.60
0.005
0.06
0.2025
10W10a
M1 Width > 10um
10S10a
10E9b
10S10b
10E9a
10A10a
M1LPAD
Metal corner 90degree
VIA1
CONT
M1
10E9b
10E9a
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DBH CONFIDENTIAL
17. VIA 1 (VIA1; rule# 11)
Rule No.
Description
11W11a
11S11a
11E10a
11E10b
min. & max. size of VIA1
min. space between two VIA1
min. enclosure of VIA1 by M1
min. enclosure of VIA1 by M1 end-of-line region
For VIA1 located at the 90 degree MET1 corner, at least one side should be
treated as end-of-line.
VIA1 on resistor body of MET1/MET2 resistor is
In METRES1, METRES2
not allowed.
Drawn VIA1 pattern density must be under 7.5%.
Drawn VIA1 must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
11Ra
11Rb
11Rc
11Ga
Conditions
Layout
Rule (um)
0.26
0.26
0.01
0.06
11E10a
Metal corner 90degree
11W11a
11E10b
11S11a
11E10b
11E10b
M1LPAD
11E10a
M1
VIA1
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DBH CONFIDENTIAL
18. METAL-2 (M2; rule# 12)
Rule No.
Description
12W12a
12S12a
min. width of M2
min. space between M2 lines
min. space between M2 lines with one or both
M2 line width are greater than 10um
min. enclosure of VIA1 by M2
min. enclosure of VIA1 by M2 end-of-line region
min. area of M2 (um2)
For VIA1 located at the 90 degree MET2 corner, at least one side should be
treated as end-of-line.
Drawn M2 (for inter-metal) pattern density must be more than 27%.
Drawn M2 must conform to a 0.005um on-grid
Exception: If NOGRID layer
rule
exist, off-grid is ok.
12S12b
12E11a
12E11b
12A12a
12Ra
12Rb
12Ga
Conditions
Layout
Rule (um)
0.28
0.28
0.60
0.01
0.06
0.2025
12W12a
M2 Width =< 10um
M2 Width > 10um
12S12a
12E11b
12S12b
12E11a
12A12a
M2LPAD
VIA1
Metal corner 90degree
M2
VIA2
12E11b
12E11a
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DBH CONFIDENTIAL
19. VIA2 (VIA2; rule# 13)
Rule No.
Description
13W13a
13S13a
13E12a
13E12b
min. & max. size of VIA2
min. space between two VIA2
min. enclosure of VIA2 by M2
min. enclosure of VIA2 by M2 end-of-line region
For VIA2 located at the 90 degree MET2 corner, at least one side should be
treated as end-of-line.
VIA2 on resistor body of MET2/MET3 resistor is
In METRES2, METRES3
not allowed.
Drawn VIA2 pattern density must be under 7.5%.
Drawn VIA2 must conform to a 0.005um on-grid
Exception: If NOGRID layer
rule
exist, off-grid is ok.
13Ra
13Rb
13Rc
13Ga
Conditions
Layout
Rule (um)
0.26
0.26
0.01
0.06
Metal corner 90degree
13E12b
13S13a
13W13a
13E12b
13E12b
M2LPAD
13E12a
VIA2
M2
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DBH CONFIDENTIAL
20. METAL-3 (M3; rule# 14)
Rule No.
Description
14W14a
14S14a
min. width of M3
min. space between M3 lines
min. space between M3 lines with one or both
M3 line width are greater than 10um
min. enclosure of VIA2 by M3
min. enclosure of VIA2 by M3 end-of-line
region
min. area of M3 (um2)
For VIA2 located at the 90 degree MET3 corner, at least one side should be
treated as end-of-line.
Drawn M3 (for inter-metal) pattern density must be more than 27%.
Drawn M3 must conform to a 0.005um on-grid
Exception: If NOGRID layer
rule
exist, off-grid is ok.
14S14b
14E13a
14E13b
14A14a
14Ra
14Rb
14Ga
Conditions
Layout
Rule (um)
0.28
0.28
0.60
0.01
0.06
0.2025
14W14a
M3 Width =< 10um
M3 Width > 10um
14S14a
14E13b
14S14b
14E13a
14A14a
M3LPAD
Metal corner 90degree
VIA2
M3
14E13b
14E13a
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DBH CONFIDENTIAL
21. VIA3 (VIA3; rule#15)
Rule No.
15W15a
15S15a
15E14a
15E14b
15Ra
15Rb
15Rc
15Ga
Description
Conditions
min. & max. size of VIA3
min. space between two VIA3
min. enclosure of VIA3 by M3
min. enclosure of VIA3 by M3 end-of-line
region
For VIA3 located at the 90 degree MET3 corner, at least one side should be
treated as end-of-line.
VIA3 on resistor body of MET3/MET4 resistor
In METRES3, METRES4
is not allowed.
Drawn VIA3 pattern density must be under 7.5%.
Drawn VIA3 must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
Layout
Rule (um)
0.26
0.26
0.01
0.06
Metal corner 90degree
15E14a
15W15a
15E14b
15S15a
15E14b
15E14b
M3LPAD
15E14a
VIA3
M3
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DBH CONFIDENTIAL
22. METAL-4 (M4; rule#16)
Rule No.
16W16a
16S16a
16S16b
16E15a
16E15b
16A16a
16Ra
16Rb
16Ga
Description
Conditions
min. width of M4
min. space between M4 lines
min. space between M4 lines with one or both
M4 line width are greater than 10um
min. enclosure of VIA3 by M4
min. enclosure of VIA3 by M4 end-of-line region
min. area of M4 (um2)
For VIA3 located at the 90 degree MET4 corner, at least one side should be
treated as end-of-line.
Drawn M4 (for inter-metal) pattern density must be more than 27%.
Drawn M4 must conform to a 0.005um on-grid
Exception: If NOGRID layer
rule
exist, off-grid is ok.
Layout
Rule (um)
0.28
0.28
0.60
0.01
0.06
0.2025
16W16a
M4 Width =< 10um
M4 Width > 10um
16S16a
16E15b
16S16b
16E15a
16A16a
M4LPAD
VIA4
VIA3
Metal corner 90degree
M4
16E15b
16E15a
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DBH CONFIDENTIAL
23. VIA4 (VIA4; rule#17)
Rule No.
17W17a
17S17a
17E16a
17E16b
17Ra
17Rb
17Rc
17Ga
Description
Conditions
min. & max. size of VIA4
min. space between two VIA4
min. enclosure of VIA4 by M4
min. enclosure of VIA4 by M4 end-of-line
region
For VIA4 located at the 90 degree MET4 corner, at least one side should be
treated as end-of-line.
VIA4 on resistor body of MET4/MET5
In METRES4, METRES5
resistor is not allowed.
Drawn VIA4 pattern density must be under 7.5%.
Drawn VIA4 must conform to a 0.005um on- Exception: If NOGRID layer
grid rule
exist, off-grid is ok.
Layout
Rule (um)
0.26
0.26
0.01
0.06
Metal corner 90degree
17E16a
17W17a
17E16b
17S17a
17E16b
17E16b
17E16a
M4LPAD
VIA4
M4
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DBH CONFIDENTIAL
24. METAL-5 (M5; rule#18)
Rule No.
Description
Conditions
min. width of M5
min. space between M5 lines
min. space between M5 lines with one or
both M5 line width are greater than 10um
min. enclosure of VIA4 by M5
min. enclosure of VIA4 by M5 end-of-line
region
Min. area of M5 (um2)
For VIA4 located at the 90 degree MET5 corner, at least one side should be
treated as end-of-line.
Drawn M5 (for inter-metal) pattern density must be more than 27%.
Drawn M5 must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
18W18a
18S18a
18S18b
18E17a
18E17b
18A18a
18Ra
18Rb
18Ga
M5 Width =< 10um
Layout
Rule (um)
0.28
0.28
0.60
0.01
0.06
0.2025
18W18a
18S18a
M5 Width > 10um
18E17b
18S18b
18E17a
18A18a
M5LPAD
VIA5
VIA4
M5
Metal corner 90degree
18E17b
18E17a
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DBH CONFIDENTIAL
25. VIA5 (VIA5; rule#19)
Rule No.
19W19a
19S19a
19E18a
19E18b
19Ra
19Rb
19Rc
19Ga
Description
Conditions
min. & max. size of VIA5
min. space between two VIA5
min. enclosure of VIA5 by M5
min. enclosure of VIA5 by M5 end-of-line
region
For VIA5 located at the 90 degree MET5 corner, at least one side should be
treated as end-of-line.
VIA5 on resistor body of MET5/MET6(top
In METRES5, METRES6
metal) resistor is not allowed.
Drawn VIA5 pattern density must be under 7.5%.
Drawn VIA5 must conform to a 0.005um onException: If NOGRID layer
grid rule
exist, off-grid is ok.
Layout
Rule (um)
0.36
0.35
0.01
0.06
Metal corner 90degree
19E18a
19E18b
19W19a
19S19a
19E18b
19E18b
19E18a
M5LPAD
VIA5
M5
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DBH CONFIDENTIAL
26. Top metal (M6; rule#20)
Rule No.
Description
Conditions
min. width of M6
min. space between M6 lines
min. space between M6 lines with one or both
M6 line width are greater than 10um
min. enclosure of VIA5 by M6
min. enclosure of VIA5 by M6 end-of-line
region
min. area of M6 (um2)
For VIA5 located at the 90 degree MET6 corner, at least one side should be
treated as end-of-line.
Drawn M6 pattern density must be more than 30%.
Drawn M6 must conform to a 0.005um on-grid
Exception: If NOGRID layer
rule
exist, off-grid is ok.
20W20a
20S20a
20S20b
20E19a
20E19b
20A20a
20Ra
20Rb
20Ga
M6 Width =< 10um
Layout
Rule (um)
0.44
0.46
0.60
0.09
0.09
0.5625
20W20a
20S20a
20E19b
M6 Width > 10um
20S20b
20E19a
20A20a
M6LPAD
VIA5
Metal corner 90degree
M6
20E19b
20E19a
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DBH CONFIDENTIAL
Option) Top Thick METAL Option Rule
Rule No.
20W20b
20W20c
20S20c
Description
min. width of M6
min. width of M6
min. space between two M6 lines
min. space between M6 lines with one or both M6
line width are greater than 10um
min. space between two M6 lines at corner
area(45degree).
min. enclosure of VIA5 by M6
min. enclosure of VIA5 by M6
Drawn M6 pattern density must be more than 30%.
20S20d
20S20e
20E19c
20E19d
20Rc
Condition
Scribe seal
Layout Rule (um)
3.1
4.2
2.0
4.0
3.0
0.8
0.59
Scribe seal
<Top Thick Metal Corner Routing Guideline>
Top Thick Metal
<3um
Top Thick Metal
90degree
<3um
3um
45degree
<3um
<3um
NOT allowed

If there are two adjacent metal lines with below 3um space, top thick metal corner should be
bent oblique with min. 3um metal space rule.
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DBH CONFIDENTIAL
27. Protective Overcoat Removal (POR; rule# 21)
27.1 Common design rule
Rule No.
Description
21W21a
21E20a
min. dimension of a POR for bonding pad
min. enclosure of POR by M1~M6
21E20b
min. enclosure of POR by M1~M6
21W21c
21S19a
21S21a
min. & max. width of VIA5
min. space between two VIA5
min. space between two bonding pad
min. space between two POR regions for
bonding pad.
21S21b
21Ra
POR must be enclosed by Top Metal
21Ga
Drawn POR must conform to a 0.005um ongrid rule
Conditions
Only check about top metal
Rule for adopted a polyimide
process ; Only check about top
metal
Layout
Rule (um)
60 X 60
2.00
5.00
0.36
0.35
5.00
9.00
Exception; in case of metal
fuse, sealring
Exception: If NOGRID layer
exist, off-grid is ok.
27.2 Normal PAD design rule
Rule No.
Description
21E19a
21E17a
21W21b
21S17a
21S17b
min. enclosure of VIA1,3,5 by POR
min. enclosure of VIA2,4 by POR
min. & max. width of VIA1~4
min. space between two VIA1~4
min. space between VIA1,3 and VIA2,4
Conditions
Layout
Rule (um)
3.00
3.00
0.26
0.45
0.13
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DBH CONFIDENTIAL
21W21a
21W21b
21S17a
21E20a
21S17a
21E19a
21S19a
21S17b
21E19a
21W21c
21W21b
21S21b
21S21a
21E20a
VIA2, 4
POR
VIA5
VIA1, 3
M1~6
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DBH CONFIDENTIAL
27.3 CUP IO PAD design rule
1. Introduction
As device density and I/O requirements are increased, the size and pitch of pads, subsequently, must be
decreased. Circuit Under Pad(CUP) device allows designers to reduce I/O area and enhance performance. In
case of CUP I/O, the circuit exists under pad area, but is not pad of general I/O. Below figures are structure
comparison between general I/O and CUP I/O.
This design manual provides rules and reference information for the design and layout of integrated circuits
using the Dongbu Hitek(DBHs) 0.18um Analog/BCD processes. These rules and the information in this
document are provided as a supplement to the rules and information for the general purpose logic process.
This document provides rules for the CUP I/O which has top VIA array like a diamond shape.
The cross section is shown below.
[ CUP I/O has top VIA array like a diamond shape ]
2. Layout rules and guidelines
56 of 224
DBH CONFIDENTIAL
2.1 CUP I/O with top VIA array like a diamond shape
Rule No. Description
min. space between pad metal (n) and metal (n), pad
21S21c
metal (n-1) and metal (n-1) (n=4~6)
21S21d
min. space between pad metal (n) and metal (n)
(n=4~6)
Condition
Layout Rule (um)
Overlap ok
0.6
In case of top thick
metal
Overlap ok
4.0
min. enclosure of POR by metal (n) and metal (n-1)
(n=4~6).
min. enclosure of the nearest VIA (n-1) by POR
21E19b
max. enclosure of the nearest VIA (n-1) by POR
21E19c
21W21d min. width of keep out zone of VIA (n-1)
21Rb
POR must be enclosed by CUP_DIA
Coincident ok
min. density of VIA (n-1) inside POR
21Rc
max. density of VIA (n-1) inside POR
21Rd
Note 1) The pad structure must be Top metal(n) / VIA(n-1) / M(n-1) (n≥4).
Note 2) VIAs should form a diamond pattern in the center of passivation window.
Note 3) Allowed Top metal level for CUP
Top Metal Level
Metal-1
Metal-2
Metal-3
Metal-4
Metal-5
PAD
X
X
X
O
O
CUP
Structure
M3-V3-M4
M4-V4-M5
21E20c
2.0
1.0
4.0
25
10%
15%
Metal-6
O
M5-V5-M6
Metal(n) and Metal(n-1)
21E20c
21W21d
21E19b/c
Metal(n)
Metal(n-1)
POR
VIA(n-1)
CUP_DIA
57 of 224
DBH CONFIDENTIAL
28. Block Well for Low VT NMOS (BLKWELL; rule#92)
Rule No.
Description
92W92a
92S92a
92E3a
92E3b
min. width of an BLKWELL
min. space between two BLKWELL
min. enclosure of DIFF by BLKWELL
min. enclosure of DIFF by BLKWELL
min. space of BLKWELL to a nominal DIFF
region
min. space of BLKWELL to a NW edge
min. space of BLKWELL to a SDNW edge
BLKWELL interact DNW is not allowed.
Only one DIFF is allowed in one BLKWELL.
P+ POLYGATE is not allowed in BLKWELL.
A bent POLY is not allowed in BLKWELL.
Drawn BLKWELL must conform to a 0.005um
on-grid rule
92S3a
92S2a
92S24a
92Ra
92Rb
92Rc
92Rd
92Ga
Conditions
In PWELL
In SDPW
Layout
Rule (um)
0.86
0.86
0.30
1.00
0.52
1.66
1.66
Exception: If NOGRID layer
exist, off-grid is ok.
58 of 224
DBH CONFIDENTIAL
92W92a
92S92a
92S2a
92E3a
92S3a
NWELL
PWELL
SDNW
91S24a
92E3b
SDPW
DIFF
POLY
BLKWELL
59 of 224
DBH CONFIDENTIAL
29. MiM Capacitor Top Metal (MTM; rule#87)
Rule No.
Description
87W87a
87W87b
87W87c
87S87a
min. width of MTM as a capacitor top plate
min. width of a dummy MTM in same MN+1 plate
min. width of a dummy MTM in different MN+1 plate
min. space between two MTM as a capacitor top plate
min. space between a dummy MTM and a MTM
regions
min. space between a dummy MN+1 of a capacitor
bottom plate and MN+1 as a capacitor bottom plate
min. enclosure of VIAN+1 by MTM2
min. enclosure of VIAN or VIAN+1 by MN+1 as a
capacitor bottom plate
min. enclosure of MTM by MN+1 as a capacitor bottom
plate
min. space between a VIAN or VIAN+1 and MTM
min. space between two VIAN+1 located upon MTM
min. space between two VIAN+1 located upon MN+1
max. width of a MTM as a capacitor top plate
max. width of a MN+1 as a capacitor bottom plate
A MTM region crosses over an MN+1 is not allowed
VIAN under MTM region is not allowed
For a capacitor larger than 30X30um, please use parallel of smaller capacitor.
Device and metal routing under MTM region are allowed. But designers need
to consider the any possible side-effect like noise coupling if any circuit or
routing is under MIM capacitor. It may be necessary to put the isolation metal
layer under the MIM capacitor bottom plate to prevent the side-effects.
Exception: If
Drawn MTM must conform to a 0.005um on-grid rule
NOGRID layer exist,
off-grid is ok.
87S87b
87S87c
87E19a
87E19b
87E18a
87S19a
87S19b
87S19c
87W87d
87W87e
87Ra
87Rb
87Na
87Nb
87Ga
Condition
Layout Rule
(um)
4.00
0.40
0.40
1.20
0.80
0.80
0.24
0.12
0.40
0.40
2.00
4.00
30.0
35.0
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DBH CONFIDENTIAL
87E19b
87E18a
87W87a
87W87e
87S19c
87S19b
87S19a
87S87a
87E19a
87S19a
Mn+1 Interconnection
Capacitor Dummy1
VIAn+1
MTM2
VIAn
Mn+1
Capacitor Dummy2
87S87b
87S87c
MTM
MTM
87W87b
87W87c
Dummy MTM
Dummy MTM
61 of 224
DBH CONFIDENTIAL
Layout Example for MiM Capacitor
MTOP
VIAN+1
MTM
MN+1
VIAN
MN+1 Interconnection
MN
MN
62 of 224
DBH CONFIDENTIAL
30. Voltage Tag (VTAG; VTAG)
Rule No.
VTAG.Ra
VTAG.Rb
VTAG.Rc
VTAG.Rd
VTAG.Re
VTAG.Rf
VTAG.Rg
Description
V2 Voltage Tag Layer must enclosure all 1.8V
devices.
V5 Voltage Tag Layer must enclosure all 5V
devices.
V7 Voltage Tag Layer must enclosure all 7V
devices.
V12 Voltage Tag Layer must enclosure all 12V
devices.
V20 Voltage Tag Layer must enclosure all 20V
devices.
V30 Voltage Tag Layer must enclosure all
24V/30V devices.
Each Voltage Tag Layer must not enclosure the
others Voltage Tag Layers.
Condition
Layout Rule
(um)
Exception: artisan library
Exception; ISO_V7,
ISO_V30
63 of 224
DBH CONFIDENTIAL
31. DIE SEAL (SEALRING; rule#38)
Rule No.
Description
38W38a
38W38b
38W38c
38S38a
38S38b
38E38a
38E38b
38E38c
38E38d
38W38d
38S38c
38S38d
38E38e
38W38e
38S38e
38S38f
38E38f
38W38f
38S38g
38S38h
38E38g
38W38g
38S38i
38S38j
38E38h
38W38h
38S38k
38S38l
38E38i
38W38i
38S38m
38S38n
38W38k
38E38k
min. width of M1, M2, M3, M4, M5, M6
min. width of PDIFF
min. width of NDIFF
min. space between two Seal DIFF, M1, M2, M3, M4, M5, M6 in scribe line.
min. space of Die TAP to seal NDIFF
min. enclosure of CONT by PDIFF (edge near scribeline)
min. enclosure of CONT by NDIFF (edge near die)
min. enclosure of PDIFF by TAP (edge near scribeline)
min. enclosure of CONT by M1
min. width of CONT
min. space between two CONT hole
min. space CONT trench to hole
min. enclosure of VIA1 by M1/M2
min. width of VIA1
min. space between two VIA1 hole
min. space of VIA1 trench to hole
min. enclosure of VIA2 by M2/M3
min. width of VIA2
min. space between two VIA2 hole
min. space of VIA2 trench to hole
min. enclosure of VIA3 by M3/M4
min. width of VIA3
min. space between two VIA3 hole
min. space of VIA3 trench to hole
min. enclosure of VIA4 by M4/M5
min. width of VIA4
min. space between two VIA4 hole
min. space of VIA4 trench to hole
min. enclosure of VIA5 by M5/M6
min. width of VIA5
min. space between two VIA5 hole
min. space of VIA5 trench to hole
min. width of SDPW
min. enclosure of DIFF by SDPW
Sealring must not overlap to any drawn layers except metal used to make
a GND connection
38Ra
Layout Rule
(um)
4.2
2.1
2.1
2.1
4.00
0.66
0.66
0.28
0.66
0.22
0.78
2.44
0.64
0.26
0.74
2.4
0.64
0.26
0.74
2.4
0.64
0.26
0.74
2.4
0.64
0.26
0.74
2.4
0.59
0.36
0.64
2.3
6.2
1.0
64 of 224
DBH CONFIDENTIAL
Top View
38E38b/d/e~i
38S38d/h/l
38E38a/d/f/h
38S38f/j/n
38E38e/g/i
38W38a
38S38e/i/m
38W38d~i
38W38e/g/i
CT, VIA2, VIA4
38S38c/g/k
M1~6
VIA1, VIA3, VIA5
38W38d/f/h
38W38a
POR trench is automatically
generated during frame preparation
Cross sectional View
POR Trench
2um
Top Metal
Hole
Trench
Metal-5
Main Die
Scribe line
Metal-4
38S38b
Metal-3
38S38a
Metal-2
Metal-1
38E38c
NDIFF
38W38c
PDIFF
38W38b
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DBH CONFIDENTIAL
Scribe Seal/Line Requirements
1. CONT, VIA1, VIA2, VIA3, VIA4, VIA5 each contain one continuous unbroken line and one parallel linear array
holes at the specified with and space. The continuous line is on the “die side” of the seal; the linear array of
holes is on the “scribe side” of the seal. CONT, VIA2, VIA4 are superposed and VIA1, VIA3, VIA5 are
superposed. To facilitate tiling of the cell around die of variable perimeters, it is permissible to eliminate a
column of vias.
2. M1, M2, M3, M4, M5, M6 are all drawn at the same width. (4.2um wide on silicon)
3. Scribe seal metal spacing to corresponding scribe line features is 2.1um on silicon
4. Scribe seal metal spacing to any drawn layers in the design database is 4.0um on silicon (excluding metal used
to make the GND connection).
5. PIMP overlaps PDIFF on scribe line side by 0.28um.
6. A substrate connection to ground may be obtained by shorting the scribe seal to metal GND.
7. PIX/PIQ pattern (flip chip only) must not be open over scribe seal.
8. Dummy diffusion must be used in the scribe line.
9. Scribe seals are not shrinkable.
10. POR trench with 2um width on scribe line provides crack suppression during sawing operation.
11. Draw seals at right angle(90deg) at chip corner as below.
Die Seal
Chip Border
66 of 224
DBH CONFIDENTIAL
32. Antenna Effect Prevention rule (ANT; rule# 51)
Rule No.
51Ra
51Rb
51Rc
51Rd
51Re
51Rf
51Na
Description
max. drawn ratio of field poly area to the active POLYGATE area
connected directly to it
max. drawn ratio of field poly perimeter area to the active POLYGATE
area connected directly to it
When the protection diode is not used, the max. ratio of each metal (for
M1 to M6) area to the active POLYGATE area
When the protection diode is not used, the max. ratio of each metal (for
M1 to M6) perimeter area to the active POLYGATE area
max. drawn ratio of CONT area to the active POLYGATE area connected
directly to it
When the protection diode is not used, the max. drawn ratio of VIA area to
the active POLYGATE area connected directly to it
dio_nsd_pw, dio_psd_nw, dio_nsd_sdpw and dio_psd_sdnw are used as
protection diode.
Layout Rule
100
200
100
400
10
20
2
51Nb
When a protection diode with area larger than or equal to 0.203um is
used, the maximum drawn ratio of Via area to the active poly gate area
can be calculated by the following equation :
Ratio = diode area X 88.33 + 75, for single layer
2
51Nc
When a protection diode with area larger than or equal to 0.203um is
used, the maximum ratio of single-layer metal perimeter area to the active
poly gate area can be calculated by the following equation :
for M1, 2, 3, 4 and 5 single layer
Ratio = diode area X 400 + 2200
for M6 alone (not cumulative), use the following equation :
Ratio = diode area X 8000 + 30000
The definition of POLY, M1-M6 perimeter area antenna ratio for each layer is
ratio = 2[(L+W) x t ] / (Wd x Ld)
L : floating metal (field poly) length connected to Gate
W : floating metal (field poly) width connected to Gate
t : Metal (Poly) thickness
Wd : transistor channel width
Ld : transistor channel length
The definition of POLY, M1-M6 area antenna ratio for each layer is
ratio = (L x W) / (Wd x Ld)
L : floating metal (field poly) length connected to Gate
W : floating metal (field poly) width connected to Gate
Wd : transistor channel width
Ld : transistor channel length
The definition of CONT, VIA1~VIA5 area antenna ratio is
ratio = {total contact(Via) area} / (Wd x Ld)
Wd : transistor channel width
Ld : transistor channel length
The thickness of POLY is 2000A.
The thickness of M1 to M5 is 5250A.
The thickness of M6 is 8375A.
The thickness of M6 in case of thick metal option is 27415A.
67 of 224
DBH CONFIDENTIAL
68 of 224
DBH CONFIDENTIAL
33. Current Density Specification
-. Jmax for 10 yrs lifetime guarantee
Jmax (DBHs@105'C)
Structure
Contact_N Moat (0.22 X 0.22)
Contact_N Poly (0.22 X 0.22)
Contact_P Moat (0.22 X 0.22)
Contact_P Poly (0.22 X 0.22)
Via 1_Down (0.26 X 0.26)
Via 1_Up (0.26 X 0.26)
Via 2_Down (0.26 X 0.26)
Via 2_Up (0.26 X 0.26)
Via 3_Down (0.26 X 0.26)
Via 3_Up (0.26 X 0.26)
Via 4_Down (0.26 X 0.26)
Via 4_Up (0.26 X 0.26)
Via 5_Down (0.36 X 0.36)
Via 5_Up (0.36 X 0.36)
Metal 1,2,3,4,5
Thin
Metal 6 (Top)
Thick
Metal 6 (Top)
Jmax (DBHs@125'C)
Jmax (DBHs@150'C)
[A/Cm2]
[mA/Contact]
[mA/Via]
[mA/um]
[A/cm2]
[mA/Contact]
[mA/Via]
[mA/um]
[A/cm2]
[mA/Contact]
[mA/Via]
[mA/um]
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.4E+05
7.7E+05
7.7E+05
7.7E+05
0.36
0.36
0.36
0.36
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.96
0.96
3.47
6.16
20.79
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.0E+05
4.3E+05
4.3E+05
4.3E+05
0.19
0.19
0.19
0.19
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.52
0.52
1.94
3.44
11.61
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
1.9E+05
2.3E+05
2.3E+05
2.3E+05
0.09
0.09
0.09
0.09
0.13
0.13
0.13
0.13
0.13
0.13
0.13
0.13
0.25
0.25
1.03
1.82
6.16
69 of 224
DBH CONFIDENTIAL
34. Metal Stress Relief (METAL SLOT; MS)
Rule No.
MS.Ra
MS.Rb
MS.Wa
MS.Wb
MS.La
MS.Sa
MS.Sb
MS.Rc
MS.Ga
MS.Gb
MS.Gc
MS.Rd
MS.Wc
MS.Re
MS.Rf
Layout Rule
(um)
Description
All Metal layers must follow this rule.
Only bonding pad areas are excepted
Maximum metal width without slotting
Minimum width of an open slot
Minimum width of a metal line which is connected to the wide metal line.
Slot is not allowed to be placed opposite this metal
Minimum length of an open slot
Minimum space between any two parallel open slots
Minimum space between any two slots in a coaxial line
All slots should be positioned parallel with the direction of current flow on
the metal
Non coincident slots in neighbor layers (M1-M2, M2-M3, M3-M4, M4-M5,
M5-M6)
Minimum offset between two slots in neighbor layers
Minimum offset between any open slot to the inner metal edge
Minimum offset between any open slot to the outer metal edge
Slots in the same layer should be staggered
Maximum width of open slot
Metal slotting rule doesn’t apply to metal with hole density beyond 30%.
Metal slotting rule doesn’t apply to metal with hole beyond 10um x 10um
and its width under 35um.
35
2.0
10.0
20.0
10.0
10.0
2.0
10.0
10.0
6
MS.Gc
MS.Sb
MS.Sa
MS.Wa
MS.La
MS.Gb
MS.Wb
Slot of (N) layer
MS.Ga
Slot of (N-1) layer
70 of 224
DBH CONFIDENTIAL
Option) Thick METAL Slotting guideline (Recommendation)
Rule No.
MS.Wd
MS.We
MS.Lb
MS.Sc
MS.Sd
MS.Gd
MS.Ge
MS.Rg
MS.Rh
MS.Ri
Description
Condition
Layout Rule (um)
min. width of open slot
Thick Top Metal
4.0
max. width of open slot
Thick Top Metal
12.0
min. length of open slot
Thick Top Metal
40.0
min. space between any two parallel open slots
Thick Top Metal
40.0
min. space between any two slots in a coaxial line
Thick Top Metal
40.0
Non coincident slotting in neighbor layers (M1-M2,
M2-M3, M3-M4, M4-M5, M5-M6)
Thick Top Metal
4.0
Minimum offset between two slots in neighbor layers
Minimum offset between any open slot to the metal
Thick Top Metal
40.0
edge
min. metal width without slotting
Thick Top Metal
80.0
Metal slotting rule doesn’t apply to metal with hole density beyond 30%.
Metal slotting rule doesn’t apply to metal with hole beyond 10um x 10um and
its width under 80um.
71 of 224
DBH CONFIDENTIAL
35. Chip Corner, Dummy Pads, Power line Rules (CDP; CDP)
Rule No.
Description
CDP.Ra
The wide metal is defined as being > 30um wide.
There must be power line of wide metal line around the corner in Top metal
layer
For large chip( ≥100mm2), Both Metal line and slots must turn 45 degree
between 300um – 400um of the corner
For small chip( <100mm2), Both Metal line and slots must turn 45 degree
between 100um – 200um of the corner
Independent of chip size, the inside edge of metal line corner must be
longer than 15um
Dummy pads should be added in the chip corner as many as possible
Minimum space between two Vias at the same level
Minimum offset between two Vias at the different levels
Minimum offset between two Via4and Via5 at the different levels
Minimum extension of Metal over Via
Minimum & maximum size of Via1~4
Minimum & maximum size of Via5
CDP.Rb
CDP.Rc
CDP.Rd
CDP.Re
CDP.Rf
CDP.Sa
CDP.Oa
CDP.Ob
CDP.Ea
CDP.Da
CDP.Db
Guide Line
CDP.Ga
CDP.Gb
CDP.Gc
Description
Minimum space between two dummy pads
Minimum clearance between seal ring and outer dummy pads edge
Maximum width of dummy pads
Minimum width of dummy pads
Layout Rule
(um)
0.56
0.21
0.14
3.0
0.26X0.26
0.36X0.36
2.0
20
80
10
72 of 224
DBH CONFIDENTIAL
CDP.Gc
Via5
Via 2, 4
Via 1, 3
CDP.Gc
CDP.Gb
CDP.Ea
CDP.Ga
CDP.G.1
CDP.Ea
CDP.Gb
CDP.Oa
Seal ring
CDP.Sa
CDP.Sa
CDP.Ob
CDP.Sa
73 of 224
DBH CONFIDENTIAL
36. Layout Guideline for Latch-Up Prevention (LU; LU)
This is layout guideline for latch-up prevention
Rule No.
Description
Layout Rule
LU.a
For I/O Buffers and ESD devices, a double guard ring structure should be
inserted in between NMOS’s and PMOS’s, as shown in Fig 37-1.
LU.b
For I/O Buffers and ESD devices, the minimum spacing between NMOS
and PMOS. Exception; esd_hv_pig_7v
15
LU.c
For I/O and internal circuits, the maximum distance from any point inside
Source/Drain DIFF area to the nearest pickup DIFF in the same (NWELL
or SDNW) or (PWELL or SDPW). Exception; ESD components with
ESDMY
30
LU.d
A guard ring structure with SDNW pseudo-collector and P+ pickup should
be inserted in between I/O buffer and internal circuit area.(Fig 37-2)
LU.e
The minimum spacing between I/O buffer and internal circuit area.
LU.f
Any hot DIFF area connecting to I/O PAD should be surrounded by double
guard ring.
50
74 of 224
DBH CONFIDENTIAL
VDD
VSS
Anode
P+
Cathode
LU.b ＞ 15um
P+
N+
N+
P+
SDNW
SDPW
P+ N+
N+
SDPW
SDNW
Fig. 37-1
POLY
POLY
Active
Active
LU.c
POLY
Active
LU.c
LU.c
pick-up
Double Guard Ring
PAD
I/O Cell
Core Region
LU.e
Fig. 37-2
75 of 224
DBH CONFIDENTIAL
37. Dummy Layer Guideline and Generation Rule
The pattern density difference over chip causes topology height variation, reduces process margin and lowers
the production yield. To make pattern density of non-active area similar to the pattern density of major active
operation area of chip, Dongbu Hitek can insert dummy pattern to non-active area of Moat, Poly, and all level of
Metal layer.
1. Minimum design rule of each layer
1.1 Active Layer
Dummy Layer
Feature Size[um]
Pitch[um]
Remark
Active
1.5 x 1.5
2.5
Square, No breakdown
Distance to Layers
PDT, NDT
DWELL
SDNW, SDPW Edge
NWELL, PWELL Edge
PCHSTBLK Edge
PCHST Edge
Active (DIFF)
Poly
FG
Fuse
NWRES
RESIST
DUMBLK(diff), DUMBLK(all)
Boundary
Rule [um]
4
3
1.5
0.7
1.5
1.5
0.7
0.3
0.3
0.0
5.0
1.5
0.0
5.0
Remark
Extracted layer
Floating Poly of E2PROM
Note) All upper rules are based on drawing layers except PCHST (it is extracted layer)
76 of 224
DBH CONFIDENTIAL
1.2 Poly Layer
Dummy Layer
Feature Size[um]
Pitch[um]
Remark
Poly
2.1 x 0.5
2.5
Cross bar, No breakdown
Distance to Layers
PDT, NDT
DWELL
Active (DIFF)
Active Filler
SDNW, SDPW Edge
NWELL, PWELL Edge
PCHSTBLK Edge
PCHST Edge
Poly
FG
NWRES
RESIST
Fuse
DUMBLK(poly), DUMBLK(all)
Boundary
Rule [um]
4
3
0.7
0.2
1.5
0.7
1.5
1.5
0.8
0.8
5.0
1.5
2.0
0.0
Remark
Extracted layer
Floating Poly of E2PROM
5.0
Note) All upper rules are based on drawing layers except PCHST (it is extracted layer)
77 of 224
DBH CONFIDENTIAL
1.3 Metal Layer
Dummy Layer
Feature
Size[um]
Pitch[um]
Remark
Metal_Thin
6×1.8
12 / 6
Dummy metal n layer cannot be overlap
dummy metal n+1 or n-1 layer.
Metal_Thick
10 X 5
15 / 10
See the Note.
Distance to Layers
Metal layer
MTM
POR, Fuse, FUSOR
DUMMETBLK, DUMBLK(all),
DUMBLK(metx)
Boundary
Rule [um]
3.0
5.0
5.0
0.0
Remark
x=1,2,3,4,5,6
2.0
Note> Fundamentally thick metal dummy is not generated in main DB. But in some cases, thin and
thick top metal may exist in the same DB such like MPW or customer’s own shuttle. In this case
thick dummy is NOT generated in the test chip(s) with THICK top metal but thick metal dummy IS
generated in the test chip(s) with THIN metal.
<MPW>
<Drawing>
Thick
Top
Metal
drawing
Thin Top
Metal
drawing
Thin Top
Metal
drawing
Thin Top
Metal
drawing
<Dummy>
NO
DUMMY
Thick
DUMMY
Thick
DUMMY
Thick
DUMMY
78 of 224
DBH CONFIDENTIAL
1.4 Recommended Pattern Density in chip level
Layer
Pattern Density
Remark
Active
30% ~ 50%
After Dummy Generation in Local Area( < 14400um )
Poly
20% ~ 27%
After dummy generation in chip level
Metal
20% ~ 50%
After dummy generation in chip level
2
1.5 Example
6um
6um
Thick Top Metal
Filler
79 of 224
DBH CONFIDENTIAL
4. Component Design Rule
1. CMOS
1.1 5.0V Standard VT NMOS (nch_svt_5p0v)
Rule No.
Description of key design rule
min. width of a DIFF to define the width of NMOS/PMOS
min. width of a POLY to define the gate length of 5.0V NMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(Inside TGOX50)
Butted backgate is allowed.
min. enclosure of NDIFF by SDPW
min. extension of a POLY beyond DIFF into field oxide (ENDCAP)
min. enclosure of PDIFF by SDPW (in V2,V5, V7)
min. enclosure of NDIFF (in PW or SDPW) by NIMP
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
min. enclosure of DIFF by TGOX50
3W3b
6W6d
3S3b
3Na
3E23i
6X3b
3E23a
8E3a
7E3b
111E3a
Layout Rule
(um)
0.22
0.50
0.42
0.70
0.22
0.12
0.18
0.02
0.32
SDPW
POLY
111E3a
8E3a
7E3b
6W6d
DIFF
NIMP
3W3b
3S3b
PIMP
CONT
3E23a
3E23i
6X3b
TGOX50
Backgate
Source/Drain
Source/Drain
NDIFF
PDIFF
MET1
PMD
STI
80 of 224
DBH CONFIDENTIAL
1.2 5.0V Standard VT PMOS (pch_svt_5p0v)
Rule No.
3W3b
6W6g
3S3b
3Na
3E24l
6X3b
3E24a
7E3a
8E3b
111E3a
Layout Rule
(um)
0.22
0.50
Description of key design rule
min. width of a DIFF to define the width of NMOS/PMOS
min. width of a POLY to define the gate length of 5.0V PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(Inside TGOX50)
Butted backgate is allowed.
min. enclosure of PDIFF by SDNW
min. extension of a POLY beyond DIFF into field oxide (ENDCAP)
min. enclosure of NDIFF by SDNW (In V2, V5, V7, ISO_V7)
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
min. enclosure of DIFF by TGOX50
0.42
0.70
0.22
0.12
0.18
0.02
0.32
SDNW
111E3a
7E3a
8E3b
POLY
DIFF
6W6g
3W3b
3S3b
NIMP
PIMP
3E24a
3E24l
6X3b
CONT
TGOX50
Backgate
Source/Drain
Source/Drain
NDIFF
PDIFF
MET1
PMD
STI
81 of 224
DBH CONFIDENTIAL
1.3 5.0V Low VT NMOS (nch_lvt_5p0v)
Rule No.
Description of key design rule
3W3g
6W6i
92S3a
6X3c
92E3b
92E23a
min. width of a DIFF to define the width of 5.0V Low VT NMOS
min. width of a POLY to define the gate length of 5.0V low VT NMOS
min. space of BLKWELL to a nominal DIFF region
min. extension of a POLY beyond DIFF in BLKWELL into field oxide (end cap)
min. enclosure of DIFF by BLKWELL
min. enclosure of BLKWELL by SDPW
Layout Rule
(um)
3.00
1.20
0.52
0.35
1.00
1.66
BLKWELL
SDPW
POLY
6W6i
DIFF
3W3g
92S3a
NIMP
92E3b
6X3c
PIMP
CONT
92E23a
TGOX50
Backgate
Source/Drain
Source/Drain
NDIFF
PDIFF
MET1
PMD
STI
P-sub (P-type)
P-sub
82 of 224
DBH CONFIDENTIAL
1.4 5.0V Isolated Standard VT NMOS (nch_svt_iso_5p0v)
Rule No.
3W3b
6W6d
3S3b
3Na
24X22a
24O22a
Description of key design rule
min. width of a DIFF to define the width of NMOS/PMOS
min. width of a POLY to define the gate length of 5.0V NMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(Inside TGOX50)
Butted backgate is allowed.
min. extension of SDNW beyond DNW
min. overlap of DNW to SDNW
Layout Rule
(um)
0.22
0.50
0.42
1.50
2.00
83 of 224
DBH CONFIDENTIAL
SDNW
POLY
DIFF
NIMP
24O22a
PIMP
CONT
24X22a
SDPW
DNW
TGOX50
Iso_ring
Backgate
Source/Drain
Source/Drain
Iso_ring
SDPW (P-type)
SDNW (N-type)
SDNW (N-type)
DNW (N-type)
NDIFF
PDIFF
MET1
PMD
STI
84 of 224
DBH CONFIDENTIAL
1.5 5.0V Isolated Standard VT PMOS (pch_svt_iso_5p0v)
Rule No.
3W3b
6W6g
3S3b
3Na
24X22a
2Nb
Description of key design rule
min. width of a DIFF to define the width of NMOS/PMOS
min. width of a POLY to define the gate length of 5.0V PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(Inside TGOX50)
Butted backgate is allowed.
min. extension of SDNW beyond DNW
Iso-ring and backgate of Isolated PMOS must have same potential.
Layout Rule
(um)
0.22
0.50
0.42
1.50
85 of 224
DBH CONFIDENTIAL
SDNW
POLY
DIFF
NIMP
PIMP
CONT
24X22a
SDPW
DNW
TGOX50
Iso_ring & Backgate
Source/Drain
Source/Drain
Iso_ring
SDNW (N-type)
DNW (N-type)
NDIFF
PDIFF
MET1
PMD
STI
86 of 224
DBH CONFIDENTIAL
1.6 1.8V Standard VT NMOS (nch_svt_1p8v)
Rule No.
3W3a
6W6b
3S3a
3Na
3E1e
6X3b
3E1a
8E3a
7E3b
Layout Rule
(um)
0.22
0.18
Description of key design rule
min. width of a DIFF to define the width of NMOS/PMOS
min. width of a POLY to define the gate length of 1.8V NMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(outside TGOX50)
Butted backgate is allowed.
min. enclosure of NDIFF by PW
min. extension of a POLY beyond DIFF into field oxide (ENDCAP)
min. enclosure of PDIFF by PW
min. enclosure of NDIFF (in PW or SDPW) by NIMP
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
0.28
0.43
0.22
0.12
0.18
0.02
PWELL
POLY
8E3a
7E3b
DIFF
6W6b
3W3a
3S3a
NIMP
PIMP
3E1a
3E1e
Backgate
Source/Drain
6X3b
CONT
Source/Drain
NDIFF
PDIFF
MET1
PMD
STI
87 of 224
DBH CONFIDENTIAL
1.7 1.8V Standard VT PMOS (pch_svt_1p8v)
Rule No.
3W3a
6W6e
3S3a
3Na
3E2c
6X3b
3E2a
7E3a
8E3b
Layout Rule
(um)
0.22
0.18
Description of key design rule
min. width of a DIFF to define the width of NMOS/PMOS
min. width of a POLY to define the gate length of 1.8V PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(outside TGOX50)
Butted backgate is allowed.
min. enclosure of PDIFF by NW
min. extension of a POLY beyond DIFF into field oxide (ENDCAP)
min. enclosure of NDIFF by NW
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
0.28
0.43
0.22
0.12
0.18
0.02
NWELL
POLY
7E3a
8E3b
6W6e
DIFF
3W3a
3S3a
NIMP
PIMP
3E2c
3E2a
Backgate
Source/Drain
6X3b
CONT
Source/Drain
NDIFF
PDIFF
MET1
PMD
STI
88 of 224
DBH CONFIDENTIAL
1.8 1.8V Low VT NMOS (nch_lvt_1p8v)
Rule No.
Description of key design rule
3W3a
6W6h
92S3a
6X3c
92E3a
92E1a
min. width of a DIFF to define the width of NMOS/PMOS
min. width of a POLY to define the gate length of 1.8V low VT NMOS
min. space of BLKWELL to a nominal DIFF region
min. extension of a POLY beyond DIFF in BLKWELL into field oxide (end cap)
min. enclosure of DIFF by BLKWELL
min. enclosure of BLKWELL by PWELL
Layout Rule
(um)
0.22
0.50
0.52
0.35
0.30
1.66
BLKWELL
PWELL
POLY
6W6h
DIFF
3W3a
92S3a
NIMP
92E3a
PIMP
6X3c
CONT
92E1a
Backgate
Source/Drain
Source/Drain
NDIFF
PDIFF
MET1
PMD
STI
P-SUB
P-sub (P-type)
89 of 224
DBH CONFIDENTIAL
1.9 1.8V Isolated Standard VT NMOS (nch_svt_iso_1p8v)
Rule No.
3W3a
6W6b
3S3a
3Na
22X2a
22O2a
Description of key design rule
min. width of a DIFF to define the width of NMOS/PMOS
min. width of a POLY to define the gate length of 1.8V NMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(outside TGOX50)
Butted backgate is allowed.
min. extension of NW beyond DNW
min. overlap of DNW to NW
Layout Rule
(um)
0.22
0.18
0.28
1.50
2.00
90 of 224
DBH CONFIDENTIAL
NWELL
POLY
DIFF
NIMP
22O2a
PIMP
CONT
22X2a
PWELL
DNW
Iso_ring
Backgate
Source/Drain
Source/Drain
Iso_ring
PWELL (P-type)
NWELL (N-type)
NWELL (N-type)
DNW (N-type)
NDIFF
PDIFF
MET1
PMD
STI
91 of 224
DBH CONFIDENTIAL
1.10 1.8V Isolated Standard VT PMOS (pch_svt_iso_1p8v)
Rule No.
3W3a
6W6e
3S3a
3Na
22X2a
2Nb
Description of key design rule
min. width of a DIFF to define the width of NMOS/PMOS
min. width of a POLY to define the gate length of 1.8V PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(outside TGOX50)
Butted backgate is allowed.
min. extension of NW beyond DNW
Iso-ring and backgate of Isolated PMOS must have same potential.
Layout Rule
(um)
0.22
0.18
0.28
1.50
92 of 224
DBH CONFIDENTIAL
NWELL
POLY
DIFF
NIMP
PIMP
CONT
22X2a
PWELL
DNW
Iso_ring & Backgate
Source/Drain
Source/Drain
Iso_ring
NWELL (N-type)
DNW (N-type)
NDIFF
PDIFF
MET1
PMD
STI
93 of 224
DBH CONFIDENTIAL
2. DE-CMOS
2.1 7V Asymmetric DE-NMOS (nch_dea_7v)
Rule No.
3W3f
3S3b
6W6j
3E23d
3S3t
47O6a
107O6a
47X6b
107X6a
107X3a
3E23l
3S3e
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLY to define the channel length of 7V Asymmetric DE-NMOS
min. enclosure of NDIFF of drain by SDPW
min. space of NDIFF of drain to PDIFF
min. / max. overlap of SAB to POLY
min. / max. overlap of SDBLK to POLY
min. / max. extension of SAB beyond POLY into length direction
min. / max. extension of SDBLK beyond POLY into length direction
min. extension of SDBLK beyond DIFF into field
min. enclosure of PDIFF by SDPW
max. space of NDIFF to PDIFF (backgate)
Layout Rule
(um)
0.42
0.42
0.80
4.13
1.12
0.20
0.18
0.60
0.50
0.18
2.12
25.20
94 of 224
DBH CONFIDENTIAL
SDPW
POLY
DIFF
107X3a
NIMP
107O6a
3S3b
6W6j
PIMP
107X6a
3E23l
CONT
47X6b
3E23d
47O6a
TGOX50
SAB
SDBLK
Backgate
Source
Drain
HVNLDD
NDIFF
P+
HVNLDD
N+
N+
PDIFF
MET1
PMD
SDPW
STI
95 of 224
DBH CONFIDENTIAL
2.2 7V Asymmetric DE-PMOS (pch_dea_7v)
Rule No.
3W3f
3S3b
6W6k
3E24d
47O6a
107O6a
47X6c
107X6b
107X3a
3E24k
3S3u
3S3f
24E105a
23S24l
105Ra
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLY to define the channel length of 7V Asymmetric DE-PMOS
min. enclosure of PDIFF of drain by SDNW
min. / max. overlap of SAB to POLY
min. / max. overlap of SDBLK to POLY
min. / max. extension of SAB beyond POLY into length direction
min. / max. extension of SDBLK beyond POLY into length direction
min. extension of SDBLK beyond DIFF into field
min. enclosure of NDIFF by SDNW
min. space of PDIFF of drain to NDIFF
max. space of PDIFF to NDIFF (backgate)
min. enclosure of SDNW by PCHSTBLK (In ISO_V30)
min. space of SDPW outside ISO_V30 to SDNW inside ISO_V30
ISO_V30 must include PCHSTBLK.
Layout Rule
(um)
0.42
0.42
0.70
4.13
0.20
0.18
0.50
0.40
0.18
2.12
1.12
25.20
1.50
1.50
96 of 224
DBH CONFIDENTIAL
SDNW
POLY
107X3a
DIFF
NIMP
107O6a
3S3b
6W6k
PIMP
107X6b
3E24k
CONT
47X6c
3E24d
47O6a
TGOX50
SAB
SDBLK
Backgate
Source
Drain
HVPLDD
NDIFF
N+
HVPLDD
P+
P+
PDIFF
MET1
PMD
SDNW
STI
97 of 224
DBH CONFIDENTIAL
2.3 7V Isolated Asymmetric DE-NMOS (nch_dea_iso_7v)
Rule No.
3W3f
3S3b
6W6j
3E23d
3S3t
47O6a
107O6a
47X6b
107X6a
107X3a
3E23l
3S3e
3E24k
23S24a
24X22a
24O22a
24E105a
23S24l
105Ra
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLY to define the channel length of 7V Asymmetric DE-NMOS
min. enclosure of NDIFF of drain by SDPW
min. space of NDIFF of drain to PDIFF
min. / max. overlap of SAB to POLY
min. / max. overlap of SDBLK to POLY
min. / max. extension of SAB beyond POLY into length direction
min. / max. extension of SDBLK beyond POLY into length direction
min. extension of SDBLK beyond DIFF into field
min. enclosure of PDIFF by SDPW
max. space of NDIFF to PDIFF (backgate)
min. enclosure of NDIFF by SDNW
min. space of SDPW to SDNW
min. extension of SDNW beyond DNW
min. overlap of DNW to SDNW
min. enclosure of SDNW by PCHSTBLK (In ISO_V30)
min. space of SDPW outside ISO_V30 to SDNW inside ISO_V30
ISO_V30 must include PCHSTBLK.
Layout Rule
(um)
0.42
0.42
0.80
4.13
1.12
0.20
0.18
0.60
0.50
0.18
2.12
25.20
2.12
0.00
1.50
2.00
1.50
1.50
98 of 224
DBH CONFIDENTIAL
DNW
SDPW
24O22a
24X22a
POLY
DIFF
NIMP
3E24k
TGOX50
3E24k
23S24a
SAB
SDBLK
SDNW
Iso-ring
N+
Backgate
P+
Source
Drain
HVNLDD
N+
SDNW
SDPW
N+
Iso-ring
N+
SDNW
DNW
HVNLDD
PDIFF
PMD
NDIFF
MET1
STI
99 of 224
DBH CONFIDENTIAL
2.4 12V Asymmetric DE-NMOS (nch_dea_12v)
Rule No.
3W3f
3S3b
6W6l
3E23k
47O6a
91O6a
47X6b
91X6b
91X3a
6O24a
3X24b
23S24a
23S24b
23S24c
3S24d
3S3e
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLY to define the channel length of 12V Asymmetric DE-NMOS
min. enclosure of PDIFF by SDPW (only check outward direction of device)
min. / max. overlap of SAB to POLY
min. / max. overlap of HRID to POLY
min. / max. extension of SAB beyond POLY into length direction
min. / max. extension of HRID beyond POLY into length direction
min. extension of HRID beyond DIFF into field
min. / max. overlap of SDNW to POLY
min. extension of SDNW not facing gate beyond NDIFF of drain (In V12)
min. space of SDPW to SDNW not facing gate
min. / max. space of SDPW to SDNW facing gate
min. space of SDNW to SDPW outer edge (In V12)
min. space of SDNW to PDIFF (backgate) (In V12)
max. space of NDIFF to PDIFF (backgate)
Layout Rule
(um)
0.42
0.42
1.50
2.12
0.20
0.18
0.60
0.50
0.18
0.60
0.50
0.00
0.00
4.13
1.12
25.20
100 of 224
DBH CONFIDENTIAL
SDNW
SDPW
91X3a
23S24b
23S24a
DIFF
91O6a
3S3b
6W6l
NIMP
91X6b
3E23k
POLY
3E24b
PIMP
47X6b
47O6a
CONT
23S24c
6O24a
TGOX50
SAB
HRID
Backgate
Source
Drain
NDIFF
PDIFF
MET1
P+
N+
N+
PMD
STI
SDPW
SDNW
P-SUB
101 of 224
DBH CONFIDENTIAL
2.5 12V Asymmetric DE-PMOS (pch_dea_12v)
Rule No.
3W3f
3S3b
6W6m
3X23a
3E24m
47O6a
91O6a
47X6b
91X6b
91X3a
6O23a
23S24a
23S24b
23S24d
3S23d
24O22a
24X22a
3S3f
24E105a
23S24l
105Ra
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLY to define the channel length of 12V Asymmetric DE-PMOS
min. extension of SDPW not facing gate beyond PDIFF of drain (V12)
min. enclosure of NDIFF by SDNW (only check outward direction of device)
min. / max. overlap of SAB to POLY
min. / max. overlap of HRID to POLY
min. / max. extension of SAB beyond POLY into length direction
min. / max. extension of HRID beyond POLY into length direction
min. extension of HRID beyond DIFF into field
min. / max. overlap of SDPW to POLY
min. space of SDPW to SDNW not facing gate
min. / max. space of SDPW to SDNW facing gate
min. space of SDPW to SDNW outer edge (In V12)
min. space of SDPW to NDIFF (backgate) (In V12)
min. overlap of DNW to SDNW
min. extension of SDNW beyond DNW
max. space of PDIFF to NDIFF (backgate)
min. enclosure of SDNW by PCHSTBLK (In ISO_V30)
min. space of SDPW outside ISO_V30 to SDNW inside ISO_V30
ISO_V30 must include PCHSTBLK.
Layout Rule
(um)
0.42
0.42
1.20
0.50
2.12
0.20
0.18
0.60
0.50
0.18
0.50
0.00
0.00
4.13
1.12
2.00
1.50
25.20
1.50
1.50
102 of 224
DBH CONFIDENTIAL
SDNW
SDPW
91X3a
23S24b
23S24a
POLY
91O6a
3S3b
6W6m
3E24m
24X22a
91X6b
3X23a
DIFF
NIMP
47X6b
PIMP
47O6a
24O22a
CONT
6O23a
23S24d
TGOX50
SAB
HRID
Backgate
Source
Drain
DNW
NDIFF
N+
P+
P+
PDIFF
MET1
PMD
SDNW
SDPW
STI
DNW
103 of 224
DBH CONFIDENTIAL
2.6 20V Asymmetric DE-NMOS (nch_dea_20v)
Rule No.
3W3f
3S3b
6W6n
3E23k
3S3g
6X3d
3O24a
3E24i
23S24a
23S24b
23S24e
3S24e
3S3e
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLYGATE to define the channel length of 20V/24/30V Asymmetric
DE-NMOS
min. enclosure of PDIFF by SDPW (only check outward direction of device)
min. / max. space of DIFF for channel to DIFF for drain
min. / max. extension of POLY beyond channel active into drain direction
min. / max. overlap of SDNW to channel active
min. enclosure of NDIFF of drain by SDNW not facing gate(V20, V30, no tag)
min. space of SDPW to SDNW not facing gate
min. / max. space of SDPW to SDNW facing gate
min. space of SDNW to SDPW outer edge (In V20)
min. space of SDNW to PDIFF (backgate) (In V20)
max. space of NDIFF to PDIFF (backgate)
Layout Rule
(um)
0.42
0.42
2.50
2.12
1.00
0.50
0.30
1.00
0.00
0.00
4.63
1.62
25.20
104 of 224
DBH CONFIDENTIAL
SDNW
SDPW
23S24b
23S24a
POLY
6X3d
3S3b
DIFF
6W6n
3E23k
3E24i
3S3g
NIMP
3O24a
PIMP
23S24e
CONT
TGOX50
SAB
Backgate
P+
Source
Drain
HRID
N+
N+
NDIFF
PDIFF
MET1
SDPW
SDNW
PMD
P-SUB
STI
105 of 224
DBH CONFIDENTIAL
2.7 20V Asymmetric DE-PMOS (pch_dea_20v)
Rule No.
3W3f
3S3b
6W6o
3E23g
3O23a
3S3h
6X3e
23S24a
23S24b
23S24f
3S23e
24O22a
24X22a
3E24m
3S3f
24E105a
23S24l
105Ra
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLYGATE to define the channel length of 20V/24/30V Asymmetric
DE-PMOS
min. enclosure of PDIFF of drain by SDPW not facing gate (V20, V30, no tag)
min. / max. overlap of SDPW to channel active
min. / max. space of DIFF for channel to DIFF for drain
min. / max. extension of POLY beyond channel active into drain direction
min. space of SDPW to SDNW not facing gate
min. / max. space of SDPW to SDNW facing gate
min. space of SDPW to SDNW outer edge (In V20)
min. space of SDPW to NDIFF (backgate) (In V20)
min. overlap of DNW to SDNW
min. extension of SDNW beyond DNW
min. enclosure of NDIFF by SDNW (only check outward direction of device)
max. space of PDIFF to NDIFF (backgate)
min. enclosure of SDNW by PCHSTBLK (In ISO_V30)
min. space of SDPW outside ISO_V30 to SDNW inside ISO_V30
ISO_V30 must include PCHSTBLK.
Layout Rule
(um)
0.42
0.42
1.50
1.00
0.40
0.60
0.30
0.00
0.00
4.63
1.62
2.00
1.50
2.12
25.20
1.50
1.50
106 of 224
DBH CONFIDENTIAL
SDNW
SDPW
23S24b
23S24a
POLY
6X3e
3S3b
6W6o
24X22a
3E24m
3E23g
3S3h
3O23a
DIFF
NIMP
PIMP
24O22a
CONT
23S24f
TGOX50
DNW
Backgate
Source
Drain
NDIFF
N+
P+
P+
PDIFF
MET1
PMD
SDNW
SDPW
STI
DNW
107 of 224
DBH CONFIDENTIAL
2.8 24V Asymmetric DE-NMOS (nch_dea_24v)
Rule No.
3W3f
3S3b
6W6n
3E23k
3S3i
6X3f
3O24a
3E24i
23S24a
23S24b
23S24g
3S24f
3S3e
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLYGATE to define the channel length of 20V/24/30V Asymmetric
DE-NMOS
min. enclosure of PDIFF by SDPW (only check outward direction of device)
min. / max. space of DIFF for channel to DIFF for drain
min. / max. extension of POLY beyond channel active into drain direction
min. / max. overlap of SDNW to channel active
min. enclosure of NDIFF of drain by SDNW not facing gate(V20, V30, no tag)
min. space of SDPW to SDNW not facing gate
min. / max. space of SDPW to SDNW facing gate
min. space of SDNW to SDPW outer edge (In V30)
min. space of SDNW to PDIFF (backgate) (In V30)
max. space of NDIFF to PDIFF (backgate)
Layout Rule
(um)
0.42
0.42
2.50
2.12
1.50
0.75
0.30
1.00
0.00
0.00
5.13
2.12
25.20
108 of 224
DBH CONFIDENTIAL
SDNW
SDPW
23S24b
23S24a
POLY
6X3f
3S3b
DIFF
6W6n
3E23k
3E24i
3S3i
NIMP
3O24a
PIMP
23S24g
CONT
TGOX50
SAB
Backgate
P+
Source
Drain
HRID
N+
N+
NDIFF
PDIFF
MET1
SDPW
SDNW
PMD
P-SUB
STI
109 of 224
DBH CONFIDENTIAL
2.9 24V Asymmetric DE-PMOS (pch_dea_24v)
Rule No.
3W3f
3S3b
6W6o
3E23g
3O23a
3S3j
6X3g
23S24a
23S24b
23S24h
3S23f
24O22a
24X22a
3E24m
3S3f
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLYGATE to define the channel length of 20V/24/30V Asymmetric
DE-PMOS
min. enclosure of PDIFF of drain by SDPW not facing gate (V20, V30, no tag)
min. / max. overlap of SDPW to channel active
min. / max. space of DIFF for channel to DIFF for drain
min. / max. extension of POLY beyond channel active into drain direction
min. space of SDPW to SDNW not facing gate
min. / max. space of SDPW to SDNW facing gate
min. space of SDPW not facing gate to SDNW outer edge (In V30)
min. space of SDPW not facing gate to NDIFF (backgate) (In V30)
min. overlap of DNW to SDNW
min. extension of SDNW beyond DNW
min. enclosure of NDIFF by SDNW (only check outward direction of device)
max. space of PDIFF to NDIFF (backgate)
Layout Rule
(um)
0.42
0.42
1.50
1.00
0.40
1.00
0.50
0.00
0.00
5.13
2.12
2.00
1.50
2.12
25.20
110 of 224
DBH CONFIDENTIAL
SDNW
SDPW
23S24b
23S24a
POLY
6X3g
3S3b
6W6o
24X22a
3E24m
3E23g
3S3j
3O23a
DIFF
NIMP
PIMP
24O22a
CONT
23S24h
TGOX50
DNW
Backgate
Source
Drain
NDIFF
N+
P+
P+
PDIFF
MET1
PMD
SDNW
SDPW
STI
DNW
111 of 224
DBH CONFIDENTIAL
2.10 30V Asymmetric DE-NMOS (nch_dea_30v)
Rule No.
3W3f
3S3b
6W6n
3E23k
3S3m
6X3h
3O24a
3E24i
23S24a
23S24b
23S24g
3S24f
3S3e
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLYGATE to define the channel length of 20V/24/30V Asymmetric
DE-NMOS
min. enclosure of PDIFF by SDPW (only check outward direction of device)
min. / max. space of DIFF for channel to DIFF for drain
min. / max. extension of POLY beyond channel active into drain direction
min. / max. overlap of SDNW to channel active
min. enclosure of NDIFF of drain by SDNW not facing gate(V20, V30, no tag)
min. space of SDPW to SDNW not facing gate
min. / max. space of SDPW to SDNW facing gate
min. space of SDNW to SDPW outer edge (In V30)
min. space of SDNW to PDIFF (backgate) (In V30)
max. space of NDIFF to PDIFF (backgate)
Layout Rule
(um)
0.42
0.42
2.50
2.12
2.00
1.00
0.30
1.00
0.00
0.00
5.13
2.12
25.20
112 of 224
DBH CONFIDENTIAL
SDNW
SDPW
23S24b
23S24a
POLY
6X3h
3S3b
DIFF
6W6n
3E23k
3E24i
3S3m
NIMP
3O24a
PIMP
23S24g
CONT
TGOX50
SAB
Backgate
P+
Source
Drain
HRID
N+
N+
NDIFF
PDIFF
MET1
SDPW
SDNW
PMD
P-SUB
STI
113 of 224
DBH CONFIDENTIAL
2.11 30V Asymmetric DE-PMOS (pch_dea_30v)
Rule No.
3W3f
3S3b
6W6o
3E101a
3O101a
3S3j
6X3g
101S24a
101S24b
101S24c
101S3a
24O22a
24X22a
3E24m
3S3f
Description of key design rule
min. width of a DIFF to define the width of DE-NMOS/DE-PMOS
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLYGATE to define the channel length of 20V/24/30V Asymmetric
DE-PMOS
min. enclosure of PDIFF of drain by PDT not facing gate (V20, V30, no tag)
min. / max. overlap of PDT to channel active
min. / max. space of DIFF for channel to DIFF for drain
min. / max. extension of POLY beyond channel active into drain direction
min. space of PDT to SDNW not facing gate
min. / max. space of PDT to SDNW facing gate
min. space of PDT not facing gate to SDNW outer edge (In V30)
min. space of PDT to NDIFF (backgate) (In V30)
min. overlap of DNW to SDNW
min. extension of SDNW beyond DNW
min. enclosure of NDIFF by SDNW (only check outward direction of device)
max. space of PDIFF to NDIFF (backgate)
Layout Rule
(um)
0.42
0.42
1.50
1.00
0.40
1.00
0.50
0.00
0.00
5.13
1.62
2.00
1.50
2.12
25.20
114 of 224
DBH CONFIDENTIAL
SDNW
PDT
101S24b
101S24a
POLY
6X3g
3S3b
6W6o
3E24m
24X22a
3E101a
3S3j
3O101a
DIFF
NIMP
PIMP
24O22a
CONT
101S24c
TGOX50
DNW
Backgate
Source
Drain
NDIFF
N+
P+
P+
PDIFF
MET1
PMD
SDNW
PDT
STI
DNW
115 of 224
DBH CONFIDENTIAL
3. BJTs
3.1 8V vertical NPN (npn_v_8v)
Rule No.
Description of key design rule
3W3e
24X22a
24O22c
3S3o
3S3k
23E22a
3E23b
3E23m
3E23e
8E3a
23S24k
105E24c
105E40a
40E40a
105E111a
min. / max. size of a DIFF to define the area of Emitter
min. extension of SDNW beyond DNW
min./ max. overlap of DNW to SDNW
min./ max. space of a NDIFF of emitter to a PDIFF of base
min. space of a NDIFF of collector to a PDIFF of base
min. / max. enclosure of SDPW by DNW
min. enclosure of PDIFF(base pickup) by SDPW (V12)
Min. enclosure of PDIFF(P-sub pickup) by SDPW
min. / max. enclosure of NDIFF(emitter) by SDPW
min. enclosure of NDIFF (in PW or SDPW) by NIMP
min. / max. space of SDNW of a collector to SDPW of P-sub pickup
min. / max. enclosure of SDNW outer edge of a collector by PCHSTBLK
min. / max. enclosure of PCHSTBLK by DUMDIFFBLK
min. / max. enclosure of DUMDIFFBLK by DUMPYBLK
min. / max. enclosure of PCHSTBLK by TGOX50
Layout Rule
(um)
1, 2, 4, 8, 16
1.50
2.00
1.42
1.50
2.00
0.50
0.40
2.42
0.18
1.00
1.00
0.00
0.00
0.00
116 of 224
DBH CONFIDENTIAL
SDNW
SDPW
DIFF
22O22c
23E22a
24X2a
NIMP
PIMP
3S3k
3S3o
CONT
3W3e
3E23b
TGOX50
3E23e
DNW
23S24k
P-sub
Collector
Base
Emitter
P+
N+
P+
N+
SDNW
SDPW
SDPW
Base
P+
Collector
N+
SDNW
P-sub
P+
SDPW
DNW
NDIFF
MET1
PDIFF
PMD
STI
117 of 224
DBH CONFIDENTIAL
3.2 20V Substrate PNP (pnp_s_20v)
Rule No.
3W3e
3E24e
3S3l
3E24f
7E3a
23S24m
105E23a
105E40a
40E40a
105E111a
Description of key design rule
min. / max. size of a DIFF to define the area of Emitter
min. / max. enclosure of NDIFF by SDNW
min. / max. space of NDIFF of base to PDIFF of emitter
min. enclosure of PDIFF by SDNW
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. / max space of SDNW of a base to SDPW of a collector
min. / max. enclosure of SDPW outer edge of a collector by PCHSTBLK
min. / max. enclosure of PCHSTBLK by DUMDIFFBLK
min. / max. enclosure of DUMDIFFBLK by DUMPYBLK
min. / max. enclosure of PCHSTBLK by TGOX50
Layout Rule (um)
1, 2, 4, 8, 16
1.50
3.20
5.70
0.18
1.00
0.00
0.00
0.00
0.00
118 of 224
DBH CONFIDENTIAL
SDPW
DIFF
NIMP
3E24f
PIMP
3S3l
3E24e
CONT
3W3e
TGOX50
DNW
23S24m
SDNW
Collector
Base
Emitter
N+
P+
P+
SDPW
SDNW
NDIFF
MET1
STI
PDIFF
PMD
SDNW
Base
N+
Collector
P+
SDPW
119 of 224
DBH CONFIDENTIAL
3.3 5V Vertical NPN w/ SDNW and SDPW (npn_v_hv_5v)
Rule No.
3W3e
24X22a
24O22a
23S24a
3S3r
3S3n
3E23n
3E23a
40E24a
111E40a
40E40a
Description of key design rule
min. / max. size of a DIFF to define the area of Emitter
min. extension of SDNW beyond DNW
min. overlap of DNW to SDNW
min. space SDPW (Base) to SDNW (Collector)
min./ max space NDIFF (emitter) to PDIFF (base)
min. / max space of a NDIFF of a collector to a PDIFF of a base
min. / max. enclosure of HVNDIFF(emitter) by SDPW
min. enclosure of PDIFF by SDPW
min. / max. enclosure of SDNW outer edge of a collector by a
DUMDIFFBLK
min. / max. enclosure of DUMDIFFBLK by TGOX50
min. / max. enclosure of DUMDIFFBLK by DUMPYBLK
Layout Rule[um]
1, 2, 4, 8, 16
1.50
2.00
0.00
0.42
1.12
1.04
0.12
0.00
0.00
0.00
120 of 224
DBH CONFIDENTIAL
SDPW
DIFF
24O22a 24X22a
NIMP
PIMP
3S3n
3S3r
CONT
3W3e
TGOX50
23S24a
3E23n
DNW
3E23a
SDNW
Collector
Base
Emitter
N+
P+
N+
SDNW
SDPW
Base
P+
Collector
N+
SDNW
DNW
NDIFF
MET1
PDIFF
PMD
STI
121 of 224
DBH CONFIDENTIAL
3.4 5V Vertical PNP w/ SDNW and SDPW (pnp_v_hv_5v)
Rule No.
3W3e
3S3s
3E24n
3E24a
3E23a
7E3b
8E3b
7E3a
23S24a
105E23a
105E40a
40E40a
111E3a
111Ra
Description of key design rule
min. / max. size of a DIFF to define the area of Emitter
min./ max space NDIFF (Base) to PDIFF (Emitter and collector)
min./ max enclosure of PDIFF(emitter) by SDNW
min. enclosure of NDIFF(base) by SDNW
min. enclosure of PDIFF(collector) by SDPW
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. space of SDPW to SDNW
min. / max. enclosure of SDPW outer edge of a collector by PCHSTBLK
min. / max. enclosure of PCHSTBLK by DUMDIFFBLK
min. / max. enclosure of DUMDIFFBLK by DUMPYBLK
min. enclosure of DIFF by TGOX50
Any DIFF must be enclosed by TGOX50 layer
Layout Rule (um)
1, 2, 4, 8, 16
0.42
0.96
0.12
0.12
0.02
0.02
0.18
0.00
0.00
0.00
0.00
0.32
122 of 224
DBH CONFIDENTIAL
SDPW
DIFF
3S3s
NIMP
PIMP
3S3s
3E24n
3E24a
CONT
3E23a
3W3e
TGOX50
DNW
23S24a
SDNW
Collector
Base
Emitter
N+
P+
P+
SDPW
SDNW
NDIFF
MET1
STI
PDIFF
PMD
SDNW
Base
N+
Collector
P+
SDPW
123 of 224
DBH CONFIDENTIAL
3.5 10V Lateral PNP (pnp_l_10v)
Rule No.
3W3e
24W24d
22X2a
22O2a
24E2b
24E2c
3E24g
3E24k
1S1f
3E1b
1S24a
1S24c
1S24d
1S24b
1S2e
105E2a
105E40a
40E40a
105E111a
Description of key design rule
min. / max. size of a DIFF to define the size of Emitter active
min./ max. width of a SDNW to define the width of Base (between emitter and
collector)
min. extension of NW beyond DNW
min overlap of DNW by NW
min. / max. enclosure of NW by SDNW (NW outer edge)
min. / max. enclosure of NW by SDNW (NW inner edge)
min. / max. enclosure of HVNDIFF by SDNW (outer SDNW edge)
min. / max. enclosure of HVNDIFF by SDNW (inner SDNW edge)
min. / max. space PWELL emitter and PWELL collector
min. / max. enclosure of HVPDIFF(emitter & collector) by PWELL
min./ max space of PWELL of emitter to SDNW
min./ max space of PWELL of collector to SDNW (outer PW edge in collector)
min./ max space of PWELL of collector to SDNW (inner PW edge in collector)
min. space of PWELL (p-sub) to SDNW
min. / max. space of NW of a base to PW of P-sub pickup
min. / max. enclosure of NW outer edge of a base by PCHSTBLK
min. / max. enclosure of PCHSTBLK by DUMDIFFBLK
min. / max. enclosure of DUMDIFFBLK by DUMPYBLK
min. / max. enclosure of PCHSTBLK by TGOX50
Layout Rule (um)
1, 2, 4, 8, 16
2.40
1.50
2.00
0.00
1.00
1.70
1.80
2.40
0.50
0.00
0.50
0.00
1.00
1.00
1.00
0.00
0.00
0.00
124 of 224
DBH CONFIDENTIAL
PWELL
SDPW
3E1b
DIFF
3E1b
22O2a
3E1b
22X2a
NIMP
PIMP
1S1f
3S3k
24E2b
CONT
3W3e
24W24d
3E23b
TGOX50
3E24g
3E23e
DNW
NWELL
SDNW
P-sub
Base
P+
Collector
Emitter
P+
N+
Collector
Base
P-sub
P+
N+
P+
P+
1S24d
NW
+SDNW
PW
SDNW
PW
SDNW
PW
SDNW
1S24a
PW
24E2c
SDNW
1S24b
NW 1S2e
+SDNW
PW
1S24c
DNW
NDIFF
MET1
STI
PDIFF
PMD
SDNW
125 of 224
DBH CONFIDENTIAL
3.6 5V Vertical NPN (npn_v_5v)
Rule No.
3W3e
22X2a
22O2a
1S2a
3S3r
3S3n
3E2b
3E1a
40E2a
111E40a
40E40a
Description of key design rule
min. / max. size of a DIFF to define the area of Emitter
min. extension of NW beyond DNW
min. overlap of DNW to NW
min. space PW (Base) to NW (Collector)
min./ max space NDIFF (emitter) to PDIFF (base)
min. / max space of a NDIFF of a collector to a PDIFF of a base
min. / max. enclosure of HVNDIFF(emitter) by PW
min. enclosure of PDIFF by PW
min. / max. enclosure of NW outer edge of a collector by a DUMDIFFBLK
Min. / max. enclosure of DUMDIFFBLK by TGOX50
min. / max. enclosure of DUMDIFFBLK by DUMPYBLK
Layout Rule[um]
1, 2, 4, 8, 16
1.50
2.00
0.00
0.42
1.12
1.04
0.12
0.00
0.00
0.00
126 of 224
DBH CONFIDENTIAL
PWELL
SDPW
DIFF
22O2a
22X2a
NIMP
PIMP
3S3n
3S3r
CONT
3W3e
TGOX50
1S2a
3E2b
DNW
3E1a
Collector
Base
Emitter
N+
P+
N+
NW
PW
NWELL
Base
P+
Collector
N+
NW
DNW
NDIFF
MET1
PDIFF
PMD
STI
127 of 224
DBH CONFIDENTIAL
3.7 5V Vertical PNP (pnp_v_5v)
Rule No.
3W3e
3E2a
3E1a
3S3s
7E3b
8E3b
7E3a
1S2a
Description of key design rule
min. / max. size of a DIFF to define the area of Emitter
min. enclosure of NDIFF by NW
min. enclosure of PDIFF by PW
min./ max space NDIFF (Base) to PDIFF (Emitter and collector)
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. space PW to NW
Layout Rule[um]
1, 2, 4, 8, 16
0.12
0.12
0.42
0.02
0.02
0.18
0.00
128 of 224
DBH CONFIDENTIAL
NWELL
3S3b
PWELL
3S3s
DIFF
NIMP
PIMP
3W3e
CONT
7E3b
1S2a
3E2a
7E3a
Collector
8E3b
3E1a
Base
Emitter
Base
N+
P+
N+
P+
PW
NW
NDIFF
MET1
PDIFF
PMD
Collector
P+
N+
PW
STI
129 of 224
DBH CONFIDENTIAL
4. Resistors
4.1 High Sheet Resistance Poly Resistor (res_pp1_hsr, res_pp1_hsr_1k)
Rule No.
Description
min. width of HRI POLY Resistor
min. length of res_pp1_hsr
min. enclosure of POLY resistor by HRI
min. extension of PIMP beyond a POLY as a resistor head
min. extension of SAB to related field POLY
min. extension of HRID beyond POLY
min. / max. extension of SAB beyond HRID
min. enclosure of POLY Resistor by TGOX50
min. / max. space of PIMP to HRID
CONT to pick up poly resistor should be a single column array.
Do not use dog-bone type resistor head.
HRID is a dummy layer for blocking the nuisance implant (SD I/I, LDD I/I).
Draw the RESIST layer with body area of poly resistor.
CONT must not be located in RESIST.
See the poly resistor section for multi-segment unit rule.
Bent poly resistor is not allowed.
res_pp1_hsr and res_pp1_hsr_1k cannot be provided at one process simultaneously.
90W90b
47La
90E6a
7X6b
47X6a
91X6a
47X91a
111E6a
7S91a
47Ra
47Rb
91Na
31Ra
31Rb
47Na
6Rd
90Na
Layout
Rule[um]
0.42
5.00
0.26
0.18
0.22
0.30
0.30
0.40
0.00
POLY
111E6a
47X6a
PIMP
91X6a
47X91a
HRI
90W90b
7S91a
7X6b
90E6a
LENGTH
HRID
TGOX50
SAB
CONT
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DBH CONFIDENTIAL
4.2 Low Sheet Resistance Poly Resistor (res_pp1_lsr)
Rule No.
Description of key design rule
47W47b
47Lb
min. width of POLY resistor
min. length of res_pp1_lsr
7E6a
min. enclosure of POLY as a resistor by PIMP
111E6a
47Ra
47Rb
31Ra
31Rb
6Rd
47Na
min. enclosure of POLY Resistor by TGOX50
CONT to pick up poly resistor should be a single column array.
Do not use dog-bone type resistor head.
Draw the RESIST layer with body area of poly resistor.
CONT must not be located in RESIST.
Bent poly resistor is not allowed.
See the poly resistor section for multi-segment unit rule.
111E6a
Layout
Rule[um]
0.42
5.00
0.26
0.40
POLY
PIMP
47W47b
TGOX50
7E6a
CONT
131 of 224
DBH CONFIDENTIAL
4.3 P+ Poly Non-salicided Resistor (res_pp1)
Rule No.
Description of key design rule
47W47b
47Lc
min. width of POLY resistor
min. length of res_pp1
7E6a
min. enclosure of POLY as a resistor by PIMP
47X6a
111E6a
47Ra
47Rb
31Ra
31Rb
6Rd
47Na
min. extension of SAB to related field POLY
min. enclosure of POLY Resistor by TGOX50
CONT to pick up poly resistor should be a single column array.
Do not use dog-bone type resistor head.
Draw the RESIST layer with body area of poly resistor.
CONT must not be located in RESIST.
Bent poly resistor is not allowed.
See the poly resistor section for multi-segment unit rule.
111E6a
47X6a
Layout
Rule[um]
0.42
5.00
0.26
0.22
0.40
POLY
PIMP
47W47b
TGOX50
7E6a
SAB
CONT
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DBH CONFIDENTIAL
4.4 N+ Poly Non-salicided Resistor (res_np1)
Rule No.
47W47b
47Ld
8E6a
47X6a
111E6a
47Ra
47Rb
31Ra
31Rb
6Rd
47Na
Layout
Rule[um]
0.42
5.00
0.26
0.22
0.40
Description of key design rule
min. width of POLY resistor
min. length of res_np1
min. enclosure of POLY as a resistor by NIMP
min. extension of SAB to related field POLY
min. enclosure of POLY Resistor by TGOX50
CONT to pick up poly resistor should be a single column array.
Do not use dog-bone type resistor head.
Draw the RESIST layer with body area of poly resistor.
CONT must not be located in RESIST.
Bent poly resistor is not allowed.
See the poly resistor section for multi-segment unit rule.
POLY
111E6a
47X6a
NIMP
47W47b
TGOX50
8E6a
SAB
CONT
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DBH CONFIDENTIAL
Poly Resistor
1.Poly Resistor Block: if long side of poly line with SAB(or RES) is more than 10um and space between
poly lines with SAB( or RES) is less than 5um, then the resistor group defined as
Poly Resistor Block.
Poly Resistor
Block
Length > 10um
SAB or RES
Space <=5um
2
1-1.Total Area of Poly Resistor Block on field cannot exceed 90000 um .
If space between Poly Resistor Blocks is less than 10um, the resistor blocks are regarded as one resistor
block in DRC.
Space >= 10um
Area < 90000 um2
Rule No.
47Rc
Description
Layout Rule[um]
max. area of a Poly Resistor Block (um2)
90000
1-2.If short side length of Poly Resistor Block is more than 40um, the space from resistor block to nearby active
diffusion should be more than 10um to reserve room for dummy diffusion.
Short side length > 40um
Space >= 10um
134 of 224
DBH CONFIDENTIAL
Rule No.
Description
Layout Rule[um]
min. extension from DIFF to Poly Resistor Block whose short
side length is more than 40um
There must be no DUMBLK(diff) and DUMBLK(all) in the area
of 10um beyond Poly Resistor Block whose short side length is
more than 40um.
47S3b
47Rd
10
2.Multi-segment unit have a design rule as below.
2-1.Poly to poly space >= 2um, SAB layer take drawing on each of the poly resistor body.
SAB layer
>=2um
2-2.Poly to poly space 0.25um<= and < 2um, SAB layer take drawing on whole area of the poly resistor
block.
0.25um<= poly to poly space<2.0um
Rule No.
47S47b
47S47c
Description
min. space of Poly Resistor (drawing SAB layer on each of the poly
resistor body )
min. space of Poly Resistor (drawing SAB layer to the whole resistor
block )
Layout Rule[um]
2
0.25
135 of 224
DBH CONFIDENTIAL
3.Dummy Poly drawing
RESIST layer
Dummy poly
Dummy poly
Drawing the dummy poly(NO drawing RESIST layer) at both side of multi-segment unit, space between poly
resistor and dummy poly depend on space rule of SAB layer(refer to Number 3).
4.Prevention of parasitic field transistor turn-on by poly resistor
6S24a
POLY
6E2a
6E24a
SDNW
6S2a
NWELL
Not allowed
Rule No.
6E24a
6S24a
6E2a
Description
min. enclosure of POLY as poly resistor by
SDNW
min. space of POLY as poly resistor to
SDNW
min. enclosure of POLY as poly resistor by
NW
6S2a
min. space of POLY as poly resistor to NW
6Rc
POLY must not be used for interconnect
Condition
coincident not ok,
overlap not ok
butting not ok, overlap
not ok
coincident not ok,
overlap not ok
butting not ok, overlap
not ok
In V20, V30, including no
voltage tag
Exception; poly resistor
Layout Rule[um]
1.50
1.50
1.50
1.50
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DBH CONFIDENTIAL
4.5 P+ Diff Non-salicided Resistor (res_pdiff)
Rule No.
47W47c
47Le
7E3a
47X3a
111E3a
47S9a
3E24h
31Rb
3Rg
Description
min. width of DIFF Resistor
min. length of res_pdiff
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. extension of SAB to related DIFF
min. enclosure of DIFF by TGOX50
min. space between SAB and CONT
min. enclosure of PDIFF by SDNW
CONT must not be located in RESIST.
Bent diff resistor is not allowed.
Layout Rule[um]
0.42
5.00
0.18
0.22
0.32
0.22
0.70
Note) Bulk terminal of p-type resistor should be connected highest potential.
SDNW
POLY
111E3a
47X3a
DIFF
NIMP
47W47c
47S9a
PIMP
7E3a
CONT
3E24e
TGOX50
SAB
Minus
Plus
Bulk
NDIFF
PDIFF
MET1
N+
P+
PMD
STI
SDNW
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DBH CONFIDENTIAL
4.6 N+ Diff Non-salicided Resistor (res_ndiff)
Rule No.
47W47c
47Lf
8E3a
47X3a
111E3a
47S9a
3E23f
31Rb
3Rh
Description
min. width of DIFF Resistor
min. length of res_ndiff
min. enclosure of NDIFF (in PW or SDPW) by NIMP
min. extension of SAB to related DIFF
min. enclosure of DIFF by TGOX50
min. space between SAB and CONT
min. enclosure of NDIFF by SDPW
CONT must not be located in RESIST.
Bent diff resistor is not allowed.
Layout Rule[um]
0.42
5.00
0.18
0.22
0.32
0.22
0.70
Note) SUB terminal of n-type resistor should be connected lowest potential.
SDPW
POLY
111E3a
47X3a
DIFF
NIMP
47W47c
47S9a
PIMP
8E3a
CONT
3E23f
TGOX50
SAB
Plus
Minus
P-sub
NDIFF
PDIFF
MET1
P+
N+
PMD
STI
SDPW
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DBH CONFIDENTIAL
4.7 P+ Diff Silicided Resistor in SDNW (res_pdiff_lsr_sdnw)
Rule No.
47W47c
47Lh
7E3a
3E24l
31Rb
3Rh
Description
min. width of DIFF Resistor
min. length of res_pdiff_lsr_sdnw
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. enclosure of PDIFF by SDNW
CONT must not be located in RESIST.
Bent diff resistor is not allowed.
Layout Rule[um]
0.42
5.00
0.18
0.70
Note) Bulk terminal of p-type resistor should be connected highest potential.
SDNW
POLY
DIFF
NIMP
47W47c
PIMP
7E3a
CONT
3E24l
TGOX50
SAB
Minus
Plus
Bulk
NDIFF
PDIFF
MET1
N+
P+
PMD
STI
SDNW
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DBH CONFIDENTIAL
4.8 SDNW Resistor (res_sdnw)
Rule No.
Description
min. width of SDNW Resistor
min. length of res_sdnw
min. enclosure of NDIFF by NIMP (Resistor head)
min. space between two SDNW Resistor
min. space of SDNW (resistor body) to SDNW (not resistor)
min. enclosure of NDIFF by SDNW
Bent sdnw resistor is not allowed.
24W24b
24La
8E3d
24S24f
24S24g
3E24n
24Rc
Layout
Rule[um]
0.86
5.00
0.18
4.40
4.40
0.00
Note) SUB terminal of n-type resistor should be connected lowest potential.
SDNW
POLY
DIFF
NIMP
24W24b
PIMP
CONT
8E3d
SDPW
Plus
Minus
P-sub
NDIFF
PDIFF
MET1
N+
N+
P+
PMD
STI
SDNW
SDPW
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DBH CONFIDENTIAL
4.9 P+ Diff Silicided Resistor (res_pdiff_lsr)
Rule No.
47W47c
47Lg
7E3a
3E2c
31Rb
3Rh
Description
min. width of DIFF Resistor
min. length of res_pdiff_lsr
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. enclosure of PDIFF by NW
CONT must not be located in RESIST.
Bent diff resistor is not allowed.
Layout Rule[um]
0.42
5.00
0.18
0.43
Note) Bulk terminal of p-type resistor should be connected highest potential.
NWELL
POLY
DIFF
NIMP
47W47c
PIMP
7E3a
CONT
3E2c
TGOX50
SAB
Minus
Plus
Bulk
NDIFF
PDIFF
MET1
N+
P+
PMD
STI
NW
141 of 224
DBH CONFIDENTIAL
4.10 NWELL Resistor (res_nw)
Rule No.
Layout
Rule[um]
0.86
5.00
0.18
1.40
2.90
3.50
2.90
Description
min. width of NWELL Resistor
min. length of res_nw
min. enclosure of NDIFF by NIMP (Resistor head)
min. space between two NWELL Resistor
min. space of NW (resistor body) to NW (not resistor)
min. space of DNW to NW
min. space of SDNW to NW
Bent nwell resistor is not allowed.
2W2b
2La
8E3d
2S2f
2S2g
22S2b
24S2g
2Rb
Note) SUB terminal of n-type resistor should be connected lowest potential.
NWELL
POLY
DIFF
NIMP
2W2b
PIMP
CONT
8E3d
SDPW
Plus
Minus
P-sub
NDIFF
PDIFF
MET1
N+
N+
P+
PMD
STI
NW
SDPW
142 of 224
DBH CONFIDENTIAL
4.11 Poly fuse (res_p1f)
Rule No.
6W6x
6W6y
9W9a
9E6a
9S3a
10E9a
10E9b
6W6v
6W6w
6S10a
6S12a
6S14a
6S16a
6S18a
6S20a
6S3b
6S6d
88Ra
88Rb
6E40a
88Rc
88 Rd
111E6b
Layout
Rule[um]
5.5
0.6
0.22
0.1
0.2
0.005
0.06
2.88
3.5
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
Description
min. & max. width of a POLY of Fuse length
min. & max. width of a POLY of Fuse width
min. & max. size of CONT
min. enclosure of POLY CONT by POLY
min. space between CONT on POLY and DIFF
min. enclosure of CONT by M1
min. enclosure of CONT by M1 end-of-line region
min. & max. width of a POLY of landing PAD of fuse length direction
min. & max. width of a POLY of landing PAD of fuse width direction
min. space between polyfuse link and M1
min. space between polyfuse link and M2
min. space between polyfuse link and M3
min. space between polyfuse link and M4
min. space between polyfuse link and M5
min. space between polyfuse link and M6
min. space between polyfuse link and DIFF
min. space between polyfuse link and POLY
CONT must not touch polyfuse link
polyfuse link must be contained by DUMBLK(40:0)
min. enclosure of polyfuse link by DUMBLK(40:0)
All Metal layers are not allowed over the polyfuse link
(Metal route and dummy)
POLY must be enclosed by NIMP
min. enclosure of POLY fuse by TGOX50
3.0
0.40
Fuselink
length: 5.5um
width 0.6um
6W6w
111E6b
6W6v
MET1
MET1
CoSi2
POLY
STI
POLY
CONT
CoSi2
NIMP
STI
MET1
PMD
TGOX50
143 of 224
DBH CONFIDENTIAL
4.12 Metal-1 Resistor (res_m1)
Rule No.
10W10a
11E10a
11E10b
Layout
Rule[um]
0.23
0.01
0.06
Description
min. width of M1
min. enclosure of VIA1 by M1
min. enclosure of VIA1 by M1 end-of-line region
11E10b
10W10a
11E10a
MET2, top view
MET2, side view
VIA1
MET1, top view
MET1, side view
IMD1
PMD
STI
144 of 224
DBH CONFIDENTIAL
4.13 Metal-2 Resistor (res_m2)
Rule No.
12W12a
13E12a
13E12b
Layout
Rule[um]
0.28
0.01
0.06
Description
min. width of M2
min. enclosure of VIA2 by M2
min. enclosure of VIA2 by M2 end-of-line region
13E12b
12W12a
13E12a
MET3, top view
MET3, side view
VIA2
MET2, top view
MET2, side view
IMD2
IMD1
PMD
STI
145 of 224
DBH CONFIDENTIAL
4.14 Metal-3 Resistor (res_m3)
Rule No.
14W14a
15E14a
15E14b
Layout
Rule[um]
0.28
0.01
0.06
Description
min. width of M3
min. enclosure of VIA3 by M3
min. enclosure of VIA3 by M3 end-of-line region
15E14b
14W14a
15E14a
MET4, top view
MET4, side view
VIA3
MET3, top view
MET3, side view
IMD3
IMD2
IMD1
PMD
STI
146 of 224
DBH CONFIDENTIAL
4.15 Metal-4 Resistor (res_m4)
Rule No.
16W16a
17E16a
17E16b
Layout
Rule[um]
0.28
0.01
0.06
Description
min. width of M4
min. enclosure of VIA4 by M4
min. enclosure of VIA4 by M4 end-of-line region
17E16b
16W16a
17E16a
MET5, top view
MET5, side view
VIA4
MET4, top view
MET4, side view
IMD4
IMD3
IMD2
IMD1
PMD
STI
147 of 224
DBH CONFIDENTIAL
4.16 Metal-5 Resistor (res_m5)
Rule No.
18W18a
19E18a
19E18b
Layout
Rule[um]
0.28
0.01
0.06
Description
min. width of M5
min. enclosure of VIA5 by M5
min. enclosure of VIA5 by M5 end-of-line region
19E18b
18W18a
19E18a
MET6, top view
MET6, side view
VIA5
MET5, top view
MET5, side view
IMD5
IMD4
IMD3
IMD2
IMD1
PMD
STI
148 of 224
DBH CONFIDENTIAL
4.17 Top Metal Resistor (res_top)
Rule No.
20W20a
20E19a
20E19b
Layout
Rule[um]
0.44
0.09
0.09
Description
min. width of M6
min. enclosure of VIA5 by M6
min. enclosure of VIA5 by M6 end-of-line region
20E19b
20W20a
20E19a
MET6, top view
MET6, side view
VIA5
MET5, top view
MET5, side view
IMD6
IMD5
IMD4
IMD3
IMD2
IMD1
PMD
STI
149 of 224
DBH CONFIDENTIAL
4.18 Top Thick Metal Resistor (res_top_thick)
Rule No.
20W20b
20E19c
Layout
Rule[um]
3.1
0.8
Description
min. width of M6
min. enclosure of VIA5 by M6
20E19c
20W20b
MET6, top view
MET6, side view
VIA5
MET5, top view
MET5, side view
IMD5
IMD4
IMD3
IMD2
IMD1
PMD
STI
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DBH CONFIDENTIAL
5. Capacitors
5.1 NPOLY-SDNW Capacitor with thick oxide (cap_sdnwnp1_5p0v)
Rule No.
Description of key design rule
min. enclosure of DIFF by TGOX50
min. enclosure of 5.0V transistor POLYGATE by TGOX50
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
min. enclosure of NDIFF by SDNW (In V2, V5, V7, ISO_V7)
111E3a
111E3b
8E3b
3E24a
Layout Rule
(um)
0.32
0.40
0.02
0.12
SDNW
111E3b
POLY
DIFF
NIMP
111E3a
3E24a
PIMP
CONT
TGOX50
8E3b
SDPW
Minus
Plus
Minus
P-sub
NDIFF
PDIFF
N+
N+
P+
MET1
PMD
STI
SDNW
SDPW
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DBH CONFIDENTIAL
5.2 MIM Capacitor (cap_mim, cap_mim_1f)
Rule No
87W87a
87W87b
87W87c
87S87a
87S87b
87S87c
87E19a
87E19b
87E18a
87S19a
87S19b
87S19c
87W87d
87W87e
87Nc
Description of key design rule
min. width of MTM as a capacitor top plate
min. width of a dummy MTM in same MN+1 plate
min. width of a dummy MTM in different MN+1 plate
min. space between two MTM as a capacitor top plate
min. space between a dummy MTM and a MTM regions
min. space between a dummy MN+1 of a capacitor bottom plate and MN+1 as a
capacitor bottom plate
min. enclosure of VIAN+1 by MTM
min. enclosure of VIAN or VIAN+1 by MN+1 as a capacitor bottom plate
min. enclosure of MTM by MN+1 as a capacitor bottom plate
min. space between a VIAN or VIAN+1 and MTM
min. space between two VIAN+1 located upon MTM
min. space between two VIAN+1 located upon MN+1
max. width of a MTM as a capacitor top plate
max. width of a MN+1 as a capacitor bottom plate
Layout Rule (um)
4.00
0.40
0.40
1.20
0.80
0.80
0.24
0.12
0.40
0.40
2.00
4.00
30.0
35.0
cap_mim and cap_mim_1f cannot be provided at one process simultaneously.
Note) MiM capacitor is not provided in the 1P2M process.
152 of 224
DBH CONFIDENTIAL
87E19b
87E18a
87W87a
87W87e
87S19c
87S19b
87S19a
87S87a
87E19a
87S19a
Mn+1 Interconnection
VIAn+1
MTM
VIAn
Mn+1
Capacitor Dummy2
Capacitor Dummy1
87S87b
87S87c
MTM
MTM
87W87b
87W87c
Dummy MTM
Dummy MTM
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DBH CONFIDENTIAL
5.3 NPOLY-NWELL Capacitor with thin oxide (cap_nwnp1_1p8v)
Rule No.
Layout Rule
(um)
0.02
0.12
Description of key design rule
8E3b
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
3E2a
min. enclosure of NDIFF by NW
NWELL
POLY
DIFF
NIMP
3E2a
PIMP
CONT
SDPW
8E3b
Minus
Plus
Minus
P-sub
NDIFF
PDIFF
MET1
PMD
N+
N+
P+
STI
NW
SDPW
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DBH CONFIDENTIAL
6. Diodes
6.1 NSD-SDPW Diode (dio_nsd_sdpw)
Rule No.
Layout
Rule[um]
0.12
Description of key design rule
min. enclosure of PDIFF by SDPW
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to
PDIFF) (Inside TGOX50)
min. enclosure of NDIFF (in PW or SDPW) by NIMP
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
3E23a
3S3b
8E3a
7E3b
0.42
0.18
0.02
SDPW
7E3b
DIFF
NIMP
3S3b
PIMP
8E3a
3E23a
CONT
TGOX50
Anode
Cathode
Anode
NDIFF
PDIFF
MET1
PMD
STI
SDPW
155 of 224
DBH CONFIDENTIAL
6.2 PSD-SDNW Diode (dio_psd_sdnw)
Rule No.
Layout
Rule[um]
0.12
Description of key design rule
min. enclosure of NDIFF by SDNW
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to
PDIFF) (Inside TGOX50)
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
3E24a
3S3b
7E3a
8E3b
0.42
0.18
0.02
SDNW
8E3b
DIFF
NIMP
3S3b
PIMP
7E3a
3E24a
CONT
TGOX50
Cathode
Anode
Cathode
NDIFF
PDIFF
MET1
PMD
STI
SDNW
156 of 224
DBH CONFIDENTIAL
6.3 MV Zener Diode (dio_z_mv)
Rule No.
Layout
Rule[um]
2.46
1.5
2.0
0.12
0.02
1.3
0.4
1.1
0.00
0.40
0.02
0.32
1.50
Description of key design rule
min. width of DIFF to define the width of Diode
min. extension of SDNW beyond DNW
min. overlap of DNW to SDNW
min. enclosure of PDIFF by SDPW
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
min. enclosure of NIMP by PSDBLK
min. enclosure of PSDBLK by SAB
min. enclosure of SAB by DIFF
min. space SDPW to SDNW
min. overlap of SAB to NIMP
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
min. enclosure of DIFF by TGOX50
min. space of SDPW outside ISO_V30 to SDNW inside ISO_V30
ISO_V30 must include PCHSTBLK.
min. enclosure of outer edge of Iso-ring by PCHSTBLK
3W3i
24X22a
24O22a
3E23a
7E3b
8E162a
162E47a
47E3a
23S24a
8O47a
8E3b
111E3a
23S24l
105Ra
105Rb
111E3a
3E23a
DIFF
7E3b
8E162a
SDNW
47E3a
SDPW
DNW
23S24a
3W3i
47S9a
1.50
TGOX50
8O47a
PSDBLK
162E47a
7E3b
NIMP
24O22a
PIMP
24X22a
8E3b
SAB
CONT
HVPLDD
PSD
SDNW
Anode Colle
ctor
Cathode
Anode
HVPLDD
NSD
SDPW
PSD
NDIFF
S
D
PDIFF
SDNW
MET1
PMD
DNW
STI
P-sub
157 of 224
DBH CONFIDENTIAL
6.4 NSD-PWELL Diode (dio_nsd_pw)
Rule No.
Layout
Rule[um]
0.12
Description of key design rule
min. enclosure of PDIFF by PW
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to
PDIFF) (Outside TGOX50)
min. enclosure of NDIFF (in PW or SDPW) by NIMP
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
3E1a
3S3a
8E3a
7E3b
0.28
0.18
0.02
PWELL
7E3b
DIFF
NIMP
3S3a
PIMP
8E3a
3E1a
CONT
TGOX50
Anode
Cathode
Anode
NDIFF
PDIFF
MET1
PMD
STI
PWELL
158 of 224
DBH CONFIDENTIAL
6.5 PSD-NWELL Diode (dio_psd_nw)
Rule No.
Layout
Rule[um]
0.12
Description of key design rule
min. enclosure of NDIFF by NW
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to
PDIFF) (Outside TGOX50)
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
3E2a
3S3a
7E3a
8E3b
0.28
0.18
0.02
NWELL
8E3b
DIFF
NIMP
3S3a
PIMP
7E3a
3E2a
CONT
TGOX50
Cathode
Anode
Cathode
NDIFF
PDIFF
MET1
PMD
STI
NWELL
159 of 224
DBH CONFIDENTIAL
6.6 LV Zener Diode (dio_z_lv)
Rule No.
3W3i
22X2a
22O2a
3E1a
3E23a
7E3b
8E162a
162E47a
47E3a
1S2a
23S2a
8O47a
8E3b
111E3a
1S2f
105Ra
105Rb
Description of key design rule
min. width of DIFF to define the width of Diode
min. extension of NW beyond DNW
min. overlap of DNW to NW
min. enclosure of PDIFF by PW
min. enclosure of PDIFF by SDPW
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
min. enclosure of NIMP by PSDBLK
min. enclosure of PSDBLK by SAB
min. enclosure of SAB by DIFF
min. space PW to NW
min. space SDPW to NW
min. overlap of SAB to NIMP
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
min. enclosure of DIFF by TGOX50
min. space of PWELL outside ISO_V30 to NWELL inside ISO_V30
ISO_V30 must include PCHSTBLK.
min. enclosure of outer edge of Iso-ring by PCHSTBLK
Layout
Rule[um]
2.46
1.5
2.0
0.12
0.12
0.02
1.3
0.4
1.1
0.00
0.00
0.40
0.02
0.32
1.50
1.50
160 of 224
DBH CONFIDENTIAL
DIFF
111E3a
NWELL
7E3b
PWELL
3E1a / 3E23a
8E162a
47E3a
SDPW
DNW
1S2a/23S2a
3S3b
3W3i
47S9a
TGOX50
8O47a
PSDBLK
162E47a
7E3b
NIMP
22O2a
PIMP
22X2a
8E3b
SAB
CONT
Anode Colle
ctor
Cathode
Anode
NDIFF
PDIFF
HVPLDD
PSD
NWELL
HVPLDD
NSD
PWELL + SDPW
PSD
MET1
S
D
PMD
NWELL
STI
DNW
P-sub
161 of 224
DBH CONFIDENTIAL
7. NVMs
7.1 Single Poly EEPROM_Thick Oxide (nch_ee_5p0v)
Rule No.
3W3h
6W6p
6W6q
6W6r
8X6b
8E6b
23S24i
3E24j
3S24c
3X6a
111Ra
6O3a
8S6c
7X6c
47X3c
47E6a
Description of key design rule
min. / max. width of a DIFF (eeprom read transistor gate width)
min. / max. width of a POLY (eeprom read transistor gate length)
min. / max. width of a POLY (eeprom control gate, X-direction)
min. / max. width of a POLY (eeprom control gate, Y-direction)
min. extension of NIMP beyond POLY
min. enclosure of NIMP by POLY in Control Gate side
min. / max. space of SDPW to SDNW
min. / max. enclosure of DIFF by SDNW (tunneling region, control gate)
min. / max. space of DIFF (eeprom read transistor) to SDNW
min. extension of DIFF beyond POLY (control gate)
Any DIFF must be enclosed by TGOX50 layer
min. / max. overlap of a POLY to PDIFF (eeprom tunneling region)
min. / max. space between NIMP and POLY
(tunneling region, control gate)
min. / max. extension of PIMP beyond POLY (tunneling region)
min. extension of SAB beyond related DIFF
min. enclosure of POLY(floating) by SAB (eeprom)
Layout Rule[um]
1.00
0.50
6.70
3.70
0.26
0.18
1.00
1.00
2.00
0.40
0.70
0.80
0.80
0.40
0.22
b
47X3c
6O3a
3X6a
8E6b
47E6a
6W6p
8X6b
6W6r
a’
a
3S24c
3S24c
8S6c
7X6c
3W3h
3E24j
6W6q
23S24i
8S6c
3E24j
b’
Tunneling Gate
Control Gate
SDPW
(P-type)
SDNW
(N-type)
SDPW
(P-type)
* Tunneling region
Source & Bulk
Drain
* Control Gate
P-sub
a-a’
* Read Transistor
P-sub
b-b’
SDNW
POLY
NIMP
SAB
METAL1
SDPW
DIFF
PIMP
CONT
PCHSTBLK
TGOX50
162 of 224
DBH CONFIDENTIAL
7.2 Single Poly EEPROM_Thin Oxide (nch_ee_5p0v_to)
Rule No.
Layout
Rule[um]
1.00
0.50
0.50
4.59
3.68
2.89
1.98
0.7
0.7
0.4
0.3
0.3
0.3
2.0
0.0
0.22
0.30
0.30
Description of key design rule
min. / max. width of a DIFF (eeprom read transistor gate width)
min. / max. width of a FG (eeprom read transistor gate length)
min. / max. width of a POLY (eeprom select transistor gate length)
min. / max. width of a FG (eeprom control gate, X-direction)
min. / max. width of a FG (eeprom control gate, X-direction at contact area)
min. / max. width of a FG (eeprom control gate, Y-direction)
min. / max. width of a FG (eeprom control gate, Y-direction at contact area)
min. space of NDIFF to SDNW for EEPROM Cell
min. enclosure of PDIFF by SDPW for EEPROM Cell
min. extension from DIFF to related FG inside DIFF for EEPROM Cell
3W3h
141W141a
6W6z
141W141b
141W141c
141W141d
141W141e
3S24a
3E23h
141X3a
8E3e
141X8a
7E3f
23S23f
24X22b
47X3a
47X141a
47X141b
min. enclosure of NDIFF (in PW or SDPW) by NIMP at Read Tr. side (Coincident ok)
min. extension of NIMP beyond FG on field oxide area
min. enclosure of (SDPW) pick-up PDIFF by PIMP(Coincident ok)
min. space between two SDPW
min. extension of SDNW beyond DNW
min. extension of SAB to related DIFF
min. extension of SAB passing through DIFF to related FG
min. extension of SAB to related FG at Read tr side
b
c
3E23h
7E3f
47X141a
141W141a
a
3W3h
47X3a
23S23f
141W141c
141X8a
6W6z
a’
141W141b
141W141d
141W141e
141X3a
8E3e
3S24a
c’
b’
DIFF
SDNW
SDPW
PIMP
FG
POLY
n+ p+
SDPW
24X22b
SDPW
n+
SDNW
p+ n+
n+
NIMP
DNW
SAB
n+
CONT
n+
n+
SDPW
SDPW
DNW
DNW
DNW
P-sub
P-sub
P-sub
a-a’
b-b’
c-c’
163 of 224
DBH CONFIDENTIAL
7.3 Single Poly EPROM (pch_eprom_5p0v)
Rule No.
Description of key design rule
3E23ca
3E24ca
3E23cb
3E24cb
24X22a
24O22a
23S24a
111E3a
111E3b
8E3a
min. / max. width of POLY to define gate length of select NMOS transistor
min. / max. width of POLY to define gate length of floating PMOS transistor
min. / max. width of DIFF to define gate width of select NMOS transistor
min. / max. width of DIFF to define gate width of floating PMOS transistor
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to
PDIFF) (inside TGOX50)
min. enclosure of SDPW pick-up PDIFF by SDPW
min. enclosure of SDNW pick-up NDIFF by SDNW
min. enclosure of NDIFF (in SDPW) by SDPW
min. enclosure of PDIFF (in SDNW) by SDNW
min. extension of SDNW beyond DNW
min. overlap of DNW to SDNW
min. space of SDPW to SDNW
min. enclosure of DIFF by TGOX50
min. enclosure of 5.0V transistor POLYGATE by TGOX50
min. enclosure of NDIFF (in PW or SDPW) by NIMP
8E3b
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
7E3a
7E3b
47S9a
47E6ca
6X3b
6Rca
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
min. space between SAB and CONT
min. enclosure of POLY of floating PMOS by SAB
min. extension of a POLY beyond DIFF into field oxide (ENDCAP)
POLY of floating PMOS must be enclosed by SAB
6W6ca
6W6cb
3W3ca
3W3cb
3S3b
Layout
Rule[um]
0.50
0.50
1.00
1.00
0.42
0.21
0.21
1.00
1.00
1.50
2.00
0.00
0.32
0.40
0.18
0.02
0.18
0.02
0.22
0.22
0.22
164 of 224
DBH CONFIDENTIAL
3E24cb
47E6ca
3E23cb
3E24ca
3W3ca
6W6ca
3S3b
3S3b
3S3b
3W3cb
6W6cb
3E23ca
23S24a
24O22a
24X22a
Source
Bitline
Floating
Floating
Gate
Select
Gate
PTAB
SDPW (P-type)
NTAB
SDNW (N-type)
DNW (N-type)
DIFF
SDNW
SDPW
DNW
NIMP
PIMP
POLY
SAB
CONT
M1
TGOX50
165 of 224
DBH CONFIDENTIAL
8. nLDMOS
8.1 7V nLDMOS LSD (nch_ldmls_7v)
Rule No.
Description of key design rule
102W102b
102W102c
102W102d
102W102e
102S102f
23E102a
102X8a
min. / max. width of a DWELL (straight center section of finger)
min. / max. width of a DUMDWELL
min. / max. width of a DWELL (straight section of finger end)
min. / max. width of a DWELL (for 45deg. Edges)
min. / max. space between DWELL to DUMDWELL
min. enclosure of DUMDWELL in P-SUB or ISO P-SUB by SDPW
min. / max. extension of DWELL beyond NIMP (finger ends, in W-direction)
Min. / max. overlap of DWELL (straight center section of finger) to PIMP
(in W direction)
45-degree segments must be used in finger ends for DWELL
DUMDWELL height (in W direction) must be equal to the DWELL height
min. space of NDT to SDPW
min. / max. enclosure of NDT by PCHSTBLK
min. width of a NDIFF to define the width of nLDMOS
min. / max. width of a NDIFF (drain, in L direction)
min. / max. width of a PDIFF (finger ends, in W direction)
min. enclosure of NDIFF by NDT (drain side not facing gate)
min. enclosure of NDIFF by NDT (drain, in W direction)
min. enclosure of NDIFF by NIMP (drain side not facing gate)
min. enclosure of NDIFF by NIMP (drain, in W direction)
Any DIFF must be enclosed by TGOX50 layer
min. / max. overlap of POLY to NDT
min. / max. overlap of a POLY to common area of DWELL and NDIFF
min. / max. width of a POLY (gate length)
min. / max. space between POLY and NIMP (drain)
min. extension of a POLY beyond DIFF into field oxide (in W direction)
NIMP and PIMP source/backgate contacts must alternate
and must terminate with PIMP contacts.
min. / max. overlap of NIMP to POLY (source side)
min. / max. width of a PIMP Source (in L direction)
min. / max. width of a PIMP Source (in W direction)
min. / max. space between PIMP Source and POLY
min. / max. overlap of PIMP to POLY (finger ends, in L direction)
min. / max. space between two PIMP Source (in W direction)
min. / max. overlap of SAB to POLY (in L direction)
min. overlap of SAB to POLY (in W direction)
min. / max. extension of SAB beyond POLY into length direction
min. / max. overlap of SAB to NIMP (drain)
Min. space between SAB and CONT
min. / max. space between two CONTs (both source and drain)
PIMP or NIMP end patch must have at least one contact
min. width of a METAL1 (both source and drain)
min. space of METAL1 lines (source to drain)
min. / max. enclosure of NDIFF (drain) by LDMTAG (drain side not facing gate)
min. / max. overlap of PIMP (finger ends) to LDMTAG (in W direction)
102O7a
102Rb
102Rc
100S23a
105E100a
3W3aa
3W3ab
3W3ac
100E3a
100E3b
8E3aa
8E3ab
111Ra
6O100a
6O102a
6W6aa
6S8aa
6X3aa
8Raa
8O6aa
7W7aa
7W7ab
7S6aa
7O6aa
7S7aa
47O6aa
47O6ab
47X6aa
47O8aa
47S9aa
9S9aa
9Raa
10W10aa
10S10aa
94E3a
94O7a
Layout Rule
(um)
1.28
1.28
0.48
0.55 ≤ # ≤ 0.58
4.82
0.36
0.90
0.68
2.00
2.00
3.00
0.66
0.50
0.90
0.90
0.18
0.18
0.30
0.10
0.80
0.20
1.70
0.50
0.44
1.00
0.32
0.30
1.00
0.30
0.22
0.25
0.05
0.17
0.28
1.20
0.60
0.0
0.0
Note:

P-SUB must be connected to Source & P-Body of nLDMOS transistor.
166 of 224
DBH CONFIDENTIAL
47X6aa
NDT
DWELL
47O6aa
SDPW
47O8aa
47O6ab
6X3aa
6S8aa
POLY
94O7a
100E3b
DIFF
7O6aa
6O102a
NIMP
9S9aa
8O6aa
PIMP
7W7ab
3W3aa
SAB
7S7aa
94E3a
CONT
7W7aa
7S6aa
METAL1
102W102a
102O7a
102W102c
47S9aa
100S23a
105E100a
23E102a
3W3ac
102W102e
6O100a
102X8a
102W102d
TGOX50
PCHSTBLK
100E3a
VIA1
6W6aa
3W3ab
METAL2
LDMTAG
102S102f
P-SUB
SDPW
(P-type)
Drain
Gate
Source
(&Body)
DWELL
(P-type)
Gate
Drain
P-SUB
NDT
(N-type)
P-SUB
(P-type)
167 of 224
DBH CONFIDENTIAL
8.2 7V nLDMOS HSD (nch_ldmhs_7v)
Rule No.
Description of key design rule
102W102b
102W102c
102W102d
102W102e
102S102f
23E102a
102X8a
min. / max. width of a DWELL (straight center section of finger)
min. / max. width of a DUMDWELL
min. / max. width of a DWELL (straight section of finger end)
min. / max. width of a DWELL (for 45deg. Edges)
min. / max. space between DWELL to DUMDWELL
min. enclosure of DUMDWELL in P-SUB or ISO P-SUB by SDPW
min. / max. extension of DWELL beyond NIMP (finger ends, in W-direction)
Min. / max. overlap of DWELL (straight center section of finger) to PIMP
(in W direction)
45-degree segments must be used in finger ends for DWELL
DUMDWELL height (in W direction) must be equal to the DWELL height
min. space of NDT to SDPW
min. / max. enclosure of NDT by PCHSTBLK
min. / max. enclosure of SDNW by PCHSTBLK
min. width of a NDIFF to define the width of nLDMOS
min. / max. width of a NDIFF (drain, in L direction)
min. / max. width of a PDIFF (finger ends, in W direction)
min. enclosure of NDIFF by NDT (drain side not facing gate)
min. enclosure of NDIFF by NDT (drain, in W direction)
min. enclosure of NDIFF by NIMP (drain side not facing gate)
min. enclosure of NDIFF by NIMP (drain, in W direction)
Any DIFF must be enclosed by TGOX50 layer
min. / max. overlap of POLY to NDT
min. / max. overlap of a POLY to common area of DWELL and NDIFF
min. / max. width of a POLY (gate length)
min. / max. space between POLY and NIMP (drain)
min. extension of a POLY beyond DIFF into field oxide (in W direction)
NIMP and PIMP source/backgate contacts must alternate
and must terminate with PIMP contacts.
min. / max. overlap of NIMP to POLY (source side)
min. / max. width of a PIMP Source (in L direction)
min. / max. width of a PIMP Source (in W direction)
min. / max. space between PIMP Source and POLY
min. / max. overlap of PIMP to POLY (finger ends, in L direction)
min. / max. space between two PIMP Source (in W direction)
min. / max. overlap of SAB to POLY (in L direction)
min. overlap of SAB to POLY (in W direction)
min. / max. extension of SAB beyond POLY into length direction
min. / max. overlap of SAB to NIMP (drain)
Min. space between SAB and CONT
min. / max. space between two CONTs (both source and drain)
PIMP or NIMP end patch must have at least one contact
min. width of a METAL1 (both source and drain)
min. space of METAL1 lines (source to drain)
min. space of SDNW (outer-ring edge) to PW
min. space of SDNW (inner-ring edge) to SDPW
min. width of a SDNW (ISO-ring)
min. width of a NDT in SDNW (ISO-ring)
min. enclosure of NDT by SDNW (ISO-ring)
min. enclosure of DNW by SDNW (outer-ring edge)
min. overlap of DNW (ISO-ring) to SDNW
DUMDWELL in ISO P-SUB must be connected to DWELL body by PDIFF
min. / max. enclosure of NDIFF (drain) by LDMTAG (drain side not facing gate)
min. / max. overlap of PIMP (finger ends) to LDMTAG (in W direction)
102O7a
102Rb
102Rc
100S23a
105E100a
105E24a
3W3aa
3W3ab
3W3ac
100E3a
100E3b
8E3aa
8E3ab
111Ra
6O100a
6O102a
6W6aa
6S8aa
6X3aa
8Raa
8O6aa
7W7aa
7W7ab
7S6aa
7O6aa
7S7aa
47O6aa
47O6ab
47X6aa
47O8aa
47S9aa
9S9aa
9Raa
10W10aa
10S10aa
24S1aa
24S23aa
24W24aa
100W100b
24E100c
24E22aa
22O24a
102Rd
94E3a
94O7a
Layout Rule
(um)
1.28
1.28
0.48
0.55 ≤ # ≤ 0.58
4.82
0.36
0.90
0.68
2.00
2.00
2.00
3.00
0.66
0.50
0.90
0.90
0.18
0.18
0.30
0.10
0.80
0.20
1.70
0.50
0.44
1.00
0.32
0.30
1.00
0.30
0.22
0.25
0.05
0.17
0.28
1.20
0.60
2.00
2.00
6.00
2.00
2.00
1.50
4.50
0.0
0.0
Notes:


SD-NWELL (ISO-ring) must be connected to Drain of nLDMOS transistor.
ISO P-SUB must be connected to Source & P-Body of nLDMOS transistor.
168 of 224
DBH CONFIDENTIAL
47X6aa
47O6aa
47O8aa
47O6ab
6X3aa
6S8aa
94O7a
7O6aa
100E3b
6O102a
9S9aa
8O6aa
7W7ab
3W3aa
7S7aa
94E3a
102O7a
102W102c
47S9aa
100S23a
105E100a
23E102a
100W100b
24E100c
24E100c
7S6aa
102W102a
24S23aa
24W24aa
7W7aa
102W102e
6O100a
3W3ac
102X8a
102W102d
6W6aa
100E3a
3W3ab
24E22aa
102S102f
22O24a
105E24a
24S1aa
169 of 224
DBH CONFIDENTIAL
ISO
P-SUB
ISO-ring
SDNW
(N-type)
Drain
Source
(&Body)
Gate
DWELL
(P-type)
SDPW
(P-type)
ISO P-SUB
(P-type)
Gate
Drain
NDT
(N-type)
ISO
P-SUB
ISO-ring
NDT
(N-type)
DNW
(N-type)
DNW
DIFF
VIA1
SDNW
NIMP
METAL2
NDT
PIMP
DWELL
SAB
NWELL
CONT
SDPW
METAL1
POLY
TGOX50
PCHSTBLK
LDMTAG
170 of 224
DBH CONFIDENTIAL
8.3 12V nLDMOS LSD (nch_ldmls_12v)
Rule No.
Description of key design rule
102W102b
102W102c
102W102d
102W102e
102S102g
23E102a
102X8a
min. / max. width of a DWELL (straight center section of finger)
min. / max. width of a DUMDWELL
min. / max. width of a DWELL (straight section of finger end)
min. / max. width of a DWELL (for 45deg. Edges)
min. / max. space between DWELL to DUMDWELL
min. enclosure of DUMDWELL in P-SUB or ISO P-SUB by SDPW
min. / max. extension of DWELL beyond NIMP (finger ends, in W-direction)
Min. / max. overlap of DWELL (straight center section of finger) to PIMP
(in W direction)
45-degree segments must be used in finger ends for DWELL
DUMDWELL height (in W direction) must be equal to the DWELL height
min. space of NDT to SDPW
min. / max. enclosure of NDT by PCHSTBLK
min. width of a NDIFF to define the width of nLDMOS
min. / max. width of a NDIFF (drain, in L direction)
min. / max. width of a PDIFF (finger ends, in W direction)
min. enclosure of NDIFF by NDT (drain side not facing gate)
min. enclosure of NDIFF by NDT (drain, in W direction)
min. enclosure of NDIFF by NIMP (drain side not facing gate)
min. enclosure of NDIFF by NIMP (drain, in W direction)
Any DIFF must be enclosed by TGOX50 layer
min. / max. overlap of POLY to NDT
min. / max. overlap of a POLY to common area of DWELL and NDIFF
min. / max. width of a POLY (gate length)
min. / max. space between POLY and NIMP (drain)
min. extension of a POLY beyond DIFF into field oxide (in W direction)
NIMP and PIMP source/backgate contacts must alternate
and must terminate with PIMP contacts.
min. / max. overlap of NIMP to POLY (source side)
min. / max. width of a PIMP Source (in L direction)
min. / max. width of a PIMP Source (in W direction)
min. / max. space between PIMP Source and POLY
min. / max. overlap of PIMP to POLY (finger ends, in L direction)
min. / max. space between two PIMP Source (in W direction)
min. / max. overlap of SAB to POLY (in L direction)
min. overlap of SAB to POLY (in W direction)
min. / max. extension of SAB beyond POLY into length direction
min. / max. overlap of SAB to NIMP (drain)
Min. space between SAB and CONT
min. / max. space between two CONTs (both source and drain)
PIMP or NIMP end patch must have at least one contact
min. width of a METAL1 (both source and drain)
min. space of METAL1 lines (source to drain)
min. / max. enclosure of NDIFF (drain) by LDMTAG (drain side not facing gate)
min. / max. overlap of PIMP (finger ends) to LDMTAG (in W direction)
102O7a
102Rb
102Rc
100S23a
105E100a
3W3aa
3W3ab
3W3ac
100E3a
100E3b
8E3aa
8E3ab
111Ra
6O100b
6O102a
6W6ab
6S8ab
6X3aa
8Raa
8O6ab
7W7aa
7W7ab
7S6aa
7O6aa
7S7aa
47O6ac
47O6ab
47X6ab
47O8aa
47S9aa
9S9aa
9Raa
10W10aa
10S10aa
94E3a
94O7a
Layout Rule
(um)
1.28
1.28
0.48
0.55 ≤ # ≤ 0.58
5.22
0.36
0.90
0.68
2.00
2.00
3.00
0.66
0.50
0.90
0.90
0.18
0.18
0.40
0.10
1.00
0.40
1.70
0.60
0.44
1.00
0.32
0.30
1.00
0.40
0.22
0.45
0.05
0.17
0.28
1.20
0.60
0.0
0.0
Note:

P-SUB must be connected to Source & P-Body of nLDMOS transistor.
171 of 224
DBH CONFIDENTIAL
47X6ab
NDT
DWELL
47O6ac
SDPW
47O8aa
47O6ab
6X3aa
6S8ab
POLY
94O7a
100E3b
DIFF
7O6aa
6O102a
NIMP
9S9aa
8O6ab
PIMP
7W7ab
3W3aa
SAB
7S7aa
CONT
7W7aa
94E3a
7S6aa
METAL1
102W102a
102O7a
102W102c
47S9aa
100S23a
105E100a
23E102a
3W3ac
102W102e
6O100b
102X8a
102W102d
TGOX50
PCHSTBLK
100E3a
VIA1
6W6ab
3W3ab
METAL2
LDMTAG
102S102g
P-SUB
SDPW
(P-type)
Drain
Gate
Source
(&Body)
DWELL
(P-type)
Gate
Drain
P-SUB
NDT
(N-type)
P-SUB
(P-type)
172 of 224
DBH CONFIDENTIAL
8.4 12V nLDMOS HSD (nch_ldmhs_12v)
Rule No.
Description of key design rule
102W102b
102W102c
102W102d
102W102e
102S102g
23E102a
102X8a
min. / max. width of a DWELL (straight center section of finger)
min. / max. width of a DUMDWELL
min. / max. width of a DWELL (straight section of finger end)
min. / max. width of a DWELL (for 45deg. Edges)
min. / max. space between DWELL to DUMDWELL
min. enclosure of DUMDWELL in P-SUB or ISO P-SUB by SDPW
min. / max. extension of DWELL beyond NIMP (finger ends, in W-direction)
Min. / max. overlap of DWELL (straight center section of finger) to PIMP
(in W direction)
45-degree segments must be used in finger ends for DWELL
DUMDWELL height (in W direction) must be equal to the DWELL height
min. space of NDT to SDPW
min. / max. enclosure of NDT by PCHSTBLK
min. / max. enclosure of SDNW by PCHSTBLK
min. width of a NDIFF to define the width of nLDMOS
min. / max. width of a NDIFF (drain, in L direction)
min. / max. width of a PDIFF (finger ends, in W direction)
min. enclosure of NDIFF by NDT (drain side not facing gate)
min. enclosure of NDIFF by NDT (drain, in W direction)
min. enclosure of NDIFF by NIMP (drain side not facing gate)
min. enclosure of NDIFF by NIMP (drain, in W direction)
Any DIFF must be enclosed by TGOX50 layer
min. / max. overlap of POLY to NDT
min. / max. overlap of a POLY to common area of DWELL and NDIFF
min. / max. width of a POLY (gate length)
min. / max. space between POLY and NIMP (drain)
min. extension of a POLY beyond DIFF into field oxide (in W direction)
NIMP and PIMP source/backgate contacts must alternate
and must terminate with PIMP contacts.
min. / max. overlap of NIMP to POLY (source side)
min. / max. width of a PIMP Source (in L direction)
min. / max. width of a PIMP Source (in W direction)
min. / max. space between PIMP Source and POLY
min. / max. overlap of PIMP to POLY (finger ends, in L direction)
min. / max. space between two PIMP Source (in W direction)
min. / max. overlap of SAB to POLY (in L direction)
min. overlap of SAB to POLY (in W direction)
min. / max. extension of SAB beyond POLY into length direction
min. / max. overlap of SAB to NIMP (drain)
Min. space between SAB and CONT
min. / max. space between two CONTs (both source and drain)
PIMP or NIMP end patch must have at least one contact
min. width of a METAL1 (both source and drain)
min. space of METAL1 lines (source to drain)
min. space of SDNW (outer-ring edge) to PW
min. space of SDNW (inner-ring edge) to SDPW
min. width of a SDNW (ISO-ring)
min. width of a NDT in SDNW (ISO-ring)
min. enclosure of NDT by SDNW (ISO-ring)
min. enclosure of DNW by SDNW (outer-ring edge)
min. overlap of DNW (ISO-ring) to SDNW
DUMDWELL in ISO P-SUB must be connected to DWELL body by PDIFF
min. / max. enclosure of NDIFF (drain) by LDMTAG (drain side not facing gate)
min. / max. overlap of PIMP (finger ends) to LDMTAG (in W direction)
102O7a
102Rb
102Rc
100S23a
105E100a
105E24a
3W3aa
3W3ab
3W3ac
100E3a
100E3b
8E3aa
8E3ab
111Ra
6O100b
6O102a
6W6ab
6S8ab
6X3aa
8Raa
8O6ab
7W7aa
7W7ab
7S6aa
7O6aa
7S7aa
47O6ac
47O6ab
47X6ab
47O8aa
47S9aa
9S9aa
9Raa
10W10aa
10S10aa
24S1aa
24S23aa
24W24aa
100W100b
24E100c
24E22aa
22O24a
102Rd
94E3a
94O7a
Layout Rule
(um)
1.28
1.28
0.48
0.55 ≤ # ≤ 0.58
5.22
0.36
0.90
0.68
2.00
2.00
2.00
3.00
0.66
0.50
0.90
0.90
0.18
0.18
0.40
0.10
1.00
0.40
1.70
0.60
0.44
1.00
0.32
0.30
1.00
0.40
0.22
0.45
0.05
0.17
0.28
1.20
0.60
2.00
2.00
6.00
2.00
2.00
1.50
4.50
0.0
0.0
Notes:


SD-NWELL (ISO-ring) must be connected to Drain of nLDMOS transistor.
ISO P-SUB must be connected to Source & P-Body of nLDMOS transistor.
173 of 224
DBH CONFIDENTIAL
47X6ab
47O6ac
47O8aa
47O6ab
6X3aa
6S8ab
94O7a
7O6aa
100E3b
6O102a
9S9aa
8O6ab
7W7ab
3W3aa
7S7aa
7W7aa
94E3a
102W102a
24S23aa
102O7a
47S9aa
102W102c
24W24aa
100W100b
24E100c
24E100c
7S6aa
100S23a
105E100a
102W102e
6O100b
23E102a
3W3ac
102X8a
102W102d
6W6ab
100E3a
3W3ab
24E22aa
102S102g
22O24a
105E24a
24S1aa
174 of 224
DBH CONFIDENTIAL
ISO
P-SUB
ISO-ring
SDNWELL
(N-type)
Drain
Source
(&Body)
Gate
DWELL
(P-type)
SDPW
(P-type)
ISO P-SUBI
(P-type)
Gate
Drain
NDT
(N-type)
ISO
P-SUB
ISO-ring
NDT
(N-type)
DNW
(N-type)
DNW
DIFF
VIA1
SDNW
NIMP
METAL2
NDT
PIMP
DWELL
SAB
NWELL
CONT
SDPW
METAL1
POLY
TGOX50
PCHSTBLK
LDMTAG
175 of 224
DBH CONFIDENTIAL
8.5 20V nLDMOS LSD (nch_ldmls_20v)
Rule No.
Description of key design rule
102W102b
102W102c
102W102d
102W102e
102S102h
23E102a
102X8a
min. / max. width of a DWELL (straight center section of finger)
min. / max. width of a DUMDWELL
min. / max. width of a DWELL (straight section of finger end)
min. / max. width of a DWELL (for 45deg. Edges)
min. / max. space between DWELL to DUMDWELL
min. enclosure of DUMDWELL in P-SUB or ISO P-SUB by SDPW
min. / max. extension of DWELL beyond NIMP (finger ends, in W-direction)
Min. / max. overlap of DWELL (straight center section of finger) to PIMP
(in W direction)
45-degree segments must be used in finger ends for DWELL
DUMDWELL height (in W direction) must be equal to the DWELL height
min. space of NDT to SDPW
min. / max. enclosure of NDT by PCHSTBLK
min. width of a NDIFF to define the width of nLDMOS
min. / max. width of a NDIFF (drain, in L direction)
min. / max. width of a PDIFF (finger ends, in W direction)
min. enclosure of NDIFF by SDNW (drain side not facing gate)
min. enclosure of NDIFF by SDNW (drain, in W direction)
min. / max. enclosure of NDIFF by SDNW (drain side facing gate)
min. enclosure of SDNW by NDT (drain side not facing gate)
min. enclosure of SDNW by NDT (drain, in W direction)
min. extension of NDT beyond DIFF (source side, in W direction)
min. enclosure of NDIFF by NIMP (drain)
Any DIFF must be enclosed by TGOX50 layer
min. / max. space of DIFF to NDIFF
min. / max. space of DIFF to SDNW
min. / max. overlap of DIFF to NDT (drain side facing gate)
min. / max. overlap of POLY to DIFF (gate length)
min. extension of a POLY beyond DIFF into field oxide (in W direction)
min. / max. extension of POLY beyond DIFF (in L direction)
min. / max. space between POLY and NDIFF (drain)
min. / max. overlap of a POLY to common area of DWELL and NDIFF
NIMP and PIMP source/backgate contacts must alternate
and must terminate with PIMP contacts.
min. overlap of NIMP to POLY (source side)
min. / max. width of a PIMP Source (in L direction)
min. / max. width of a PIMP Source (in W direction)
min. / max. space between PIMP Source and POLY
min. / max. overlap of PIMP to POLY (finger ends, in L direction)
min. / max. space between two PIMP Source (in W direction)
min. / max. space between two CONTs (both source and drain)
PIMP or NIMP end patch must have at least one contact
min. width of a METAL1 (both source and drain)
min. space of METAL1 lines (source to drain)
min. / max. enclosure of NDIFF (drain) by LDMTAG (drain side not facing gate)
min. / max. enclosure of NDIFF (drain) by LDMTAG (in W direction)
102O7a
102Rb
102Rc
100S23a
105E100a
3W3aa
3W3ad
3W3ac
3E24aa
3E24ab
3E24ac
24E100a
24E100b
100X3a
8E3aa
111Ra
3S3aa
3S24aa
3O100a
6O3aa
6X3aa
6X3ab
6S3aa
6O102a
8Raa
8O6ac
7W7aa
7W7ab
7S6aa
7O6ab
7S7aa
9S9aa
9Raa
10W10aa
10S10aa
94E3a
94E3b
Layout Rule
(um)
1.28
1.28
0.48
0.55 ≤ # ≤ 0.58
5.72
0.36
0.90
0.68
2.00
2.00
3.00
0.76
0.50
0.40
0.40
0.05
0.50
0.50
0.40
0.18
0.60
0.55
0.40
1.20
1.70
0.20
0.40
0.10
1.20
0.44
1.00
0.32
0.60
1.00
0.28
1.20
0.60
0.0
0.0
Note:

P-SUB must be connected to Source & P-Body of nLDMOS transistor.
176 of 224
DBH CONFIDENTIAL
NDT
DWELL
6X3ab
SDPW
6X3aa
SDNW
100X3a 24E100b
6S3aa
POLY
7O6ab
3E24ab
6O102a
DIFF
8O6ac
NIMP
9S9aa
7W7ab
PIMP
3W3aa
7S7aa
94E3a
7W7aa
3S24aa
CONT
7S6aa
METAL1
102W102b
24E100a
3W3ac
102O7a
94E3b
102W102c
102W102e
TGOX50
3E24aa
PCHSTBLK
102X8a
3E24ac
100S23a
105E100a
102W102d
23E102a
3O100a
6O3aa
VIA1
3W3ad
METAL2
3S3aa
LDMTAG
102S102h
P-SUB
SDPW
PW
(P-type)
Drain
SDNW
(N-type)
Gate
Source
(&Body)
DWELL
(P-type)
Gate
Drain
P-SUB
NDT
(N-type)
P-SUB
(P-type)
177 of 224
DBH CONFIDENTIAL
8.6 18V nLDMOS HSD (nch_ldmhs_18v)
Rule No.
Description of key design rule
102W102b
102W102c
102W102d
102W102e
102S102h
23E102a
102X8a
min. / max. width of a DWELL (straight center section of finger)
min. / max. width of a DUMDWELL
min. / max. width of a DWELL (straight section of finger end)
min. / max. width of a DWELL (for 45deg. Edges)
min. / max. space between DWELL to DUMDWELL
min. enclosure of DUMDWELL in P-SUB or ISO P-SUB by SDPW
min. / max. extension of DWELL beyond NIMP (finger ends, in W-direction)
Min. / max. overlap of DWELL (straight center section of finger) to PIMP
(in W direction)
45-degree segments must be used in finger ends for DWELL
DUMDWELL height (in W direction) must be equal to the DWELL height
min. space of NDT to SDPW
min. / max. enclosure of NDT by PCHSTBLK
min. width of a NDIFF to define the width of nLDMOS
min. / max. width of a NDIFF (drain, in L direction)
min. / max. width of a PDIFF (finger ends, in W direction)
min. enclosure of NDIFF by SDNW (drain side not facing gate)
min. enclosure of NDIFF by SDNW (drain, in W direction)
min. / max. enclosure of NDIFF by SDNW (drain side facing gate)
min. enclosure of SDNW by NDT (drain side not facing gate)
min. enclosure of SDNW by NDT (drain, in W direction)
min. extension of NDT beyond DIFF (source side, in W direction)
min. enclosure of NDIFF by NIMP (drain)
Any DIFF must be enclosed by TGOX50 layer
min. / max. space of DIFF to NDIFF
min. / max. space of DIFF to SDNW
min. / max. overlap of DIFF to NDT (drain side facing gate)
min. / max. overlap of POLY to DIFF (gate length)
min. extension of a POLY beyond DIFF into field oxide (in W direction)
min. / max. extension of POLY beyond DIFF (in L direction)
min. / max. space between POLY and NDIFF (drain)
min. / max. overlap of a POLY to common area of DWELL and NDIFF
NIMP and PIMP source/backgate contacts must alternate
and must terminate with PIMP contacts.
min. overlap of NIMP to POLY (source side)
min. / max. width of a PIMP Source (in L direction)
min. / max. width of a PIMP Source (in W direction)
min. / max. space between PIMP Source and POLY
min. / max. overlap of PIMP to POLY (finger ends, in L direction)
min. / max. space between two PIMP Source (in W direction)
min. / max. space between two CONTs (both source and drain)
PIMP or NIMP end patch must have at least one contact
min. width of a METAL1 (both source and drain)
min. space of METAL1 lines (source to drain)
min. space of SDNW (outer-ring edge) to PW
min. space of SDNW (inner-ring edge) to SDPW
min. width of a SDNW (ISO-ring)
min. width of a NDT in SDNW (ISO-ring)
min. enclosure of NDT by SDNW (ISO-ring)
min. enclosure of DNW by SDNW (outer-ring edge)
min. overlap of DNW (ISO-ring) to SDNW
DUMDWELL in ISO P-SUB must be connected to DWELL body by PDIFF
min. / max. enclosure of NDIFF (drain) by LDMTAG (drain side not facing gate)
min. / max. enclosure of NDIFF (drain) by LDMTAG (in W direction)
102O7a
102Rb
102Rc
100S23a
105E100a
3W3aa
3W3ad
3W3ac
3E24aa
3E24ab
3E24ac
24E100a
24E100b
100X3a
8E3aa
111Ra
3S3aa
3S24aa
3O100b
6O3aa
6X3aa
6X3ab
6S3aa
6O102a
8Raa
8O6ac
7W7aa
7W7ab
7S6aa
7O6ab
7S7aa
9S9aa
9Raa
10W10aa
10S10aa
24S1aa
24S23aa
24W24aa
100W100b
24E100c
24E22aa
22O24a
102Rd
94E3a
94E3b
Layout Rule
(um)
1.28
1.28
0.48
0.55 ≤ # ≤ 0.58
5.72
0.36
0.90
0.68
2.00
2.00
3.00
0.76
0.50
0.40
0.40
0.05
0.50
0.50
0.40
0.18
0.60
0.55
0.20
1.20
1.70
0.20
0.40
0.10
1.20
0.44
1.00
0.32
0.60
1.00
0.28
1.20
0.60
2.00
2.00
6.00
2.00
2.00
1.50
4.50
0.0
0.0
Note:


SD-NWELL (ISO-ring) must be connected to Drain of nLDMOS transistor.
ISO P-SUB must be connected to Source & P-Body of nLDMOS transistor.
178 of 224
DBH CONFIDENTIAL
6X3ab
6X3aa
100X3a 24E100b
6S3aa
7O6ab
3E24ab
6O102a
8O6ac
9S9aa
7W7ab
3W3aa
7S7aa
94E3a
94E3b
102W102e
102W102d
3O100a
100W100b
3E24aa
102X8a
3E24ac
100S23a
105E100a
23E102a
24E100c
24E100a
3W3ac
102O7a
102W102c
24E100c
7S6aa
102W102b
24S23aa
24W24aa
7W7aa
3S24aa
6O3aa
3S3aa
102S102h
3W3ad
24E22aa
22O24a
105E24a
24S1aa
179 of 224
DBH CONFIDENTIAL
ISO
P-SUB
ISO-ring
SDNWELL
SDNW
(N-type)
SDPW
(P-type)
Drain
Source
(&Body)
Gate
DWELL
(P-type)
SDNW
(N-type)
ISO P-SUBI
(P-type)
Gate
Drain
ISO
P-SUB
NDT
(N-type)
ISO-ring
NDT
(N-type)
DNW
(N-type)
DNW
DIFF
VIA1
SDNW
NIMP
METAL2
NDT
PIMP
DWELL
SAB
NWELL
CONT
SDPW
METAL1
POLY
TGOX50
PCHSTBLK
LDMTAG
180 of 224
DBH CONFIDENTIAL
8.7 24V nLDMOS LSD (nch_ldmls_24v)
Rule No.
Description of key design rule
102W102b
102W102c
102W102d
102W102e
102S102i
23E102a
102X8a
min. / max. width of a DWELL (straight center section of finger)
min. / max. width of a DUMDWELL
min. / max. width of a DWELL (straight section of finger end)
min. / max. width of a DWELL (for 45deg. Edges)
min. / max. space between DWELL to DUMDWELL
min. enclosure of DUMDWELL in P-SUB or ISO P-SUB by SDPW
min. / max. extension of DWELL beyond NIMP (finger ends, in W-direction)
Min. / max. overlap of DWELL (straight center section of finger) to PIMP
(in W direction)
45-degree segments must be used in finger ends for DWELL
DUMDWELL height (in W direction) must be equal to the DWELL height
min. space of NDT to SDPW
min. / max. enclosure of NDT by PCHSTBLK
min. width of a NDIFF to define the width of nLDMOS
min. / max. width of a NDIFF (drain, in L direction)
min. / max. width of a PDIFF (finger ends, in W direction)
min. enclosure of NDIFF by SDNW (drain side not facing gate)
min. enclosure of NDIFF by SDNW (drain, in W direction)
min. / max. enclosure of NDIFF by SDNW (drain side facing gate)
min. enclosure of SDNW by NDT (drain side not facing gate)
min. enclosure of SDNW by NDT (drain, in W direction)
min. extension of NDT beyond DIFF (source side, in W direction)
min. enclosure of NDIFF by NIMP (drain)
Any DIFF must be enclosed by TGOX50 layer
min. / max. space of DIFF to NDIFF
min. / max. space of DIFF to SDNW
min. / max. overlap of DIFF to NDT (drain side facing gate)
min. / max. overlap of POLY to DIFF (gate length)
min. extension of a POLY beyond DIFF into field oxide (in W direction)
min. / max. extension of POLY beyond DIFF (in L direction)
min. / max. space between POLY and NDIFF (drain)
min. / max. overlap of a POLY to common area of DWELL and NDIFF
NIMP and PIMP source/backgate contacts must alternate
and must terminate with PIMP contacts.
min. overlap of NIMP to POLY (source side)
min. / max. width of a PIMP Source (in L direction)
min. / max. width of a PIMP Source (in W direction)
min. / max. space between PIMP Source and POLY
min. / max. overlap of PIMP to POLY (finger ends, in L direction)
min. / max. space between two PIMP Source (in W direction)
min. / max. space between two CONTs (both source and drain)
PIMP or NIMP end patch must have at least one contact
min. width of a METAL1 (both source and drain)
min. space of METAL1 lines (source to drain)
min. / max. enclosure of NDIFF (drain) by LDMTAG (drain side not facing gate)
min. / max. enclosure of NDIFF (drain) by LDMTAG (in W direction)
102O7a
102Rb
102Rc
100S23a
105E100a
3W3aa
3W3ad
3W3ac
3E24aa
3E24ab
3E24ac
24E100a
24E100b
100X3a
8E3aa
111Ra
3S3ab
3S24ab
3O100a
6O3aa
6X3aa
6X3ac
6S3ab
6O102a
8Raa
8O6ac
7W7aa
7W7ab
7S6aa
7O6ab
7S7aa
9S9aa
9Raa
10W10aa
10S10aa
94E3a
94E3b
Layout Rule
(um)
1.28
1.28
0.48
0.55 ≤ # ≤ 0.58
6.02
0.36
0.90
0.68
2.00
2.00
3.00
0.76
0.50
0.40
0.40
0.05
0.50
0.50
0.40
0.18
0.90
0.85
0.40
1.20
1.70
0.40
0.50
0.10
1.20
0.44
1.00
0.32
0.60
1.00
0.28
1.20
0.60
0.0
0.0
Note:

P-SUB must be connected to Source & P-Body of nLDMOS transistor.
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NDT
DWELL
6X3ac
SDPW
6X3aa
SDNW
100X3a 24E100b
6S3ab
POLY
7O6ab
3E24ab
6O102a
DIFF
8O6ac
NIMP
9S9aa
7W7ab
PIMP
3W3aa
7S7aa
94E3a
7W7aa
3S24ab
CONT
7S6aa
METAL1
102W102b
24E100a
3W3ac
102O7a
94E3b
102W102c
102W102e
TGOX50
3E24aa
PCHSTBLK
102X8a
3E24ac
100S23a
105E100a
102W102d
23E102a
3O100a
6O3aa
VIA1
3W3ad
METAL2
3S3ab
LDMTAG
102S102i
P-SUB
SDPW
PW
(P-type)
Drain
SDNW
(N-type)
Gate
Source
(&Body)
DWELL
(P-type)
Gate
Drain
P-SUB
NDT
(N-type)
P-SUB
(P-type)
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8.8 30V nLDMOS LSD (nch_ldmls_30v)
Rule No.
Description of key design rule
102W102b
102W102c
102W102d
102W102e
102S102j
23E102a
102X8a
min. / max. width of a DWELL (straight center section of finger)
min. / max. width of a DUMDWELL
min. / max. width of a DWELL (straight section of finger end)
min. / max. width of a DWELL (for 45deg. Edges)
min. / max. space between DWELL to DUMDWELL
min. enclosure of DUMDWELL in P-SUB or ISO P-SUB by SDPW
min. / max. extension of DWELL beyond NIMP (finger ends, in W-direction)
Min. / max. overlap of DWELL (straight center section of finger) to PIMP
(in W direction)
45-degree segments must be used in finger ends for DWELL
DUMDWELL height (in W direction) must be equal to the DWELL height
min. space of NDT to SDPW
min. / max. enclosure of NDT by PCHSTBLK
min. width of a NDIFF to define the width of nLDMOS
min. / max. width of a NDIFF (drain, in L direction)
min. / max. width of a PDIFF (finger ends, in W direction)
min. enclosure of NDIFF by SDNW (drain side not facing gate)
min. enclosure of NDIFF by SDNW (drain, in W direction)
min. / max. enclosure of NDIFF by SDNW (drain side facing gate)
min. enclosure of SDNW by NDT (drain side not facing gate)
min. enclosure of SDNW by NDT (drain, in W direction)
min. extension of NDT beyond DIFF (source side, in W direction)
min. enclosure of NDIFF by NIMP (drain)
Any DIFF must be enclosed by TGOX50 layer
min. / max. space of DIFF to NDIFF
min. / max. space of DIFF to SDNW
min. / max. overlap of DIFF to NDT (drain side facing gate)
min. / max. overlap of POLY to DIFF (gate length)
min. extension of a POLY beyond DIFF into field oxide (in W direction)
min. / max. extension of POLY beyond DIFF (in L direction)
min. / max. space between POLY and NDIFF (drain)
min. / max. overlap of a POLY to common area of DWELL and NDIFF
NIMP and PIMP source/backgate contacts must alternate
and must terminate with PIMP contacts.
min. overlap of NIMP to POLY (source side)
min. / max. width of a PIMP Source (in L direction)
min. / max. width of a PIMP Source (in W direction)
min. / max. space between PIMP Source and POLY
min. / max. overlap of PIMP to POLY (finger ends, in L direction)
min. / max. space between two PIMP Source (in W direction)
min. / max. space between two CONTs (both source and drain)
PIMP or NIMP end patch must have at least one contact
min. width of a METAL1 (both source and drain)
min. space of METAL1 lines (source to drain)
min. / max. enclosure of NDIFF (drain) by LDMTAG (drain side not facing gate)
min. / max. enclosure of NDIFF (drain) by LDMTAG (in W direction)
102O7a
102Rb
102Rc
100S23a
105E100a
3W3aa
3W3ad
3W3ac
3E24aa
3E24ab
3E24ad
24E100a
24E100b
100X3a
8E3aa
111Ra
3S3ac
3S24ac
3O100b
6O3aa
6X3aa
6X3ad
6S3ac
6O102a
8Raa
8O6ac
7W7aa
7W7ab
7S6aa
7O6ab
7S7aa
9S9aa
9Raa
10W10aa
10S10aa
94E3a
94E3b
Layout Rule
(um)
1.28
1.28
0.48
0.55 ≤ # ≤ 0.58
6.32
0.36
0.90
0.68
2.00
2.00
3.00
0.76
0.50
0.40
0.40
0.40
0.50
0.50
0.40
0.18
1.20
0.80
0.20
1.20
1.70
0.60
0.60
0.10
1.20
0.44
1.00
0.32
0.60
1.00
0.28
1.20
0.60
0.0
0.0
Note:

P-SUB must be connected to Source & P-Body of nLDMOS transistor.
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DBH CONFIDENTIAL
NDT
DWELL
6X3ad
SDPW
6X3aa
SDNW
100X3a 24E100b
6S3ac
POLY
7O6ab
3E24ab
6O102a
DIFF
8O6ac
NIMP
9S9aa
7W7ab
PIMP
3W3aa
7S7aa
94E3a
7W7aa
3S24ac
CONT
7S6aa
METAL1
102W102b
24E100a
3W3ac
102O7a
94E3b
102W102c
102W102e
TGOX50
3E24aa
PCHSTBLK
102X8a
3E24ad
100S23a
105E100a
102W102d
23E102a
3O100b
6O3aa
VIA1
3W3ad
METAL2
3S3ac
LDMTAG
102S102j
P-SUB
SDPW
PW
(P-type)
Drain
SDNW
(N-type)
Gate
Source
(&Body)
DWELL
(P-type)
Gate
Drain
P-SUB
NDT
(N-type)
P-SUB
(P-type)
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DBH CONFIDENTIAL
9. I/O ESD Protection Circuit Design and Layout Guideline
9.1 1.8V & 5.0V ESD Protection Device
There are several kinds of I/O devices.
Component Description
Name
1.8V I/O NMOS
1.8V I/O PMOS
5.0V I/O NMOS
5.0V I/O PMOS
1.8V Power Protection NMOS
5.0V Power Protection NMOS
nch_io_1p8v
pch_io_1p8v
nch_io_5p0v
pch_io_5p0v
nch_pp_1p8v
nch_pp_5p0v
Remark
1.8V I/O NMOS
nch_io_1p8v_4t
4 terminal(Drain / Gate / Source / Bulk)
1.8V I/O PMOS
pch_io_1p8v_5t
5 terminal(Drain / Gate / Source / Bulk / P-sub)
5.0V I/O NMOS
nch_io_5p0v_4t
4 terminal(Drain / Gate / Source / Bulk)
5.0V I/O PMOS
pch_io_5p0v_5t
5 terminal(Drain / Gate / Source / Bulk / P-sub)
1.8V Power Protection NMOS
nch_pp_1p8v_4t
4 terminal(Drain / Gate / Source / Bulk)
5.0V Power Protection NMOS
nch_pp_5p0v_4t
4 terminal(Drain / Gate / Source / Bulk)
1.8V isolated I/O NMOS
nch_io_iso_1p8v_6t
6 terminal(Drain / Gate / Source / Bulk / ISO / P-sub)
1.8V isolated I/O PMOS
pch_io_iso_1p8v_5t
5 terminal(Drain / Gate / Source / ISO / P-sub)
5.0V isolated I/O NMOS
nch_io_iso_5p0v_6t
6 terminal(Drain / Gate / Source / Bulk / ISO / P-sub)
5.0V isolated I/O PMOS
1.8V isolated Power Protection
NMOS
5.0V isolated Power Protection
NMOS
pch_io_iso_5p0v_5t
5 terminal(Drain / Gate / Source / ISO / P-sub)
nch_pp_iso_1p8v_6t
6 terminal(Drain / Gate / Source / Bulk / ISO / P-sub)
nch_pp_iso_5p0v_6t
6 terminal(Drain / Gate / Source / Bulk / ISO / P-sub)
2 terminal(Drain / Gate, Source and Bulk)
Note :
The purpose of the 2-termainal devices is used for foundry’s own I/O library.
The purpose of the 4-termainal and 5-terminal devices is used for customer’s own I/O library.
The rule of isolated I/O devices must refer to 9. CMOS & I/O Isolation.
In isolated I/O devices , the inside of isolation ring should follow the rules of nch_io_1p8v_4t,
pch_io_1p8v_5t, nch_io_5p0v_4t, pch_io_5p0v_5t, nch_pp_1p8v_4t, nch_pp_5p0v_4t
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1)For 5.0V I/O NMOS (nch_io_5p0v)
In this structure, SAB on the drain side needs to overlap the POLY Gate by 0.05um.
Note) nch_io_5p0v must be enclosed by SDPW.
2) For 1.8V I/O NMOS (nch_io_1p8v)
In this structure, SAB on the drain side needs to overlap the POLY Gate by 0.05um.
Note) nch_io_1p8v must be enclosed by PWELL.
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DBH CONFIDENTIAL
3) For 5V I/O PMOS (pch_io_5p0v)
In this structure, SAB on the drain side needs to overlap the POLY Gate by 0.05um.
Note) pch_io_5p0v must be enclosed by SDNW.
4) For 1.8V I/O PMOS (pch_io_1p8v)
In this structure, SAB on the drain side needs to overlap the POLY Gate by 0.05um.
Note) pch_io_1p8v must be enclosed by NWELL.
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DBH CONFIDENTIAL
5) For 5V Power Protection NMOS (nch_pp_5p0v)
In these structures, it is recommended that SAB fully covers the un-contacted Gate and Source/Drain. But CONTs
must be salicided.
Note) nch_pp_5p0v must be enclosed by SDPW.
6) For 1.8V Power Protection NMOS (nch_pp_1p8v)
In these structures, it is recommended that SAB fully covers the un-contacted Gate and Source/Drain. But CONTs
must be salicided.
Note) nch_pp_1p8v must be enclosed by PWELL.
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DBH CONFIDENTIAL

I/O ESD Protection Design Rule
(a)5.0V ESD protection Devices [ unit : um ] (IO50 ; IO50)
(a-1) 5.0V NMOS (nch_io_5p0v)
Rule No.
IO50.a1
IO50.b1
Description
IO50.m1
Primary Protection
Min. Gate Length (Lg)
Min. Total Finger Width
(Except for CDM device)
Unit finger width of NMOS
(Except for CDM device)
Salicide Block
Min. SAB to POLY Space (X)
Overlap of SAB to DIFF edge (Y)
Overlap of SAB to POLY
SAB to CONT spacing
CONT spacing to POLY
in Source part
DIFF overlap of Source CONT
Min. DIFF overlap of Source CONT in the direction of parallel
to Transistor Channel
Isolation Resistor
IO50.n1
# of CONT
IO50.o1
IO50.p1
IO50.q1
IO50.r1
IO50.s1
Min. metal width in drain side of ESD devices
Min. metal width connecting PAD
Min. power metal ring width
ESDMY to PDIFF(NMOS) or NDIFF(PMOS) space
ESDMY for DRC & LVS
IO50.c1
IO50.d1
IO50.e1
IO50.f1
IO50.g1
IO50.h1
IO50.i1
IO50.j1
IO50.k1
IO50.l1
5.0V NMOS
(nch_io_5p0v)
GGMOS
0.6
420
20 ~ 60
Drain only
0.78
Y  1.0
Overlap by 0.05
0.22
0.5
0.5
1.0 + 0.22
Minimum 200 ohm
As many as possible
(DC 100mA capable)
2.0
20
50
0
ALL
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DBH CONFIDENTIAL
(a-2) 5.0V NMOS for Power Protection (nch_pp_5p0v)
Rule No.
Description
IO50.a2
IO50.b2
IO50.c2
IO50.d2
IO50.e2
IO50.f2
IO50.g2
Primary Protection
Min. Gate Length (Lg)
Min. Total Finger Width
Unit finger width of NMOS
Salicide Block
Min. SAB to POLY Space (X) in Drain part
Overlap of SAB to DIFF edge (Y)
IO50.h2
Overlap of SAB to POLY
IO50.i2
IO50.m2
SAB to CONT spacing
CONT spacing to POLY
in Source part
DIFF overlap of Source CONT
Min. DIFF overlap of Source CONT in the direction of parallel
to Transistor Channel
Isolation Resistor
IO50.n2
# of CONT
IO50.o2
IO50.p2
IO50.q2
IO50.r2
IO50.s2
IO50.t2
Min. metal width in drain side of ESD devices
Min. metal width connecting PAD
Min. power metal ring width
ESDMY to PDIFF(NMOS) or NDIFF(PMOS) space
ESDMY for DRC & LVS
POW_PRO for DRC & LVS
IO50.j2
IO50.k2
IO50.l2
5.0V NMOS
for Power
Protection
(nch_pp_5p0v)
GGMOS
0.6
420
20 ~ 60
Drain and Source
0.78
Y  1.0
Completely
cover POLY
0.22
0.75
0.75
1.0 + 0.22
Minimum 200 ohm
As many as possible
(DC 100mA capable)
2.0
20
50
0
ALL
0
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DBH CONFIDENTIAL
(a-3) 5.0V PMOS (pch_io_5p0v)
Rule No.
IO50.a3
IO50.b3
IO50.c3
IO50.d3
IO50.e3
IO50.f3
IO50.g3
IO50.h3
IO50.i3
Description
IO50.m3
Primary Protection
Min. Gate Length (Lg)
Min. Total Finger Width
Unit finger width of PMOS
Salicide Block
Min. SAB width (X)
Overlap of SAB to DIFF edge (Y)
Overlap of SAB to POLY
SAB to CONT spacing
CONT spacing to POLY
in Source part
DIFF overlap of Source CONT
Min. DIFF overlap of Source CONT in the direction of parallel to
Transistor Channel
Isolation Resistor
IO50.n3
# of CONT
IO50.o3
IO50.p3
IO50.q3
IO50.r3
IO50.s3
Min. metal width in drain side of ESD devices
Min. metal width connecting PAD
Min. power metal ring width
ESDMY to PDIFF(NMOS) or NDIFF(PMOS) space
ESDMY for DRC & LVS
IO50.j3
IO50.k3
IO50.l3
5.0V PMOS
(pch_io_5p0v)
GPMOS
0.6
600
20 ~ 60
Drain only
0.78
Y  1.0
Overlap by 0.05
0.22
0.5
0.5
1.0 + 0.22
Minimum 200 ohm
As many as possible
(DC 100mA capable)
2.0
20
50
0
ALL
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DBH CONFIDENTIAL
(b) 1.8V ESD protection Devices [ unit : um ] (IO18 ; IO18)
(b-1) 1.8V NMOS (nch_io_1p8v)
Rule No.
Description
IO18.a1
IO18.b1
IO18.c1
IO18.d1
IO18.e1
IO18.f1
IO18.g1
IO18.h1
IO18.i1
Primary Protection
Min. Gate Length (Lg)
Min. Total Finger Width (Except for CDM device)
Unit finger width of NMOS (Except for CDM device)
Salicide Block
Min. SAB width (X)
Overlap of SAB to DIFF edge (Y)
Overlap of SAB to POLY
SAB to CONT spacing
CONT spacing to POLY
in Source part
DIFF overlap of Source CONT
Min. DIFF overlap of Source CONT in the direction of parallel to
Transistor Channel
Isolation Resistor
IO18.j1
IO18.k1
IO18.l1
IO18.m1
IO18.n1
# of CONT
IO18.o1
IO18.p1
IO18.q1
IO18.r1
IO18.s1
Min. metal width in drain side of ESD devices
Min. metal width connecting PAD
Min. power metal ring width
ESDMY to PDIFF(NMOS) or NDIFF(PMOS) space
ESDMY for DRC & LVS
1.8V NMOS
(nch_io_1p8v)
GGMOS
0.25
420
20 ~ 60
Drain only
0.78
Y  1.0
Overlap by 0.05
0.22
0.5
0.5
1.0 + 0.22
Minimum 200 ohm
As many as possible (DC
100mA capable)
2.0
20
50
0
ALL
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DBH CONFIDENTIAL
(b-2) 1.8V NMOS for Power Protection (nch_pp_1p8v)
Rule No.
Description
IO18.a2
IO18.b2
IO18.c2
IO18.d2
IO18.e2
IO18.f2
IO18.g2
Primary Protection
Min. Gate Length (Lg)
Min. Total Finger Width
Unit finger width of NMOS
Salicide Block
Min. SAB to POLY Space (X) in Drain part
Overlap of SAB to DIFF edge (Y)
IO18.h2
Overlap of SAB to POLY
IO18.i2
IO18.m2
SAB to CONT spacing
CONT spacing to POLY
in Source part
DIFF overlap of Source CONT
Min. DIFF overlap of Source CONT in the direction of parallel to
Transistor Channel
Isolation Resistor
IO18.n2
# of CONT
IO18.o2
IO18.p2
IO18.q2
IO18.r2
IO18.s2
IO18.t2
Min. metal width in drain side of ESD devices
Min. metal width connecting PAD
Min. power metal ring width
ESDMY to PDIFF(NMOS) or NDIFF(PMOS) space
ESDMY for DRC & LVS
POW_PRO for DRC & LVS
IO18.j2
IO18.k2
IO18.l2
1.8V NMOS
for Power
Protection
(nch_pp_1p8v)
GGMOS
0.25
420
20 ~ 60
Drain and Source
0.78
Y  1.0
Completely
cover POLY
0.22
0.75
0.75
1.0 + 0.22
Minimum 200 ohm
As many as possible (DC
100mA capable)
2.0
20
50
0
ALL
0
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DBH CONFIDENTIAL
(b-3) 1.8V PMOS (pch_io_1p8v)
Rule No.
Description
IO18.a3
IO18.b3
IO18.c3
IO18.d3
IO18.e3
IO18.f3
IO18.g3
IO18.h3
IO18.i3
IO18.m3
Primary Protection
Min. Gate Length (Lg)
Min. Total Finger Width
Unit finger width of PMOS
Salicide Block
Min. SAB width (X)
Overlap of SAB to DIFF edge (Y)
Overlap of SAB to POLY
SAB to CONT spacing
CONT spacing to POLY
in Source part
DIFF overlap of Source CONT
Min. DIFF overlap of Source CONT in the direction of parallel to
Transistor Channel
Isolation Resistor
IO18.n3
# of CONT
IO18.o3
IO18.p3
IO18.q3
IO18.r3
IO18.s3
Min. metal width in drain side of ESD devices
Min. metal width connecting PAD
Min. power metal ring width
ESDMY to PDIFF(NMOS) or NDIFF(PMOS) space
ESDMY for DRC & LVS
IO18.j3
IO18.k3
IO18.l3
1.8V PMOS
(pch_io_1p8v)
GPMOS
0.25
600
20 ~ 60
Drain only
0.78
Y  1.0
Overlap by 0.05
0.22
0.5
0.5
1.0 + 0.22
Minimum 200 ohm
As many as possible
(DC 100mA capable)
2.0
20
50
0
ALL
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DBH CONFIDENTIAL
9.2 7V ESD Protection Device (esd_hv_pig_7v)
Rule No.
Description
IO70.a1
Primary Protection
IO70.b1
Min. Gate Length (Lg)
7.0V NMOS using pig structure
(esd_hv_pig_7v)
GGMOS
2
IO70.c1
Min. Total Finger Width
IO70.d1
Unit finger width of NMOS
IO70.e1
Salicide Block
IO70.f1
Min. SAB to POLY Space (X) in Drain part
IO70.g1
Overlap of SAB to DIFF edge (Y)
IO70.h1
Overlap of SAB to POLY
IO70.i1
SAB to CONT spacing
0.22
IO70.j1
CONT spacing to POLY in Source part
1.27
IO70.k1
0.75
IO70.m1
DIFF overlap of Source CONT
Min. DIFF overlap of Source CONT in the direction
of parallel to Transistor Channel
Isolation Resistor
IO70.n1
# of CONT
IO70.o1
Min. metal width in drain side of ESD devices
2.0
IO70.p1
Min. metal width connecting PAD
20
IO70.q1
Min. power metal ring width
50
IO70.r1
ESDMY to PDIFF(NMOS) space
0
IO70.s1
ESDMY for DRC & LVS
ALL
IO70.t1
Min. / Max. SAB to NIMP spacing
Min. / Max. length of PIMP between poly and
source
Min. / Max. PIMP between poly and source to NIMP
space
Min. / Max. overlap of poly to PIMP
0.53
IO70.l1
IO70.u1
IO70.v1
IO70.w1
300
20 ~ 60
Drain and Source
1.95
Y  2.0
Completely cover POLY
2.0 + 0.22
Minimum 200 ohm
As many as possible (DC 100mA capable)
0.74
0
0.22
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9.3 7V ESD Protection Device (esd_hv_gc_7v)
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9.4 12V ESD Protection Device (esd_hv_12v)
Rule No.
3W3j
3S3b
Description of key design rule
min. width of a DIFF to define the width of esd_hv_12v
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
Layout Rule
(um)
30.00
0.42
6W6s
min. width of a POLY to define the channel length of esd_hv_12v
0.80
47O6a
min. / max. overlap of SAB to POLY
0.20
107O6a
min. / max. overlap of SDBLK to POLY
0.18
47X6d
min. extension of SAB beyond POLY into length direction
1.50
107X6c
min. extension of SDBLK beyond POLY into length direction
1.40
107X3a
min. extension of SDBLK beyond DIFF into field
0.18
3W3n
min. total finger width of esd_hv_12v
900.00
min. enclosure of SDNW by PCHSTBLK (In esd_hv_12v)
2.00
3O47a
min./ max. overlap of SAB to DIFF edge
2.00
3O107a
min./ max. overlap of SDBLK to DIFF edge
1.90
9S6b
min. space between CONT on DIFF and POLYGATE in source of esd_hv_12v
0.50
9E3c
min. enclosure of DIFF CONT by DIFF in source of esd_hv_12v
0.50
24E105b
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SDNW
POLY
107X3a
9S6b
DIFF
3O107a
3O47a
NIMP
107O6a
3S3b
6W6s
PIMP
107X6c
9E3c
CONT
47X6d
47O6a
TGOX50
24E105b
SAB
SDBLK
PCHSTBLK
ESDMY
Backgate
Source
Drain
HVPLDD
NDIFF
N+
N+
HVPLDD
P+
P+
PDIFF
MET1
PMD
SDNW
STI
`
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9.5 12V ESD Protection Device (esd_hv_gg_12v)

esd_hv_gg_12v for 12V ESD Protection Device is composed of 2stack of esd_hv_gg_12v_lvs
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9.6 12V ESD Protection Device (esd_hv_gc_12v)

esd_hv_gc_12v for 12V ESD Protection Device is composed of 2stack of esd_hv_gc_v12_lvs.
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9.7 20V ESD Protection Device (esd_hv_gg_20v)

esd_hv_gg_20v for 20V ESD Protection Device is composed of 4stack of esd_hv_gg_20v_lvs
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9.8 20V ESD Protection Device (esd_hv_gc_20v)

esd_hv_gc_20v for 20V ESD Protection Device is composed of 3stack of esd_hv_gc_20v_lvs.
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9.9 24V ESD Protection Device (esd_hv_gc_24v)

esd_hv_gc_24v for 24V ESD Protection Device is composed of 3stack of esd_hv_gc_24v_1_lvs.
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9.10 20V and 24V ESD Protection Device (esd_hv_24v)
Rule No.
3W3l
3S3b
6W6u
3E23o
3S3p
6X3i
23S24a
23S24b
24O22d
24X22a
3W3o
24E105c
47X6e
47O6b
3O47b
9S6c
9E3d
6O23c
Description of key design rule
min. width of a DIFF to define the width of esd_hv_24v
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to PDIFF)
(inside TGOX50)
min. width of a POLYGATE to define the channel length of esd_hv_24v
min. enclosure of PDIFF of drain by SDPW not facing gate (V20, V30, no tag)
min. / max. space of DIFF for channel to DIFF for drain
min. / max. extension of POLY beyond channel active into drain direction
min. space of SDPW to SDNW not facing gate
min. / max. space of SDPW to SDNW facing gate
min. overlap of DNW to SDNW
min. extension of SDNW beyond DNW
min. total finger width of esd_hv_24v
min. enclosure of SDNW by PCHSTBLK (In esd_hv_24v)
min. extension of SAB beyond POLY into length direction
min. / max. overlap of SAB to POLY
min./ max. overlap of SAB to DIFF edge
min. space between CONT on DIFF and POLYGATE in source of esd_hv_24v
Layout Rule
(um)
60.00
0.42
2.7
1.00
0.60
0.30
0.00
0.00
1.80
1.50
2160.00
2.00
2.3
0.22
2.00
0.50
min. enclosure of DIFF CONT by DIFF in source of esd_hv_24v
0.50
min. / max. overlap of SDPW to Poly
0.7
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SDNW
SDPW
6O23c
23S24b
9S6c
3S3b
POLY
3O47b
23S24a
DIFF
6X3i
6W6u
9E3d
47X6e
3S3p
24X22a
3E23o
NIMP
PIMP
CONT
47O6b
24O22d
24E105c
DNW
TGOX50
ESDMY
PCHSTB
LK
SAB
Backgate
Source
Drain
NDIFF
N+
P+
P+
PDIFF
MET1
PMD
SDNW
SDPW
STI
DNW
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9.11 24V ESD Protection Device (esd_hv_gg_24v)

esd_hv_gg_24v for 24V ESD Protection Device is composed of 5stack of single stack esd_hv_gc_24v_lvs + 4stack
esd_hv_gg_24v_lvs.
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9.12 30V ESD Protection Device (esd_hv_gg_30v)

esd_hv_gg_30v for 30V ESD Protection Device is composed of 6stack of single stack esd_hv_gc_30v_lvs + 5stack
esd_hv_gg_30v_lvs
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9.13 30V ESD Protection Device (esd_hv_gc_30v)

esd_hv_gc_30v for 30V ESD Protection Device is composed of 4stack of esd_hv_gc_30v_1_lvs.
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9.14 NSD-PWELL Diode (dio_nsd_pw_esd)
Rule No.
Layout
Rule[um]
0.12
Description of key design rule
min. enclosure of PDIFF by PW
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to
PDIFF) (Outside TGOX50)
min. enclosure of NDIFF (in PW or SDPW) by NIMP
min. enclosure of (PW or SDPW) pick-up PDIFF by PIMP
3E1a
3S3a
8E3a
7E3b
0.28
0.18
0.02
PWELL
7E3b
DIFF
NIMP
3S3a
PIMP
8E3a
3E1a
CONT
TGOX50
Anode
Cathode
Anode
NDIFF
PDIFF
MET1
PMD
STI
PWELL
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9.15 PSD-NWELL Diode (dio_psd_nw_esd)
Rule No.
Layout
Rule[um]
0.12
Description of key design rule
min. enclosure of NDIFF by NW
min. space between two DIFF (NDIFF to NDIFF, PDIFF to PDIFF, NDIFF to
PDIFF) (Outside TGOX50)
min. enclosure of PDIFF (in NW or SDNW) by PIMP
min. enclosure of (NW or SDNW) pick-up NDIFF by NIMP
3E2a
3S3a
7E3a
8E3b
0.28
0.18
0.02
NWELL
8E3b
DIFF
NIMP
3S3a
PIMP
7E3a
3E2a
CONT
TGOX50
Cathode
Anode
Cathode
NDIFF
PDIFF
MET1
PMD
STI
NWELL
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9.16 ESD Protection Diode (dio_hv_esd)
Rule No.
Description of key design rule
Layout Rule[um]
3E23p
min. / max. enclosure of PDIFF by SDPW (exception : 45deg. Edges)
1.1
3E24q
min. / max. enclosure of NDIFF by SDNW (exception : 45deg. Edges)
1.1
7E3e
min. enclosure of PDIFF (in PW or SDPW) by PIMP
0.18
8E3f
min. enclosure of NDIFF (in NW or SDNW) by NIMP
0.18
23S24n
min. / max. space of SDNW to SDPW
0
3E24o
min. enclosure of NDIFF by SDNW in outside
2
3E105a
min. enclosure of NDIFF by PCHSTBLK
3.5
3W3m
min. / max. Cutting inner corner of NDIFF, PDIFF (for 45deg. Edges)
0.3
3E68a
min. enclosure of NDIFF by ESDMY in outside
3.5
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10. CMOS & I/O Isolation
10.1 Isolating SDNW ring (nch_svt_iso_5p0v, pch_svt_iso_5p0v, nch_io_iso_5p0v_6t, pch_io_iso _5p0v_5t,
nch_pp_iso_5p0v_6t)
Rule No.
Description of key design rule
Layout Rule
(um)
min. width of SDNW for isolation guard ring (exception ; nch_ee_5p0v_to, esd_gc_7v,
esd_gc_12v, esd_gc_20v, esd_gc_24v, esd_gc_30v, esd_hv_gg_12v,
esd_hv_gg_20v, esd_hv_gg_24v, esd_hv_gg_30v)
24W24c
105W105a
24S105a
23S24l
24X22a
24O22a
105Ra


min. width of PCHSTBLK (In ISO_V30)
min. space of SDNW for isolation guard ring to PCHSTBLK (In ISO_V30)
min. space of SDPW outside ISO_V30 to SDNW inside ISO_V30
min. extension of SDNW beyond DNW
min. overlap of DNW to SDNW
ISO_V30 must include PCHSTBLK.
3.50
1.50
0.00
1.50
1.50
2.00
Isolation ring must be biased such that the potential difference between NDIFF(source, drain) and the isolation ring
does not exceed 5.5V (nch_svt_iso_5p0v) under all operating conditions.
All SDNW regions (which are backgate of PMOS) should be tied to the same potential which is identical to the
isolation ring potential.
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SDNW
POLY
DIFF
24S105a
NIMP
24O22a
PIMP
CONT
SDPW
24X22a
DNW
PCHSTBLK
105W105a
TGOX50
Iso_ring
B/G
S/D
S/D
B/G
S/D
S/D
B/G
S/D
S/D
Iso_ring
P-sub
105W105a
SDNW
(N-type)
SDPW (P-type)
SDNW (N-type)
SDNW
(N-type)
SDPW (P-type)
SDPW
(P-type)
DNW (N-type)
NDIFF
PDIFF
MET1
PMD
STI
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10.2 Isolating NWELL ring (nch_svt_iso_1p8v, pch_svt_iso_1p8v, nch_io_iso_1p8v_6t, pch_io_iso_1p8v_5t,
nch_pp_iso_1p8v_6t)
Rule No.
Description of key design rule
2W2c
105W105a
2S105a
1S2f
23S2h
22X2a
22O2a
105Ra
min. width of NWELL for isolation guard ring
min. width of PCHSTBLK (In ISO_V30)
min. space of NWELL for isolation guard ring to PCHSTBLK (In ISO_V30)
min. space of PWELL outside ISO_V30 to NWELL inside ISO_V30
min. space of SDPW outside ISO_V30 to NWELL inside ISO_V30
min. extension of NW beyond DNW
min. overlap of DNW to NW
ISO_V30 must include PCHSTBLK.


Layout Rule
(um)
3.50
1.50
0.00
1.50
1.50
1.50
2.00
Isolation ring must be biased such that the potential difference between NDIFF(source, drain) and the isolation ring
does not exceed 1.98V(nch_svt_iso_1p8v) / 5.5V (nch_svt_iso_5p0v) under all operating conditions.
All NWELL and SDNW regions (which are backgate of PMOS) should be tied to the same potential which is identical
to the isolation ring potential.
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NWELL
POLY
DIFF
NIMP
2S105a
22O2a
PIMP
CONT
PWELL
22X2a
DNW
PCHSTBLK
105W105a
Iso_ring
B/G
S/D
S/D
B/G
S/D
S/D
B/G
S/D
S/D
Iso_ring
P-sub
105W105a
NWELL
(N-type)
PWELL (P-type)
NWELL (N-type)
NWELL
(N-type)
PWELL (P-type)
SDPW
(P-type)
DNW (N-type)
NDIFF
PDIFF
MET1
PMD
STI
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11. Field Transistor
11.1 20V P-Channel Field Transistor (pch_des_ftr_20v)
Rule No.
23W23b
23S23g
3S23c
3E23j
23E22b
3E24c
7E3d
6X23a
7E6b
6S3c
6O23b
24X22a
24O22a
23S105a
23S24j
24S105b
23Re
105Na
Description of key design rule
min. width of a SDPW to define the width of Field PMOS
min. space between two SDPWs in channel region to define channel length of Field
PMOS
min. space of SDPW to NDIFF (backgate)
min. / max. enclosure of PDIFF for source/drain by SDPW
min. enclosure of SDPW by DNW
min. enclosure of NDIFF by SDNW
min. enclosure of PDIFF by PIMP
min. extension of a POLY beyond SDPW into width direction
min. enclosure of a common area of POLY and PCHSTBLK by PIMP
min. / max. space of a PDIFF for source/drain to POLY
min. / max. overlap of a POLY to SDPW
min. extension of SDNW beyond DNW
min. overlap of DNW to SDNW
min. / max. space of a SDPW to PCHSTBLK
min. / max. space of a SDPW to SDNW not facing gate
min. / max. space of a SDNW to PCHSTBLK
SDPW must be enclosed by DNW
This field transistor is only provided for EEPROM IP library.
Layout Rule
(um)
5.00
3.00
1.00
0.40
2.00
1.00
0.18
0.20
0.18
0.20
0.20
1.50
2.00
0.00
0.00
0.00
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SDNW
7E3d
7E6b
SDPW
23S24j
23S105a
3S23c
POLY
23S23g
3E24c
24X22a
6S3c
3E23j
6O23b
DIFF
NIMP
PIMP
24O22a
6X23a
24S105b
23E22b
CONT
TGOX50
DNW
Backgate
Source
Drain
PCHSTBLK
NDIFF
N+
P+
P+
PDIFF
MET1
PMD
SDNW
P-sub
SDPW
SDPW
STI
DNW
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12.Integrated backgate contact layout guideline for Power CMOS
1.Integrated Backgate Contacts for Power NMOS/PMOS Devices
In a typical large CMOS power output, a large block of DIFF is used for the source and drain regions. Poly fingers
intersect this DIFF to define channel regions. The backgate contact region is placed outside the active transistor
DIFF region, usually ringing the active DIFF region. Unfortunately, the backgate contact regions can be quite far
from the active part of the power device in these designs (especially the center part of the device). This can lead to
de-biasing effects in the high-resistance backgate regions. This de-biasing problem is extremely important in the
case of an isolated NMOS power device.
The idea behind the Integrated Backgate Contact (IBG) is to tie the backgate down often throughout the active
region of the power device. This strategy is useful when source and backgate can be at the same potential. This
minimizes any backgate de- biasing effects, while maximizing the efficiency of the large NMOS (or PMOS) device
layout. The integrated backgate contact approach incorporates backgate contact plugs into the source region of
the striped transistor. For a large power NMOS device, PDIFF backgate contact regions would be integrated into
the source region of the device. For a large power PMOS device, NDIFF backgate contact regions would be
integrated into the source region. This integration results in NDIFF-PDIFF in the source region having 0um
spacing. Because of very heavy doping in both NDIFF and PDIFF this would result in high leakage if there is any
bias between this NDIFF and PDIFF region. To prevent this leakage, source and backgate must be tied together
and there can be no potential difference between them.
If potential difference is needed between source and backgate for very large devices, use backgate stripe every
once in a while (such that distance between any drain DIFF and backgate DIFF is < 30um) or integrate the source
and backgate with separation between NDIFF and PDIFF (using poly) so that the two DIFFs can be biased at
different potentials.
The integrated backgate contact strategy can be used for all power NMOS and PMOS devices, including 1.8V
power CMOS devices, 5V power CMOS devices, as well as asymmetrical drain-extended power CMOS devices.
2.Key layout rules for integrated backgate contacts
Rule No.
Description of key design rule
8S6a
8S6b
8O3a
8S3c
8E3c
8A8a
min. space between butted DIFF NIMP and PCH POLYGATE
min. space between butted DIFF NIMP edge and NCH POLYGATE
min. overlap from NIMP edge to NDIFF
min. space between NDIFF and butted PDIFF (inside PW or SDPW)
min. enclosure of the edge of a butted NDIFF/PDIFF by NIMP
min. area of NIMP (um2)
8Ra
NIMP overlapped with PIMP is not allowed
7S6a
7S6b
7O3a
7S3c
7E3c
7A7a
min. space between butted DIFF PIMP and NCH POLYGATE
min. space butted DIFF PIMP edge and PCH POLYGATE
min. overlap from a PIMP edge to an PDIFF
min. space between PDIFF and butted NDIFF (inside NW or SDNW)
min. enclosure of the edge of a butted NDIFF/PDIFF by PIMP
min. area of PIMP (um2)
7Ra
PIMP overlapped with NIMP is not allowed.
9S6a
min. space between CONT on DIFF and POLYGATE
9E3a
min. enclosure of DIFF CONT by DIFF
9E3b
9S3b
min. enclosure of TAPDIFF CONT by TAPDIFF
min. space between CONT and TAPDIFF
Conditions
Layout Rule
(um)
0.32
0.32
0.23
0.00
0.00
0.3844
exception;
nch_ee_5p0v,
dio_z_lv, dio_z_mv
0.32
0.32
0.23
0.00
0.00
0.3844
Exception;
nch_ee_5p0v,
dio_z_lv, dio_z_mv
0.16
Exception; SRAM
BLOCK
0.10
0.10
0.10
Note 1) NDIFF and PDIFF source/backgate contacts must alternate and must terminate with PDIFF contacts for Nchannel devices.
Note 2) PDIFF and NDIFF source/backgate contacts must alternate and must terminate with NDIFF contacts for Pchannel devices.
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1.Example of integrated backgate contacts for N-channel devices
NCH POLYGATE
PCH POLYGATE
PCH POLYGATE
Drain region (PDIFF)
PCH POLYGATE
Source region (PDIFF)
Integrated backgate contact (NDIFF)
PCH POLYGATE
Drain region (PDIFF)
NCH POLYGATE
Drain region (NDIFF)
NCH POLYGATE
Source region (NDIFF)
Integrated backgate contact (PDIFF)
NCH POLYGATE
Drain region (NDIFF)
2.Example of integrated backgate contacts for P-channel devices
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5.Revision History
Revision History
Rev
Eff.Date
ECN No.
p-0.0
10-12-10
-
p-0.1
10-12-24
p-0.2
10-12-31
v1.0
11-01-10
v1.1
11-03-18
v2.0
11-06-30
Description of Change
Initial release of preliminary version.
At DEMOS, 3E23j rule id is changed to 3E23l.
At DEMOS, 23S24j rule id is changed to 23S24l.
At DEMOS, 3E24l rule id is changed to 3E24m.
At 3S24e rule, description “PW” is changed to “PDIFF”.
At npn_v_8v, 24O22b rule id is changed to 24O22c.
At 3E23b rule, npn_v_8v is added as exception condition.
At 23S23c, exception rule is added(pch_des_ftr_20v).
At 3E23a and 3E24a, exception rules are deleted.
At exception rule of 3Ra, dio_z_lv is deleted.
At exception rule of 47S6a, nch_pp_1p8v_4t is deleted.
At pnp_s_20v, 23S24l is changed to 23S24m.
At exception rule of 3E23b, npn_v_8v is changed to P-sub pickup of
npn_v_8v.
At npn_v_8v, 3E23m is added and 105E24a is changed to 105E24c.
At 3E23c and 3E23i, exception rule is added(sealring).
At the description of 7E3a and 8E3a, NW and PW are deleted.
At 23S23a and 23S23d rule, ISO_V7 and ISO_V30 conditions are
deleted.
At 3E23a and 3E23c rule, ISO_V7 and ISO_V30 conditions are
deleted.
At metal dummy rule, METx_CAP is deleted.
At POR rule, 21Ra is added.
At 47A47a, exception rules are added.( nch_dea_7v,
nch_dea_iso_7v, pch_dea_7v, nch_dea_12v, pch_dea_12v)
Initial release from preliminary version
CUP IO Pad rules are added.
At the Well and Active resistor rule, notes for SUB and BULK terminal
connection are added.
At poly resistor block, safety rules are added.
Drawing layer information and component vs mask mapping tables
are updated.
Integrated backgate guidelines for Power CMOS are added.
At CONT and VIA rule, 9Rd/9Re/11Rb/13Rb/15Rb/17Rb/19Rb as
safety rules are added.
The following components are added.
-.dio_z_mv
-.res_sdnw
-.res_pdiff_lsr_sdnw
At NIMP and PIMP rule, exception rules of 8E3a/8Ra/7Ra are
updated.
The following layout rules are changed at nch_io_5p0v
IO50.j1 (0.75  0.5), IO50.k1 (0.75  0.5).
The following layout rules are changed at pch_io_5p0v
IO50.j3 (0.75  0.5), IO50.k3 (0.75  0.5).
At the contents, the description is changed from 9. CMOS Isolation to
9. CMOS & I/O Isolation.
nch_io_iso_5p0v_6t/
pch_io_iso_5p0v_5t/
nch_pp_iso_5p0v_6t/
isolated I/O devices are added at 8.1 5.0V ESD Protection Device
The nomenclature is changed from 5030AN18BA to 1830AN18BA.
The following coding layers and layout rules are added.
-. NWELL, PWELL, DWELL, NDT
The components using NWELL and PWELL layers are added.
Requester
YK CHOI
YK CHOI
YK CHOI
YK CHOI
YK CHOI
YK CHOI
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-. 1.8V CMOS components
-. 5V vertical NPN/PNP
-. 1.8V Npoly-Nwell capacitor
-. N+/PWELL, P+/NWELL, LV zener diode
-. NWELL resistor, Pdiff silicided resistor
-.1.8V I/O & ESD devices
The components using NDT and DWELL layers are added.
-. All nLDMOS devices
The following new components are added.
-. Single-poly EPROM
-. 5V vertical NPN/PNP w/ SDNW and SDPW
The following rules are revised and added.
-. Sealring rules
-. 20V substrate PNP rules
-.Safety rules of resistor
-. Dummy generation rules
-.Pattern density rules (Poly, Metal, Via)
7V, 12V, 20V, 24V, 30V ESD protection devices are added.
- esd_hv_pig_7v, esd_hv_gc_7v,
- esd_hv_gg_12v, esd_hv_gc_12v,
- esd_hv_gg_20v, esd_hv_gg_20v
- esd_hv_gc_24v, esd_hv_gg_24v
- esd_hv_gg_30v, esd_hv_gc_30v
ESD protection diodes are added
- NSD-PWELL Diode (dio_nsd_pw_esd)
- PSD-NWELL Diode (dio_psd_nw_esd)
- ESD Protection Diode (dio_hv_esd)
The following layout rules are changed at nch_io_1p8v
- 1.8V NMOS (nch_io_1p8v)
IO18.d1 (30~60  20~60), IO18.f1 (1.95  0.78), IO18.g1 (Y  X 
1.95  Y  1), IO18.h1 (0.45  Overlap by 0.05), IO18.l1
(1.95+0.22  1.0+0.22), IO18.o1 (3.5  2.0)
The following layout rules are changed at nch_pp_1p8v
- 1.8V NMOS for Power Protection (nch_pp_1p8v)
IO18.d2 (30~60  20~60), IO18.f2 (1.95  0.78), IO18.g2 (Y  X 
1.95  Y  1), IO18.l2 (1.95+0.22  1.0+0.22), IO18.o2 (3.5  2.0)
The following layout rules are changed at pch_io_1p8v
- 1.8V PMOS (pch_io_1p8v)
IO18.d3 (30~60  20~60), IO18.f3 (1.5  0.78), IO18.g3 (Y  X 
1.5  Y  1), IO18.h3 (0.45  Overlap by 0.05), IO18.l3 (1.5+0.22
 1.0+0.22), IO18.o3 (3.5  2.0)
The following layout rules are changed at nch_io_5p0v
- 5.0V NMOS (nch_io_5p0v)
IO50.d1 (30~60  20~60), IO50.f1 (1.95  0.78), IO50.g1 (Y  X 
1.95  Y  1), IO50.l1 (1.95+0.22  1.0+0.22), IO50.o1 (3.5  2.0)
The following layout rules are changed at nch_pp_5p0v
- 5.0V NMOS for Power Protection (nch_pp_5p0v)
IO50.d2 (30~60  20~60), IO50.f2 (1.95  0.78), IO50.g2 (Y  X 
1.95  Y  1), IO50.l2 (1.95+0.22  1.0+0.22), IO50.o2 (3.5  2.0)
The following layout rules are changed at pch_io_5p0v
- 5.0V PMOS (pch_io_5p0v)
IO50.d3 (30~60  20~60), IO50.f3 (1.5  0.78), IO50.g3 (Y  X 
1.5  Y  1), IO50.h3 (0.45  Overlap by 0.05), IO50.l3 (1.5+0.22
 1.0+0.22), IO50.o3 (3.5  2.0)
The following layout rule numbers are changed at esd_hv_12v
- 12V ESD Protection Device (esd_hv_12v)
3W3k  3W3j, 6W6t  6W6s
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DBH CONFIDENTIAL
3E2a, 24E2a, 3S2c, 3E24p rules are removed
The following layout rule numbers are changed at esd_hv_24v
- 20V and 24V ESD Protection Device (esd_hv_24v)
3E23g  3E23o, 3S3h  3S3p, 6X3e 6X3i, 47X6f  47X6e
6O23c rule is added
24E2a, 3O23b rules are removed
Component versus Mask mapping table are added
- esd_hv_pig_7v, esd_hv_gc_7v, esd_hv_gg_12v, esd_hv_gc_12v,
esd_hv_gg_20v, esd_hv_gc_20v, esd_hv_gc_24v, esd_hv_gg_24v,
esd_hv_gg_30v,
esd_hv_gc_30v,
dio_nsd_pw_esd,
dio_psd_nw_esd, dio_hv_esd
Component versus Mask mapping table are changed
esd_hv_12v, esd_hv_24v : sample gds is changed (NWELL(O1) is
removed)
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