`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: // Engineer: // // Create Date: 2022/01/18 15:12:36
// Design Name: // Module Name: ALU UUT
// Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:
// Revision 0.01 - File Created
// Additional Comments:
// //////////////////////////////////////////////////////////////////////////////////
module ALU(
input [15:0] A,
input [15:0] B,
input Cin,
input [3:0] OP,
output Cout,
output [15:0] C
);
wire [15:0] csum, csub1, csub2;
wire cout_sum, cout_sub1, cout_sub2;
add_16 a1(A, B, Cin, csum, cout_sum);
add_16 s1(16'b0, B, Cin, csub1, cout_sub1);
add_16 s2(A, ~csub1, 1'b1, csub2, cout_sub2);
assign Cout = (OP == 4'd0)? cout_sum :
(OP == 4'd1)? ((A<csub1 | cout_sub1)? 1'b1: 1'b0) :
1'b0;
assign C = (OP == 4'd0)? csum :
(OP == 4'd1)? csub2 :
(OP == 4'd2)? A :
(OP == 4'd3)? ~(A&B) :
(OP == 4'd4)? ~(A|B) :
(OP == 4'd5)? ~(A^B) :
(OP == 4'd6)? ~A :
(OP == 4'd7)? A&B :
(OP == 4'd8)? A|B :
(OP == 4'd9)? A^B :
(OP == 4'd10)? {1'b0, A[15:1]} :
(OP == 4'd11)? {A[15], A[15:1]} :
(OP == 4'd12)? {A[0], A[15:1]} :
(OP == 4'd13)? {A[14:0], 1'b0} :
(OP == 4'd14)? {B[7:0], 8'd0} :
(OP == 4'd15)? {A[14:0], A[15]} :
16'h0;
endmodule
module full_adder(input a, input b, input cin, output sum, output carry);
assign sum = a^b^cin;
assign carry = a&b | a&cin | b&cin;
endmodule
module add_16(input [15:0] a, input [15:0] b, input cin, output [15:0]sum, output carry);
wire [14:0] cout;
full_adder fadd0(a[0], b[0], cin, sum[0], cout[0]);
genvar i;
for(i=1;i<15;i=i+1)begin:generate_adder
full_adder fadd1(a[i], b[i], cout[i-1], sum[i], cout[i]);
end
full_adder fadd2(a[15], b[15], cout[14], sum[15], carry);
endmodule