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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 16, NO. 10, OCTOBER 2006
A 40-GHz Static Frequency Divider With
Quadrature Outputs in 80-nm CMOS
Christian Kromer, Student Member, IEEE, George von Büren, Student Member, IEEE, Gion Sialm,
Thomas Morf, Member, IEEE, Frank Ellinger, Member, IEEE, and Heinz Jäckel, Member, IEEE
Abstract—The implemented static frequency divider provides
quadrature ( ) clock outputs and divides frequencies up to
44 GHz. The core divider circuit consists of two current-mode
logic (CML) latches and consumes 3.2 mW from a 1.1-V supply.
The divided outputs result in a peak-to-peak and rms jitter of 6.3
and 0.8 ps, respectively, and the maximum phase mismatch between the in-phase ( ) and -outputs amounts to 1 ps at an input
frequency of 40 GHz. The high division frequency is achieved by
employing resistive loads, inductive peaking, and optimizing the
circuit layout for reduced parasitic capacitances in the latches.
The core divider consumes a chip area of 30 m 40 m only.
TABLE I
COMPARISON OF RECENTLY PUBLISHED STATIC FREQUENCY DIVIDERS [3]–[5]
Index Terms—Clock-and-data recovery (CDR), CMOS, currentmode logic (CML), frequency divider, phase-locked loop (PLL).
I. INTRODUCTION
H
IGH-SPEED quadrature ( ) clock signals are critical for a
variety of applications, ranging from in-phase/quadrature
) down-conversion in wireless receivers to phase interpo(
lation or phase and frequency detection schemes in wire-line
communication. In addition, high-speed frequency dividers are
needed for frequency synthesis in wireless and wire-line systems.
To date static frequency division at and beyond 40 GHz
could only be achieved with bipolar and III–V technologies.
In Table I, recently published CMOS static frequency dividers
are listed and compared with this work. The highest division
frequency reported to date is 33 GHz [1]. However, 40-GHz
phase-locked loops (PLLs) require frequency dividers at
40 GHz and 40-Gb/s clock-and-data recovery (CDR) circuits
need 20-GHz -clocks for half-rate phase and frequency detection. Dynamic frequency dividers achieve higher frequencies
compared to static frequency dividers. However, they suffer
from a limited bandwidth, whereas static frequency dividers
operate from dc to a maximum frequency. Moreover, regenerative dynamic frequency dividers do not provide -outputs.
To compare the results of recently published static frequency
dividers in Table I with respect to speed and power consumption, the figure-of-merit (FOM) of power consumption per
Manuscript received May 8, 2006; revised June 1, 2006. This work was supported by the Swiss Federal Office for Professional Education and Technology
under Contract/Grant KTI 4900.1.
C. Kromer, G. von Büren, G. Sialm, F. Ellinger, and H. Jäckel are with the
Electronics Laboratory, Swiss Federal Institute of Technology (ETH) Zurich,
Zürich 8092, Switzerland (e-mail: kromer@ife.ee.ethz.ch).
T. Morf is with the Zurich Research Laboratory, IBM Research, Rüschlikon
8803, Switzerland.
Color versions of Tables 1 and 2 are available online at http://ieeexplore.ieee.
org.
Digital Object Identifier 10.1109/LMWC.2006.882382
Fig. 1. Block diagram of the divide-by-two circuit including the input and
output buffers.
maximum frequency division is introduced. The lowest power
per frequency division of high-speed CMOS frequency dividers
reported to date is 0.15 mW/GHz [2].
This work presents a static frequency divider for 40-GHz PLL
and 40-Gb/s half-rate CDR applications and features by a factor
of two the lowest power consumption per maximum frequency
division of 73 W/GHz.
II. CIRCUIT DESIGN
The topology of the / static frequency divider including
input and output buffers is shown in Fig. 1.
The divider core consists of a differential CML D-flip-flop
(DFF), where the output is inverted and fed back to the data
input. The DFF is built of two latches (L1 and L2). The outputs of the two latches provide four phases at 0 , 90 , 180 ,
and 270 of the divided reference clock. Small two-stage amplifiers (AMP) buffer the outputs of the latches. This allows a
high frequency division, as the capacitive loads at the outputs of
the latches are small. At the outputs of the AMPs 50- buffers
(BUFFER) are added to drive the measurement equipment. An
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KROMER et al.: 40-GHZ STATIC FREQUENCY DIVIDER
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Fig. 3. Circuit schematic of the two-stage amplifier.
Fig. 2. Schematic of a current-mode logic (CML) latch.
input clock buffer is inserted to demonstrate proper operation
with typical on-chip voltage levels as well as rise and fall times.
The circuit schematic of the classical current-mode logic
(CML) latch is shown in Fig. 2. The latch circuit consists of two
differential stages with common loads. Their current sources
are controlled by the clock signals CP and CM, respectively. If
CM is high and CP is low, the input signal DP and DM appear
amplified at the outputs QP and QM. This is called the “tracking
phase” since the outputs track the inputs of the latch. If the CM
switches to low and CP to high voltage levels, the inputs are
turned off and whatever levels the outputs have, are sensed and
limited to the supply rails by positive feedback. This is called
the “latching phase.” Resistive loads offer a lower parasitic capacitance by a factor of approximately ten compared to PMOS
loads. Each peaking inductor of the divider uses a chip area of
15 m 15 m and occupies the top two metal layers in series.
Minimum metal width and metal-to-metal space is chosen for
a maximum inductance per area ratio. Thus, an inductance of
2 nH is achieved. A relatively high series resistance of 30
does not pose a problem for peaking purposes. The peaking
inductors increase the bandwidth of the circuit by a factor of
1.6, which is close to the maximum of 1.85 for shunt-peaking
[6]. Consequently, high-speed operation is achieved.
In the divider configuration in Fig. 1, if L1 tracks then L2
latches, and vice versa. As a result, the output of the DFF only
changes at rising CP (falling CM) clock transitions. In any other
time the outputs are static. The same applies to the outputs of
L1 in the feedback configuration as shown in Fig. 1. However,
they are shifted by half an input clock cycle or a quarter output
clock cycle. Consequently, 0 , 90 , 180 , and 270 clock phases
are derived. This type of frequency divider is called “static frequency divider.” The advantage of static compared to dynamic
frequency dividers is the broadband operation from 0 Hz to a
maximum division frequency as long as the slew rate is high
enough. The disadvantage is the relatively low maximum division frequency. This is due to the fact that each latch output node
has to drive two transistor drain and two transistor gate capacitances, the load resistor capacitance plus the input capacitance
of the output buffer (AMP). Consequently, the frequency divider
TABLE II
MEASUREMENT RESULTS OF THE FREQUENCY DIVIDER
and the sampling latches in PLLs and CDRs, respectively, are
generally the speed-limiting blocks.
In this divider design, apart from employing resistive loads
and inductive peaking, the layout was optimized for symmetry
and reduced parasitic capacitances of the transistors and metal
wiring. The symmetrical layout is needed to keep the / clock
phase mismatch at a minimum. Parasitic capacitance to the highspeed clock signal path is kept at a minimum by close placement
of the transistors carrying the high-speed divided clock output
signal and by avoiding the use of lower levels of metal to route
the high-speed connections. Consequently, the implemented circuit divides frequencies up to 44 GHz.
The circuit schematic of the two-stage amplifier (AMP) is
shown in Fig. 3. Both amplifier stages consist of CML commonsource differential amplifiers with resistive loads and inductive
peaking for high-speed operation. The transistor width of M of
the first stage is 2 m and consequently offers a small capacitive
load to the -outputs of the frequency divider and thus a high
maximum frequency division is feasible. Designing a smaller
transistor width is not possible, as the required amplifier bandwidth of 20 GHz could not be achieved. The transistor widths
of the second stage are doubled to drive the 50- output buffer.
The output buffer is similar to as presented in [7] and consists of five stages to step down the required output impedance
of 50 . Thus, the input yields a small capacitance and consequently does not limit the speed of the clock outputs.
III. MEASUREMENT RESULTS
Table II shows the maximum measured divider input frequencies versus minimum, nominal and maximum supply
voltage. At a nominal supply voltage of 1.1 V, the maximum
frequency, which can be divided by two, is 44 GHz. At the
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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 16, NO. 10, OCTOBER 2006
The chip micrograph of the implemented static frequency divider is shown in Fig. 5. The / frequency divider is located
in the center of the chip micrograph (DFF) and consumes a chip
area of 30 m 40 m only. Including the and -amplifiers
(AMP) increases the chip area to 60 m 70 m. The highly
optimized and symmetrical layout of the core divider enables the
circuit for proper frequency division by two of up to 44 GHz.
IV. CONCLUSION
Fig. 4. Sensitivity at the input of the buffer and divider.
A power efficient and high-speed / static frequency divider in 80-nm CMOS with resistive loads, inductive peaking,
and optimized layout of the divider latches is demonstrated. The
outputs features the
designed static frequency divider with
highest speed and lowest power consumption per maximum division frequency for CMOS implementations reported to date.
The extremely compact and low-power-consuming static frequency divider is therefore best suited for 40 GHz PLL and
40 Gb/s half-rate CDR applications.
ACKNOWLEDGMENT
The authors wish to thank the members of the IBM Foundry
Team, Fishkill, NY, for manufacturing the CMOS chips.
REFERENCES
Fig. 5. Chip micrograph of the frequency divider with input and output buffers.
maximum supply voltage of 1.2 V, proper frequency division is
still achieved at a maximum input frequency of 44.7 GHz.
The input power at the input of the divider is calculated by
adding the measured clock buffer gain to the measured minimum input clock buffer power for proper frequency division.
Both input powers at the divider and buffer input are shown in
Fig. 4. Proper frequency division is achieved from 2 to 44 GHz
for sinusoidal input signals 0 dBm. A maximum peak-to-peak
and rms phase jitter of 6.3 and 0.8 ps, respectively, is measured. The mean measured duty-cycle and / phase mismatch
amounts to 1 ps.
The input and output buffers consume 27 mW from a 1.1-V
supply, each. The DFF and one two-stage amplifier consume approximately 3.2 and 2.4 mW, respectively, from a 1.1-V supply.
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