UNIT V
MEMORY AND PROGRAMMABLE LOGIC
RAM – Memory Decoding – Error Detection and Correction - ROM - Programmable Logic Array –
Programmable Array Logic – Sequential Programmable Devices..
 A memory unit is a device to which binary information is transferred for storage and from
which information is retrieved when needed for processing.
 A memory unit is a collection of cells capable of storing a large quantity of binary information.
TWO TYPES OF MEMORIES
Explain in detail about two types of memories.
May 2012
 There are two types of memories that are used in digital systems: random-access memory
(RAM) and read-only memory (ROM)
 The process of storing new information into memory is referred to as a memory “write”
operation.
 The process of transferring the stored information out of memory is referred to as a
memory “read” operation.
 RAM can perform both write and read operations. ROM can perform only the read operation.
 This means that suitable binary information is already stored inside memory and can be
retrieved or read at any time. However, that information cannot be altered by writing.
 ROM is one example of a PLD. Other such units are
o Programmable logic array (PLA)
o Programmable array logic (PAL), and
o Field Programmable Gate Array (FPGA).
 A PLD is an integrated circuit with internal logic gates connected through electronic paths that
behave similarly to fuses.
Fig: Block diagram of a memory unit.
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 The n data input lines provide the information to be stored in memory and the n data
output lines supply the information coming out of memory.
 The k address lines specify the particular word chosen among the many available.
 The two control inputs specify the direction of transfer desired: The Write input causes binary
data to be transferred into the memory and the Read input causes binary data to be transferred
out of memory.
 A typical PLD may have hundreds to millions of gates interconnected through hundreds to
thousands of internal paths. Instead of having multiple input lines into the gate, we draw a
single line entering the gate.
 The input lines are drawn perpendicular to this single line and are connected to the gate through
internal fuses as shown in the figure. In a similar fashion, we can draw the array logic for an
AND gate.
Fig: Conventional and array logic diagrams for OR gate
READ-ONLY MEMORY
What is ROM and why is it necessary to use ROM in a computer? Explain various types of ROM in
detail. [NOV-2019]
Explain in detail about read-only memory.
(Apr 2018 , Dec 2011)
 A ROM is essentially a memory device in which permanent binary information is stored.
 It is embedded in the unit and cannot be altered, even when the power is turned off.
 It does not have data inputs because it does not have write operation.
Fig: ROM block diagram
 Number of words is get from number of address inputs, here it is ‘k’, hence 2k words of n bits
each is present in the memory.
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Fig: Internal logic of a 32×8 ROM
Example:
 The five inputs are decoded into 32 distinct outputs by means of a 5×32 decoder. Each output of
the decoder represents a memory address.
 The 32 outputs of the decoder are connected to each of the eight OR gates. Each OR gate must be
considered as having 32 inputs.
 Each output of the decoder is connected to one of the inputs of each OR gate. Since each OR gate
has 32 input connections and there are 8 OR gates, the ROM contains 32 x 8 = 256 internal
connections.
 A programmable connection between two lines is logically equivalent to a switch that can be
altered to be either closed (meaning that the two lines are connected) or open (meaning that the
two lines are disconnected).
 The programmable intersection between two lines is sometimes called a cross point.
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 For example, programming the ROM according to the truth table given by table. Every 0 listed
in the truth table specifies the absence of a connection and every 1 listed specifies a path that is
obtained by a connection.
Fig: Programming the ROM according to ROM truth table
Types of ROMs
The required paths in a ROM may be programmed in four different ways.
 Mask programming
o Done by the semiconductor company during the last fabrication process of the unit.
o This procedure is costly because the vendor charges the customer a special fee for
custom masking the particular ROM.
 Programmable read-only memory- PROM.
o Economical for small quantity.
o The fuses in the PROM are blown by the application of a high-voltage pulse to the
device through a special pin.
o A blown fuse defines a binary 0 state and an intact fuse gives a binary 1 state.
o The procedure is irreversible and once programmed; the fixed pattern is permanent and
cannot be altered.
 Erasable PROM or EPROM
o This can be restructured to the initial state even though it has been programmed
previously.
o It is erased by placing under a special ultraviolet light for a given length of time.
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 Electrically erasable PROM (EEPROM or E2PROM)
o Electrical signals are used to erase the previously programmed connections instead of
ultraviolet light.
o The advantage is that the device can be erased without removing it from its socket.
Combinational PLDs
 The PROM is a combinational programmable logic device (PLD)-an integrated circuit with
programmable gates divided into an AND array and an OR array to provide an AND-OR sum
of- product implementation.
 There are three major types of combinational PLDs, differing in the placement of the
programmable connections in the AND-OR array.
1. PROM- Fixed AND array and a programmable OR array.
2. PAL - Programmable AND array and a fixed OR array.
3. PLA - Programmable AND array and a programmable OR array.
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RANDOM ACCESS MEMORY
Discuss briefly about RAM and its types. (or) Explain in detail about random access memory. Apr.
2014, Dec. 2010, Nov 2018, Apr 2019
 A memory unit is a collection of storage cells together with associated circuits needed to transfer
information into and out of a device.
 A memory unit stores binary information in groups of bits called words.
 A memory word is a group of 1 's and 0's and may represent a number, an instruction , one or
more alphanumeric characters or any other binary-coded information.
 Each word in memory is assigned an identification number called an address starting from 0 upto
2k-1. where k is the number of address lines.
 Consider for example, a memory unit with a capacity of 1K words of 16 bits each. Since
1K=1024bytes = 210 and 16 bits constitute two bytes, we can say that the memory can
accommodate 2048 = 2K bytes.
Fig: Contents of a 1024 × 16 memory
Read and write operations:
 The two operations that RAM can perform are the write and read operations.
Steps to read operation as follows:
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 Apply the binary address of the desired word to the address lines.
 Apply the data bits that must be stored in memory to the data input lines.
 Activate the write input.
Steps to write operation as follows:
 Apply the binary address of the desired word to the address lines.
 Activate the read input.
 The memory enable or chip select is used to enable the particular memory chip in a multichip
implementation of a large memory.
 When the memory enable is inactive, the memory chip is not selected and no operation is
performed. When the memory enable input is active, the read/write operation to be performed.
Timing Waveforms
 The operation of the memory unit is controlled by an external device such as a central
processing unit (CPU).
 The CPU is usually synchronized by its own clock.
 The access time of memory is the time required to select a word and read it.
 The cycle time of memory is the time required to complete a write operation.
Fig: Memory read cycle timing waveform
 The memory- enable and read/write signals must be in their high level for a read operation.
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Fig: Memory write cycle timing waveform
 The memory enable signal switches to the high level and the read/write signal switches to the
low level to indicate a write operation.
Types of RAM
 Integrated circuit RAM units are available in two operating modes: static and dynamic.
S.No Static RAM
Dynamic RAM
1
Static RAM contains less memory cells
Dynamic RAM contains more memory cells
per unit area
as compared to static RAM per unit area.
It has less access time hence faster
Its access time is greater than static RAMs.
2
memories.
3
Static RAM consists of number of flip
Dynamic RAMs store the data as a charge
flops. Each flip flop stores one bit.
on the capacitor. It consists of MOSFET
and the capacitor for each cell.
4.
Refreshing circuitry is not required.
Refreshing circuitry is required to maintain
the charge on the capacitors after every few
milliseconds
5
Cost is more
Cost is less
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TWO MARKS
1. Define a memory cell. [May/June 2007,Nov/Dec 2004.2006]
Memories are made up of registers. Each register consists of storage elements, each of which stores
one bit of data. Such a storage element is called a memory cell.
2. Define a memory location.[May/June 2006]
Memories are made up of registers. Each register in the memory is one storage location is called
memory location. Each memory location is identified by an address.
3. What is a volatile memory? Give example.[Nov/Dec 2007,2013]
The memory which cannot hold data when power is turned off is known as volatile memory. The
static RAM is a volatile memory.
4. What is non-volatile memory?[Nov/Dec 2013]
The memory which can hold data even if power is turned off is known as non volatile memory.
5. Name the types of ROM. [May/June 2011].
There are four types of ROM.
1. Masked ROM(Masked Read only memory)
2. PROM(Programmable ROM)
3. EPROM(Erasable Programmable ROM)
4. EEPROM or E2 PROM (Electrically Erasable PROM)
6. Define address and word.
In a ROM, each bit combination of the input variable is called an address. Each bit combination
that comes out of the output lines is called a word.
7. Explain ROM
A Read Only Memory (ROM) is a device that includes both the decoder and the OR gates within a
single IC package. It consists of ‘n’ input lines and ‘m’ output lines. Each bit combination of the input
variables is called an address .Each bit combination that comes out of the output lines is called a word.
The number of distinct address possible with ‘n’ input variables is 2n.
8. What is mask – programmable ROM?
A type of memory where the stored data are permanently stored into the memory device during
the manufacturing process.
9. Define PROM.
PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to
a decoder and a programmable OR array. It allows user to store data or program. PROMs use the fuses
with material like nichrome and polycrystalline. The user can blow these fuses by passing around 20 to
50mAof current for the period 5 to 20µs.
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10. Explain EPROM.
EPROM is Erasable Programmable Read Only Memory. It uses MOS circuitry. They store 1’s and 0’s
as a packet of charge in a buried layer of the IC chip. We can erase the stored data in the EPROMs by exposing the chip to
ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be
reprogrammed.
11. Explain EEPROM. [Nov/Dec 2014]
EEPROM is Electrically Erasable Programmable Read Only Memory It uses MOS circuitry. Data is
stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective
erasing at the register level rather than erasing all the information since the information can be changed by using
electrical signals.
12. How is individual location in a EEPROM programmed or erased?[May/June 2006]
Since it is electrically erasable memory, by activating particular row and column it is possible that
individual can be programmed or erased.
13. What is RAM?
RAM is Random Access Memory. Read and write operation can be carried out. It is a volatile memory. It can hold
data as power is ON.
14. Give the advantages of RAM.[Nov/Dec 2013]
Advantages of RAM are:
1. RAM is a memory where we can read as well as write the data.
2. Higher speed.
3. The particular memory location can be accessed using the address of at memory location.
4. Low power dissipation
5. Compatibility
6. Economy
15. What is read and write operation?
The write operation stores data in to a specified address location in to the memory and read operation takes data out of a
specified address from the memory.
16. List the two categories of RAM.
1. Static RAM
2. Dynamic RAM
17. What is static memory?
Nov/Dec 2006,April/May 2007]
Memories that consist of circuits of retaining their state as long as power is applied are known as static memories.
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18. Differentiate Static RAM and dynamic RAM. [Nov/Dec 2009] [Nov -2019]
S.No Static RAM
Dynamic RAM
1
Static RAM contains less memory cells
Dynamic RAM contains more memory cells
per unit area
as compared to static RAM per unit area.
It has less access time hence faster
Its access time is greater than static RAMs.
2
memories.
3
Static RAM consists of number of flip
Dynamic RAMs store the data as a charge
flops. Each flip flop stores one bit.
on the capacitor. It consists of MOSFET
and the capacitor for each cell.
4.
Refreshing circuitry is not required.
Refreshing circuitry is required to maintain
the charge on the capacitors after every few
milliseconds
5
Cost is more
Cost is less
19. What are the advantages of static RAM and dynamic RAM? [NOV 2020]
Advantages of SRAM:
 SRAM is faster than DRAM which means it is faster in operation.
 SRAM can be used to create a speed-sensitive cache.
 SRAM only has medium power consumption.
 SRAM has a shorter cycle time since it does not require pausing between accesses.
Advantages of DRAM:
 DRAM is more affordable than SRAM.
 DRAM has a higher storage capacity which enables you to create a larger RAM space system.
 DRAM offers a simple structure.
 DRAM utilizes logic and circuitry which makes the memory module simpler to set up and use.
20. Define dynamic RAM.
Dynamic RAMs use capacitors as storage elements and cannot retain data very long without
capacitors being recharged by a process called refreshing.
21. List the two types of SRAM.
1. Asynchronous SRAMs
2. Synchronous burst RAMs
22. List the basic types of DRAMS.
1. Fast page mode DRAM
2. Extended Data Out DRAM (EDO DRAM)
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3. Burst EDO DRAM
4. Synchronous DRAM.
23. What is the technique adopted by DRAMs?
DRAMs use a technique called address multiplexing to reduce the number of address lines.
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MEMORY DECODING
Explain in detail about memory decoding.
Apr. 2014,Apr 2017
 Once the address is given as input to memory, it has to select the corresponding memory word for
performing either a read/write operation. This can be done by decoding circuit.
Internal Construction
 Ram specification = m × n binary storage cells. Where, m words and n bits per word
 The binary storage cell is the basic building block of a memory unit.
Fig: Block diagram of a memory cell
Fig: Logic diagram of a memory cell
 The storage part of the cell is modeled by an SR latch. .Actually, the cell is an electronic
circuit with four to six transistors.
 The select input enables the cell for reading or writing.
 A 1 in the read/write input provides the read operation.
 A 0 in the read/write input provides the write operation.
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Fig: Diagram of a 4×4 RAM
 The small blocks labeled BC (binary cell) with its three inputs and one output.
 A memory with four words needs two address lines. The two address inputs go through a 2×4
decoder to select one of the four words.
 The decoder is enabled with the memory-enable input.
 When the memory enable is 0, all outputs of the decoder are 0 and none of the memory words are
selected.
 With the memory select at 1, one of the four words is selected depending on the address input.
 Once a word has been selected, the read/write input determines the operation to be carried out.
 During the read operation
o four bits of the selected word go through OR gates.
 During the write operation
o data available in the input lines are transferred into the four binary cells of the selected
word.
Coincident Decoding
 A decoder with k inputs and 2k outputs requires 2k AND gates with k inputs per gate.
 The total number of gates and the number of inputs per gate can be reduced by employing two
decoders in a two - dimensional selection scheme.
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Fig: Two dimensional decoding structure for a 1K-word memory
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 Two k/2 input decoders are used instead of one k-input decoder. One for row selection and the
other is column selection.
 For example, instead of using a single 10 x 1,024 decoder, we use two 5 x 32 decoders. With the
single decoder, we would need 1,024 AND gates with 10 inputs in each. The five most significant
bits of the address go to input X and the five least significant bits go to input Y.
 Each word within the memory array is selected by the coincidence of one X line and one Y
line.
Address Multiplexing
 Because of large capacity, the address decoding of DRAM is arranged in a two dimensional array
and larger memories often have multiple arrays.
 To reduce the number of pins in the IC package, hence address multiplexing is done.
 In a two-dimensional array, the address is applied in two parts at different times, with the row
address first and the column address second.
 Since the same set of pins is used for both parts of the address, the size of the package is
decreased significantly.
Fig: Address multiplexing for a 64K DRAM
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 The memory consists of a two-dimensional array of cells arranged into 256 rows by 256
columns, for a total of 28 x 28 = 216 = 64K words.
 There is a single data input line; a single data output line, and a read/write control as well as
an eight-bit address input and two address strobes, the later included for- enabling the row and
column address into their respective registers.
 The row address strobe (RAS) enables the eight-bit row register.
 The column address strobe (CAS) enables the eight-bit column register.
 The bar on top of the name of the strobe symbol indicates that the registers are enabled on the
zero level of the signal.
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256k x 8 RAM using 64k x 8 RAM chips
Explain the logical construction of a 256k x 8 RAM using 64k x 8 RAM chips. (Apr 2019) [Nov 2019]
•
No. of words is the same (8-bits)
•
No. of address lines are not the same (64K  256K)
•
64K  16-bit address (26 x 210)
•
256  18-bit address (28 x 210)
An additional 2-bits is needed for the address bit.

2 additional address bits are applied to a 2 x 4 decoder and represent the MSB of the address
bit.
How many 64K x 8 RAM chip to add?

Additional 2-bits  22 = 4 of 64 x 8 RAM

Use Memory Enable to activate the decoder.
 When bit 17 and 16 = 00, The first 64 x 8 RAM is activated. Address : 0 – 65,535
 When bit 17 and 16 = 01, The 2nd 64 x 8 RAM is activated. Address : 65,536 – 131,071
 When bit 17 and 16 = 10, The 3rd 64 x 8 RAM is activated. Address : 131,071 – 196,607
 When bit 17 and 16 = 11, The 4th 64 x 8 RAM is activated. Address : 196,608 – 262,143
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How many 32k x 8 RAM chips are needed to provide memory capacity of 512k bytes. [Nov -2019]
•
No. of words is the same (8-bits)
•
No. of address lines are not the same (32K  512K)
•
32K  15-bit address (25 x 210)
•
512K  19-bit address (29 x 210)
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An additional 4-bits is needed for the address bit.

4 additional address bits are applied to a 4 x 16 decoder and represent the MSB of the address
bit.
How many 32K x 8 RAM chip to add?

Additional 2-bits  24 = 16 of 32k x 8 RAM are needed to provide memory capacity of 512k
bytes.
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TWO MARKS
1. Define address of a memory.
Address of memory:
The location of a unit of data in a memory is called address.
2. Define capacity of a memory.
Capacity of memory:
The capacity of memory is the total number of data units that can be stored.
3. Write about internal construction of Memory cell and memory decoding. (Apr 2017)
The internal construction of a RAM of m words and n bits per word consists of m × n binary
storage cells and associated decoding circuits for selecting individual words. The binary storage cell
is the basic building block of a memory unit.
Fig: Block diagram of a memory cell
Once the address is given as input to memory, it has to select the corresponding memory word for
performing either a read/write operation. This can be done by decoding circuit.
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ERROR DETECTION AND CORRECTION
Explain in detail about error detection and correction.
Dec'13,Nov 2017,Apr 2018, Apr 2019
 The most common error detection scheme is the parity bit.
 A parity bit is generated and stored along with the data word in memory.
 The parity of the word is checked after reading it from memory.
 The data word is accepted if the parity of the bits read out is correct. If the parity checked results
in an inversion, an error is detected, but it cannot be corrected.
 An error-correcting code generates multiple parity check bits that are stored with the data word in
memory. Each check bit is parity over a group of bits in the data word.
 When the word is read back from memory, the associated parity bits are also read from memory
and compared with a new set of check bits generated from the data that have been read. If the
check bits are correct, no error has occurred.
 If the check bits do not match the stored parity, they generate a unique pattern called a syndrome,
which can be used to identify e r r o r i n bit.
 A single error occurs when a bit changes in value from 1 to 0 or from 0 to 1 during the write or
read operation. If the specific bit in error is identified, then the error can be corrected by
complementing the erroneous bit.
Hamming Code
 One of the most common error-correcting codes used in RAMs was devised by R. W. Hamming.
In the Hamming code, k. parity bits are added to an n-bit data word, forming a new word of n +
k bits.
 The bit positions are numbered in sequence from 1 to n + k, these positions numbered as a power
of 2 are reserved for the parity bits. The remaining bits are the data bits.
 Consider, for example the 8-bit data word 11000100. We include 4 parity bits with the 8-bit
word and arrange the 12 bits as follows:
 The 4 parity bits P1, P2, P4 and P8 are in positions 1, 2, 4 and 8 respectively. The 8 bits of
the data word are in the remaining positions. Each parity bit is calculated as follows:
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 The 8-bit data word is stored in memory together with the 4 parity bits as a 12-bit composite
word. Substituting the 4 P bits in their proper positions, we obtain the 12-bit composite
word stored in memory.
 When the 12 bits are read from memory, they are checked again for errors. The parity is
checked over the same combination of bits, including the parity bit.
 The 4 check bits are evaluated as follows:
 A 0 check bit designates even parity over the checked bits and a 1 designates odd parity.
 Since the bits were stored with even parity, the result, C = C 8C4C2C1 = 0000, indicates that
no error has occurred.
 However, if C≠0, then the 4 -bit binary number formed by the check bits gives the position of
the erroneous bit. For example, consider the following three cases:
Single-Error Correction, Double-Error Detection
 The Hamming code can detect and correct only a single error. By adding another parity bit to the
coded word, the Hamming code can be used to correct a single error and detect double errors.
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TWO MARKS
1. What are error detecting codes? (Apr 2019)
Error detection codes are used to detect the errors present in the received data (bit stream). These
codes contain some bits, which are included to the original bit stream. These codes detect the error, if
it is occurred during transmission of the original data.
Eg: Parity Code, Hamming Code
2. What are error correcting codes?
Error correction codes are used to correct the errors present in the received data (bit stream) so that,
we will get the original bit stream.
Eg: Hamming Code
3. How many check bits are required for single bit error detection and correction? (Apr 2018)
12 check bits are required for single bit error detection and correction.
PROGRAMMABLE LOGIC DEVICES
Explain in detail about programmable logic devices. Apr. 2013, Dec. 2013, Nov 2017, Apr 2019, [Nov2019]
PROGRAMMABLE LOGIC ARRAY
 Programmable logic arrays (PLAs) is a type of fixed architecture logic devices with
programmable AND gates followed by programmable OR array.
 PLA is used to implement a complex combinational circuit.
 The AND and OR gates inside the PLA are initially fabricated with fuses among them.
 The specific Boolean functions are implemented in sum of products (SOP) form by blowing
appropriate fuses and leaving the desired connections.
 For an example, the Boolean expressions are,
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Fig: PLA with three inputs, four product terms and two outputs
 The fuse map of a PLA can be specified in a tabular form. The first section lists the product
terms numerically.
 The second section specifies the required paths between inputs and AND gates.
 The third section specifies the paths between the AND and OR gates. For each output variable,
we may have a T'(for true) or C (for complement) for programming the XOR gate.
 For each product term, the inputs are marked with 1, 0, or - (dash). If a variable in the product
term appears in the form in which it is true, the corresponding input variable is marked with a 1.
 If it appears complemented, the corresponding input variable is marked with a 0. If the variable is
absent from the product term, it is marked with a dash.
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Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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Problems using PROM:
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PROGRAMMABLE ARRAY LOGIC (Nov 2018)
 The PAL is a programmable logic device with a fixed OR array and a programmable AND
array. Because only the AND gates are programmable, the PAL is easier to program than but is
not as flexible as the PLA.
 As an example of using a PAL in the design of a combinational circuit,
Problem:
Implement the following Boolean functions, using PAL.
Sol:
Simplify the functions using K Map:
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PAL Programming Table:
BCD to Gray Code using PLA and PAL.
(Apr 2018)
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PAL Implementation:
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TWO MARKS
1. Define PLD.
Programmable Logic Devices consist of a large array of AND gates and OR gates that can be
programmed to achieve specific logic functions.
2. Give the classification of PLDs.[April/May 2013]
PLDs are classified as:
1. Programmable Read Only Memory(PROM)
2. Programmable Logic Array(PLA)
3. Programmable Array Logic(PAL)
4. Generic Array Logic (GAL)
3. What is programmable logic array(PLA)?[April/May 2008, Nov 2017]
In PLA both AND and OR gates have fuses at the inputs, therefore in PLA both AND and OR gates
are programmable. The outputs from OR gates go through fuses as inputs to output inverters so that final
output can be programmed as either AND-OR or AND-OR-INVERT.
4. Why was PAL developed?
PAL is a PLD that was developed to overcome certain disadvantages of PLA such as longer delays
due to additional fusible links that result from using two programmable arrays and more circuit
complexity.
5. Why the input variables to a PAL are buffered?
The input variables to a PAL are buffered to prevent loading by the large number of AND gate
inputs to which available or its complement can be connected.
6. Define PAL. [NOV 2020]
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array
with output logic
7.
Compare PLA and PAL.[April/May 2013 , Apr 2017, Nov 2018]
S.No. PLA
PAL
1
Both AND and OR arrays are
OR array is fixed and AND array is
programmable
programmable
2
Costliest and complex than PAL
Cheaper and simpler
3
AND array can be programmed to get
AND array can be programmed to get
desired minterms
desired minterms
Any Boolean functions in SOP form can be
Any Boolean functions in SOP form can
implemented using PLA
be implemented using PLA
4
Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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8. Differentiate ROM and PLD. (Nov 2017)
S.No ROM (Read only Memory)
PLD (Programmable Logic Devices)
1.
It is a device that includes both AND and
It is a device that includes both the decoder
and the OR gates with in a singlel IC package. OR gates within a single IC package.
2.
ROM does not full decoding of the variables
PLD does not provide full decoding of the
and does generate all the minterms.
variable and does not generate all the
minterms.
9. Compare the features of PROM,PAL and PLA.[April/May 2009]
S.No.
PROM
PLA
PAL
1
AND array is fixed and
Both AND and OR arrays
OR array is fixed and AND
2
OR array is programmable are programmable
array is programmable
Cheaper and simple to use
Cheaper and simpler
Costliest and complex than
PAL
3
4
All minterms are decoded
AND array can be
AND array can be
programmed to get desired
programmed to get desired
minterms
minterms
Only Boolean functions in
Any Boolean functions in
Any Boolean functions in
standard SOP form can be
SOP form can be
SOP form can be
implemented using PROM implemented using PLA
implemented using PLA
10. Give the comparison between PROM and PLA.
S.No
PROM
PLA
1
AND array is fixed and OR array is
Both AND and OR arrays are
programmable.
Programmable.
Cheaper and simple to use.
Costliest and complex than
2
PROMS.
11. How many address lines and data lines are there in 4K x 8 ROM? (Apr 2018)
Address Lines (n) : 2n=N, 2 12 = 4096 (or) 4K; n=12 address lines
Data Lines : 8 bits
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Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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SEQUENTIAL PROGRAMMABLE DEVICES
Explain in detail about sequential programmable devices.(Apr 2017, Apr 2018)
Digital systems are designed with flip-flops and gates. Since the combinational PLD consists of only
gates, it is necessary to include external flip-flops when they are used in the design. Sequential
programmable devices include both gates and flip-flops.
1. Sequential (or simple) programmable logic device (SPLD)
2. Complex programmable logic device (CPLD)
3. Field-programmable gate array (FPGA)
Sequential (or simple) programmable logic device (SPLD):
 The sequential PLD is sometimes referred to as a simple PLD to differentiate it from the
complex PLD.
 The SPLD includes flip‐ flops, in addition to the AND–OR array, within the integrated circuit
chip. The result is a sequential circuit as shown in Fig.
 A PAL or PLA is modified by including a number of flip‐ flops connected to form a register.
 The circuit outputs can be taken from the OR gates or from the outputs of the flip-flops.
Complex programmable logic device (CPLD):
 CPLD is a collection of PLDs to be connected to each other through a programmable switch
matrix.
 The input–output (I/O) blocks provide the connections to the IC pins.
 Each I/O pin is driven by a three‐ state buffer and can be programmed to act as input or output.
 The switch matrix receives inputs from the I/O block and directs them to the individual
macrocells.
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 Similarly, selected outputs from macrocells are sent to the outputs as needed.
 Each PLD typically contains from 8 to 16 macrocells.
Field-programmable gate array (FPGA):
 A field‐ programmable gate array (FPGA) is a VLSI circuit that can be programmed at the
user’s location.
 A typical FPGA consists of an array
of millions of logic blocks, surrounded by
programmable input and output blocks and connected together via programmable
interconnections.
 There is a wide variety of internal configurations within this group of devices.
 The performance of each type of device depends on the circuit contained in its logic blocks
and the efficiency of its programmed interconnections.
Fig: Large programmable-logic-device scaling approaches: (a) CPLD; (b) FPGA.
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 A typical
FPGA logic block
consists
of lookup
tables,
multiplexers, gates, and
flip‐ flops.
 A lookup table is a truth table stored in an SRAM and provides the combinational circuit
functions for the logic block.
 The combinational logic section, along with a number of programmable multiplexers, is
used to configure the input equations for the flipflop and the output of the logic
block.
 The advantage of using RAM instead of ROM to store the truth table is that the table can be
programmed by writing into memory.
 The disadvantage is that the memory is volatile and presents the need for the lookup
table’s content to be reloaded in the event that power is disrupted. The program can be
downloaded either from a host computer or from an onboard PROM.
 The program remains in SRAM until the FPGA is reprogrammed or the power is turned
off. The device must be reprogrammed every time power is turned on.
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APPLICATION SPECIFIC –ICs
Explain in detail about application specific –IC (ASIC).
 The acronym ASIC stands for Application Specific Integrated Circuit.
 ICs are made on a thin circular silicon wafer, with each wafer holding hundreds of die.
 The transistors and wiring are made from many layers built on top of one other.
 The types of ASIC are
1. Full custom ASIC
2. Standard cell based ASIC
3. Gate array based ASIC
Full custom ASIC:
 In full custom ASIC, an engineer designs some or all of the logic cells, circuits or layout
specifically for one ASIC.
 This is used only if existing cell libraries are not fast enough or the logic cells are not small
enough or consume too much power.
Standard cell based ASIC:
 A cell based ASIC uses predesigned logic cells (e.g., AND gates, Multiplexers, flip flops etc.,)
known as standard cells.
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 The standard-cell areas may be used in combination with larger predesigned cells like
microcontrollers or microprocessors known as mega cells.
 A cell based ASIC having four fixed blocks. The flexible block contains row of standard cells.
Gate array based ASIC:
 In a gate array based ASIC the transistors are predefined on the silicon wafer.
 The predefined pattern of transistors on a gate array is the base array, and the smallest element
that is replicated to make the base array is the base cell.
 Only the top few layers or metal, which define the interconnect between transistors, are defined
by the designer using custom marks.
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TWO MARKS
1. What is combinational PLD?[Nov/Dec 2007]
The PROM is a combinational programmable logic device (combinational PLD). The
combinational PLD is an integrated circuit with programmable gates divided in to an AND array and
an OR array to provide an AND-OR sum of product implementation.
2. What are the types of combinational PLDs?
1. They are used to implement combinational circuits
2. Registers PALs can be used to implement sequential circuits.
3. They can be programmed to use as code converters.
4. They are used as a combinational logic in addressing decoding section of a
microprocessor based systems.
3. What is FPGA? [Nov/Dec 2004,April/May 2006,Nov/Dec 2014,Nov 2018]
FPGA stands for Field Programmable Gate Array, which is the next generation in the
programmable PLDs. The word ‘field’ refers to the ability of the gate arrays to be programmed for
a specific function by the end user. The word ‘array’ indicates a series of columns and rows of
gates that can be programmed by the end user.
4. What is a FIFO memory?
The term FIFO refers to the basic operation of this type of memory in which the first data bit
written into the memory is to first to be read out.
5.
How many words can a 16x8 memory can store?
A 16x8 memory can store 16,384 words of eight bits each to be stored
Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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6. Give the feature of UV EPROM
UV EPROM is electrically programmable by the user, but the store data must be erased by
exposure to ultra violet light over a period of several minutes.
7. What are the terms that determine the size of a PAL?
The size of a PLA is specified by the
a. Number of inputs
b. Number of products terms
c. Number of outputs.
8. Define a bus.
A bus is a set of conductive paths that serve to interconnect two or more functional
components of a system or several diverse systems.
9. Define Cache memory.
Cache memory is a relatively small, high-speed memory that can store the most recently used
instructions or data from larger but slower main memory.
10. What is flash memory? [Nov/Dec 2014]
Flash memories are high-density nonvolatile read/write memories . Flash memory combines the low
cost and high density features of an UV EPROM and the in-circuit electrical erasability feature of
EEPROM without compromising the high-speed access of both. Structurally, the memory cell of a
flash memory is like that of an EPROM.
11. List the configurable elements in the FPGA architecture.
The FPGA architecture consists of three types of configurable elements.
A perimeter of Input / Output Blocks(IOBs)
A core array of configurable Logic Blocks(CLBs)
Resources for interconnection.
12. List the advantages of PLD. (or) List the advantages of using sequential programmable devices.
(Apr 2019)
1. Construction is simple
2. It consists of any number of input variables.
3. Low cost
4. Implementation is easy
13. Why the input variables to a PAL are buffered?
The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs
to which available or its complement can be connected.
Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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Problems:
Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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Problem:
Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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**************************
[NOV / DEC 2020]
A 12-bit Hamming code word containing 8 bits of data and 4 parity bits is read from
memory. What was the original 8-bit data word that was written into memory if the 12-bit word
read out is as follows:
a) 000011101010
b) 101110000110
c) 101111110100
Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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SOLUTION:
a) C1(1,3,5,7,9,11) = 0,0,1,1,1,1 = 0
C2 (2,3,6,7,10,11) = 0,0,1,1,0,1 = 1
C4 (4,5,6,7,12) = 0,1,1,1,0 = 1
C8 (8,9,10,11,12) = 0,1,0,1,0 = 0
C = 0110
(Data-bits are 3 5 6 7 9 10 11 12)
Error in bit 6 => Corrected 8-bit data = 0 1 0 1 1 0 1 0
b) C1(1,3,5,7,9,11) = 1,1,1,0,0,1 = 0
C2(2,3,6,7,10,11) = 0,1,0,0,1,1 = 1
C4(4,5,6,7,12) = 1,1,0,0,0 = 0
C8(8,9,10,11,12) = 0,0,1,1,0 = 0
C = 0010 ( Parity bit)
(Data-bits are 3 5 6 7 9 10 11 12)
Error in bit 2 => Corrected 8-bit data = 1 1 0 0 0 1 1 0
c) C = 0000
No Error
8-bit Data = 1 1 1 1 0 1 0 0
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[NOV / DEC 2020]
List the PLA and PAL programming table for the BCD to Excess-3 code convert whose Boolean
function are simplified as
w = A + BC + BD,
x = B′C + B′D + BC′D,
y = CD + C′D,
z = D’.
SOLUTION:
Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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PLA:
PAL:
Mrs.T.Priyadarsini, Asst.Prof., /ECE VRS College of Engg & Tech, Arasur
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