ELEN E4215:
Analog Filter Design & Synthesis
Discrete Time Analog Filters
Columbia University
Fall 2019
Tod Dickson, Ph.D.
todickso@us.ibm.com
Research Staff Member, IBM T.J. Watson Research Center
Adjunct Professor, Columbia University
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Reading
 Schaumann Chapter 17
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Active CT Filters Drawbacks
 Filter parameters (ω0, Q, cutoff frequencies,
etc) depend on product or ratio of unlike
items (RC time constants, Gm/C ratios, etc)
 Tuning methods exist, but typically requires
additional circuitry with power/area overhead.
Often relies on matching between the tuning and
actual circuitry.
 For good accuracy, we are better off relying
on ratios of like items (as is the case with a
lot of analog design).
 Cannot build integrators only out of resistors,
since they don’t store charge…
 What about a filter topology that depends on a
ratio of capacitors?
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Switched-Capacitor Resistor
Equivalent
φ1, φ2 are non-overlapping clocks. Only one on at a time.
φ1 on: V1 charges up C1.
Q1 = C1V1
φ2 on: V2 charges up C1.
Q2 = C1V2
Over one full clock cycle, the change in charge of C1 is ∆Q = C1∆V = C1 (V1 − V2 )
The average current over one clock cycle is
I avg =
Req =
Equivalent to a resistor:
∆Q C1 (V1 − V2 )
=
T
T
V1 − V2 T
1
=
=
I avg
C1 f s C1
1
= 1MΩ
Example: 1MHz clock, 1pF cap
1MHz × 1 pF
This is an approximation that assumes the signals on V1 and V2
vary slowly with respect to the clock frequency. More later…
Req =
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Non-Overlapping Clock Generator
Common non-overlapping clock generator is based on an
S-R flip-flop. Recall:
NOR gate outputs a logic 0 when one or both of its inputs = 1.
Expectation is that set (S) and reset (R) are not asserted high at
the same time.
When S is asserted, Q = 0, Q = 1.
When R is asserted, Q = 0, Q = 1.
If S and R are complimentary (differential) clocks, these are the
only two states we care about
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Non-Overlapping Clock Generator
Putting a delay in the ‘feedback’ path causes
both outputs φ1 and φ2 to be 0 until the
appropriate signal has propagated through
the delay.
φ
T=
φ
1
fs
φ
φ1
φ2
delay
n-1
n-(1/2)
End of φ1: integer samples.
n
n+(1/2)
n+1
End of φ2: ½ off integer samples.
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Integrator Time Constant
CA
RA
vi
+
Topology
Unity Gain
Tolerance
vo
Approximation! Need to analyze the discrete
time transfer function – more later
Op-amp RC Integrator
1
ω0 =
RAC A
Switched-Cap Integrator
ω0 ≈
Depends on absolute
values of R and C, which
may vary by +/- 20%
1
C
= fs × 1
REQC2
C2
Depends on clock period (usually
accurate to within a few ppm)
and ratio of capacitors (accurate
to within a few percent,
depending on area)
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Discrete Time Signaling
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Sampled Signals
Consider a continuous time signal
x (t )
We wish to sample this signal every T
seconds. This operation can be expressed
mathematically by multiplying x (t ) with a train
of impulses s (t )
+∞
+∞
n = −∞
n = −∞
xS (t ) = x (t )s (t ) = x (t )  δ (t − nT ) = x (nT )  δ (t − nT )
The Laplace transform of the sampled signal is
X S (s ) =
∞
 x (nT )e
− snT
s
n = −∞
Spectrum of the sampled signal is
1 +∞
X s ( jω ) =  X [ j (ω − ωc )]
T n = −∞
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Spectrum of Discrete-Time Signals
1
X ( jω )
Spectrum of the continuous signal is
ω
1
T
X ( jω )
X s ( jω )
Spectrum of the sampled signal is
ωB
n =0→
ωc
1
X ( jω )
T
(CT spectrum)
ω
2ωc
k =1→
1 +∞
X s ( jω ) =  X [ j (ω − ωc )]
T n = −∞
1
X ( j (ω − ωc ))
T
(CT spectrum shifted by ωc)
Can see by inspection – if X(jω) has frequency content beyond ωc/2 (or
fs/2), there will be overlap. If the signal X(jω) is not band limited, an
anti-aliasing filter is required.
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Z-Transform
Laplace transform of sampled signal:
X S (s ) =
 x (nT )e
− snT
s
n = −∞
∞
X (z ) ≡  xs (nT )z
Define z ≡ e and hence
n = −∞
Mapping from s-plane to z-plane:
sT
∞
−n
z = z e jΩ = e (σ + jω )T
Magnitude: z = e
σT
LHP: inside unit circle
RHP: outside unit circle
Angle:
Ω = ωT
It is not a 1-to-1 mapping.
X(z) is not a function of the sampling rate, only of the samples. We often
normalize with respect to the sampling period T (as seen on the real &
imaginary axis on the s-plane plot).
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Z as a Delay Operator
X (z ) ≡
∞
 x (nT )z
−n
s
z = z e jΩ = e (σ + jω )T
n = −∞
Along the jω axis (σ = 0),
z − n = e − jωnT
is a pure delay of nT seconds
xs [nT ] → X (z )
xs [(n − 1)T ] → z −1 X (z )
1 

xs  n − T  → z −0.5 X (z )
2 

xs [(n + 1)T ] → z +1 X (z )
1 

xs  n + T  → z +0.5 X (z )
2 

This observation makes it convenient to derive z-domain transfer
functions using (e.g.) difference equations from a sampled data
system.
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Continuous-Time Analog System
with Discrete-Time Filter
continuous
x(n)
xin Anti-Aliasing
Filter
Sampled
System
Discrete-Time
Filter
fs
fs
continuous
Sample-andHold
fs
discrete
Filter processes discrete samples
Need a sample-and-hold to
translate “discrete” samples into
an “analog” waveform.
We need to account for the frequency response of the S/H in the overall
“continuous-time” system response.
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xsh
Zero-Order Hold Response
Impulse response of a zero-order hold is
 1 , 0 < t ≤ Ts
hZOH (t ) =  Ts
 0,
elsewhere
We take the Laplace transform of the impulse response to find
the transfer function:
1
H ZOH (s ) =  hZOH (t )e dt =
t = −∞
Ts
t =∞
− st

t =Ts
t =0
Substituting s=jω, and recalling that
1 − e − sTs
e dt =
sTs
− st
(e
sin ( x ) =
jx
− e − jx )
2j
we can evaluate the frequency response
1 − e − jωTs
H ZOH ( jω ) =
=
jωTs
e
−
jωTs
2
jωTs
− jπf
−
 e jωTs 2 − e − jωTs 2 
Ts 
ω

2
sin
e f s sin πf 

 e

2

=

 fs 
=
ωTs
πf
jωTs
fs
2
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Zero-Order Hold Response
sin πf  − jπf
fs 
H ZOH ( jω ) = 
e
πf
fs
fs
sin  πf 
 fs 
H ZOH (ω ) =
πf
fs
sin (π )
At f = fs,
H ZOH ( f = f s ) =
At f = fs/2
π
f s  sin 2

=2
H ZOH  f =
= π
2
π


2
π
=0
( )
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(-3.9dB)
CT to DT Mapping
Continuous-time analog filter design techniques are well-understood.
If we have a continuous-time transfer function HCT(sct), how can we
generate an equivalent discrete-time transfer function HDT(z)?
One way…
z ≡ e sctT → sct =
1
ln(z )
T
T is the sampling period
Plug in expression for sct into the known CT transfer function.
1


H DT (z ) = H CT  sct = ln (z )
T


This will result in DT transfer functions that depend on ln(z).
Not very practical, since they cannot be realized.
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Bilinear Transformation
More practical method is to approximate this relationship.
z ≡ e sctT =
e
e
( 2)
sct T
( 2)
− sct T
Taking only the first-order terms in the Taylor series…
T
2
z≈
T
1 − sct
2
1 + sct
or, solving for s we get
sct ≈
ex ≈ 1+ x
2 z −1
T z +1
This is known as the Bilinear transformation. It is a conformal
mapping of points on the s-plane to points on the z-plane.
Example: Low-pass RC
H CT (sct ) =
1
1 + sct RC
1 + z −1
2 z −1
1

H DT (z ) = H CT  sct =
=
=
2
z
1
−
T
z
1
+


 2 RC  −1  2 RC 

 1 + RC
 T z + 1 1 + T  + z 1 − T 
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Bilinear Transformation
Any ramifications of the approximation used in bilinear transformation?
Observations:
1) z=+1 is mapped to s = 0 (dc is preserved)
2 z −1
sct ≈
2) z=-1 is mapped to s = infinite (not fs/2)
T z +1
3) Points on the unit circle in the z-plane are
mapped to points on the imaginary axis of
the s-plane (stability is preserved)
 2 z −1
Find the freq response of H DT (z ) = H CT 
 and compare to that of H CT ( jωct )
 T z +1
2 e
H DT (e jωT ) = H CT 
jωT
T e
jωT

 ωT  
 j sin 

−1
2
2

  = H  j 2 tan ωT  
 = H CT 


CT
T
+1
T
2
 ωT  



 cos 2  

 

If HCT has a desired response at frequency ω,
HDT will have that response at a frequency ωct.
This is called frequency warping.
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ωct =
2
 ωT 
tan

T
2


Frequency Warping: Graphical View
ωct =
ω=
Frequencies over an interval
− ∞ ≤ ωct ≤ ∞
are compressed into a finite range
−
ωc
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2
≤ω ≤
ωc
2
2
 ωT 
tan

T
2


2
ω T 
tan −1  ct 
T
 2 
Bilinear Transformation
As an example, go back to our simple first-order low pass filter
H DT (z ) =
1
 2 z − 1
1 + RC 
 T z + 1
H DT (e jωT ) =
1
1
=
 2 e jωT − 1
2
 ωT 
1
+
RC
j
tan
1 + RC 


jωT

T
2
T
e
+
1





You design the RC filter expecting a cutoff frequency of
But what you actually get is
ω = ω3dB ,actual =
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2
1
T 1 
tan −1 
<
T
 2 RC  RC
ωct = ω3dB =
1
RC
Graphical View
H (s ) =
1
1 + sRC
− 3dB
H1
Apply bilinear transform
1
RC
2
T 1 
tan 

T
 2 RC 
H d (e jωT )
− 3dB
H1
2
T 1  1
tan −1 
 RC
T
 2 RC 
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Techniques to Deal with Frequency
Warping
Technique #1: Account for warping when designing the CT transfer
function. “Pre-warp” the poles and zeros of the CT transfer function,
adjusting their values (higher) to account for the frequency warping.
If we want a pole in our final DT design to occur at ω p
then we should design our original CT transfer function to have a pole at
ω T 
2
ωct , p = tan p 
T
 2 
Returning to our RC example, we pre-warp the CT pole to
ω T  2
2
 T 
ωct , p = tan  p  = tan

T
 2 
T
 2 RC 
After applying the bilinear transform, our pole will be located at
ωp =
2
1
T 2
T
 2
 T 
tan −1  ωct , p  = tan −1 
tan
 =
T
2
 T
 2 RC   RC
2T
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Techniques to Deal with Frequency
Warping
Technique #2: Use a high sampling rate relative to the signal frequency
(i.e., ‘oversample’)
2
ωT
 ωT  2 ωT
ωct = tan 
=ω
<< 1
≈
If
then
T
2
T 2
2


In other words, if we sample at a much higher rate than the frequencies of
interest in the filter, then the warping will be small.
Oversampling restricts our operation
to this portion of the frequency
mapping curve where its behavior is
linear
Same concept as making a
‘continuous-time’ approximation with
regards to the switched-capacitor
resistor we looked at earlier.
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Switched Capacitor Filters
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Integrator
Input charges C1
Stored charge is
transferred to the output
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Integrator
Sampling Phase
Input charges C1
Q1 [(n − 1)T ] = C1vci [(n − 1)T ]
C2 holds its charge from
previous half-cycle

3 
Q2 [(n − 1)T ] = Q2  n − T 
2 

Charge Transfer Phase
Op-amp forces 0 voltage on C1

1 
Q1  n − T  = 0
2 

Charge that had been stored on C1 is
transferred to C2, adding to the charge
that was already stored on C2.

1 
Q2  n − T  = Q2 [(n − 1)T ] + Q1 [(n − 1)T ]
2 

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Integrator
The output is taken on the

1 
[
]
Q
nT
=
Q
n
−

T  = Q2 [(n − 1)T ] + Q1 [(n − 1)T ]
next cycle of φ1, during which
2
2
2 

the charge on C2 is held.
Q
Noting that v = − Q2 and vci = 1
co
C1
C2
C2vco [nT ] = C2vco [(n − 1)T ] − C1vci [(n − 1)T ]
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Integrator
We can rewrite the difference
equation to get a z-domain
transfer function.
C2vco [nT ] = C2vco [(n − 1)T ] − C1vci [(n − 1)T ]
C2Vo (z ) = C2 z −1Vo (z ) − C1 z −1Vi ( z )
Vo ( z )
C1 z −1
H (z ) =
=−
Vi (z )
C2 1 − z −1
Pole at z = +1 (marginally stable, same as a CT integrator).
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Integrator Parasitics
Parasitic top and bottom plate
capacitances can impact the transfer
function.
Cp2 is always connected to ground
Cp3 is at “virtual ground”
Cp4 has same impact as output
capacitance of op-amp. May impact
settling behavior, but not transfer
function.
Cp1 appears in parallel with C1, hence
the actual transfer function is
(
C1 + C p1 ) z −1
Vo ( z )
H (z ) =
=−
Vi (z )
C2
1 − z −1
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Parasitic-Insensitive Integrator
Same operation as before, but no parasitics appear in parallel with
C1 or C2 hence parasitics don’t steal charge.
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Parasitic-Insensitive Integrator
Can see that charge transfer operation is same as parasiticsensitive integrator.
Note that since charge is always taken out of the opposite
terminal of the capacitor, we have two net signal inversions and
hence the overall transfer function is non-inverting.
Vo ( z ) C1 z −1
H (z ) =
=
Vi ( z ) C2 1 − z −1
Disadvantage: Two extra switches that need to be driven by the
clocking network, which results in extra power dissipation. But this is
almost always acceptable to achieve more accurate transfer function.
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Delay-Free Integrator
Note clock phases are swapped…
1 
1 


Q  n − T  = vco  n − T C2 = vco [(n − 1)T ]C2
2 
2 


φ2: Output holds its
previous value
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Delay-Free Integrator
Q[nT ] = vic [nT ]C1 + voc [nT ]C2
H (z ) =
φ1: New input sample
causes current flow onto
C1, which also charges C2.
Vo (z )
C
1
=− 1
Vi (z )
C2 1 − z −1
Same integrator transfer function,
but without the z-1 delay in the
numerator
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Signal Flow Analysis
Writing difference equations
for charge redistribution in
larger circuits can be
cumbersome.
V1 ( z )
V2 (z )
V3 ( z )
(
− C1 1 − z −1
)
C2 z −1
+
1  1 


C A  1 − z −1 
− C3
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Instead, we can develop a
“signal flow” analysis based
on the smaller circuits
already analyzed and apply
this to derive transfer
functions of larger switched
capacitor circuits.
Vo ( z )
General First-Order Filter
R2
R1
H (s ) =
C2
Vout (s )
Z
R 1 + sR1C1
=− 2 =− 2×
Vin (s )
Z1
R1 1 + sR2C2
C1
Can implement resistors with switched-capacitor equivalents to
realize a discrete-time filter. Specifically, R1 & R2 are replaced
by delay-free switched caps.
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Switched-Cap Realization
Signal flow graph representation:
− C3
− C2
Vi ( z )
(
− C1 1 − z
−1
)
+
1  1 


C A  1 − z −1 
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Vo ( z )
Switched-Cap Realization
− C3
− C2
Vi ( z )
(
− C1 1 − z
[ (
−1
+
)
)]
1  1 


C A  1 − z −1 
(
Vo ( z )
)
Vo ( z ) C A 1 − z −1 = −C1 1 − z −1 Vi ( z ) − C2Vi ( z ) − C3Vo ( z )
 C1 + C2 
C

 z − 1
CA  CA
V (z )
H (z ) = o
=−
Vi ( z )
 C3 
1 +
 z − 1
 CA 
Pole @
Zero @
zp =
CA
C A + C3
zz =
DC gain found by setting z = 1, yielding
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which is always less
than 1, so filter is
always stable
C1
C1 + C2
H (1) = −
C2
C3
Switch Sharing
These switches are redundant.
During φ1, top plates of C2 and C3 are connected together.
During φ2, top plates of C2 and C3 are both connected to ground.
2
Recall that for CMOS digital circuits (i.e. clock buffers), P ∝ CV f
Minimizing the # of switches will reduce capacitance and lower
the power dissipation.
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Switch Sharing
Vi ( z )
Vo ( z )
More efficient implementation. In general, two nodes can share
switches if they are always connected to the same potential.
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Design Example
We want to build a filter than has a DC gain of 2, a 3-dB frequency
of 200kHz and a transmission zero at 500 kHz.
The clock rate is 1 MHz.
Solution: Use the bilinear transform to map the pole/zero locations
to the z-plane.
2 z −1
sct ≈
T z +1
The zero at 500kHz (fs/2) is mapped to z = -1.
Knowing that frequency warping will occur, we need to pre-warp the
location of the pole. If the pole is desired to be located at fp, we
need to pre-warp to a value fct,p.
ωct , p = 2πf ct , p =
 πf 
ω T 
2
 π × 200kHz 
tan p  = 2 f s tan p  = 2 × 1MHz × tan
 = 2π × 231kHz
T
 1MHz 
 2 
 fs 
~15% higher
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Design Example
This corresponds to an s-domain pole location of
s p = −2π × 231kHz
Now we can use the bilinear transform to map this to a z-plane pole.
2π × 231kHz
T 1+ sp
1+ sp
1−
2 fs
2 =
2 × 1MHz = 0.1584
zp =
=
2π × 231kHz
T
sp
1− sp
1
+
1−
2
2 ×1MHz
2 fs
The z-domain transfer function is
H (z ) =
k (z + 1)
z − 0.1584
Set k to meet the DC gain requirements (z=1)
H (z ) =
0.8416( z + 1) 5.3131z + 5.3131
=
z − 0.1584
6.3131z − 1
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Design Example
Equate the transfer function coefficients to solve for the required
capacitance values.
Note that for a zero at -1
 C1 + C2 
C1

H (z ) = − 
 z −
 C A = 5.3131z + 5.3131
6.3131z − 1
 C3 
1 +
 z − 1
 CA 
CA
Choose CA arbitrarily, say 1pF.
zz =
C1
C1 + C2
we need C1 = −
C A = 1 pF
C1 = 5.313 pF
C2 = −10.626 pF
C3 = 5.313 pF
C2
2
− C3
Negative capacitance
can be realized in a
fully differential
implementation by
wiring to opposite input
as shown.
− Vi ( z )
Vi ( z )
− C2
(
− C1 1 − z −1
T. Dickson © 2019
)
+
1  1 


C A  1 − z −1 
Vo ( z )
Fully-Differential Filter Topology
This implements a
negative C1
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RHP Zero
R2
− R1
H (s ) =
Vout (s )
Z
R − 1 + sR1C1
=− 2 = 2×
Vin (s )
Z1 R1 1 + sR2C2
C2
C1
Switched-cap equivalent to a ‘negative resistor’ can be
implemented by changing polarity of input sampling clocks
CA
LHP Zero
CA
RHP Zero
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RHP Zero
Note that input is sampled onto C2
during φ2. No change in signal flow
analysis as long as
1 

vi  n − T  = vi [(n − 1)T ]
2 

CA
(this was true for a delay-free integrator)
 C + C2 
C1

z −  1
CA
C
Vo (z )
A


H (z ) =
=−
Vi (z )
 C3 
1 +
 z − 1
C
A

− C3
−1
C
−2Cz 2
Vi ( z )
(
− C1 1 − z −1
[
)
+
1  1 


C A  1 − z −1 
Vo ( z )
Pole @
Zero @
]
Vo (z ) C A (1 − z −1 ) = −C1 (1 − z −1 )Vi (z ) + C2 z −1Vi (z ) − C3Vo (z )
T. Dickson © 2019
zp =
CA
C A + C3
zz =
C1 + C2
C1
Zero is outside unit circle,
equivalent to RHP in s-domain.
Switched Capacitor Biquads
T. Dickson © 2019
Active-RC Biquad Review…
RB
RA
CA
CA '
C1
RA '
-
VI
R1
(R A = R A ' , C A = C A ' )
-
+
-1
+
Vo
R2
To convert to a switched-capacitor biquad, we simply
• Replace resistors with their switched capacitor equivalents
• Non-inverting and inverting integrators can be implemented
using delayed and delay-free switched capacitor structures
T. Dickson © 2019
SC Biquad (CT Equivalence)
Determine the ‘equivalent resistance’ for a switched-capacitor
circuit implementing the functionality of R1, R2, RA, and RB.
Cx
Cx
or
Rx =
RA →
1
f sCRA
RB →
1
f s C RB
1
f sC x
R1 →
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1
f sCR1
R2 →
1
f sCR2
Biquad Transfer Function (CT)
H (s ) =
KH s2 + KB
s2 + s
ω0
Q
ω0
Q
s + K Lω0
+ ω0
2
2
Continuous-time (Active-RC) circuit:
1
ω0 =
RAC A
Q=
RB
RA
KH = −
C1
CA
KB =
− RB
R1
KL = −
Switched-capacitor equivalent (assuming ωT << 1 )
ω0 = f s
C
KH = − 1
CA
CRA
CA
CRA
1
Q=
=
f sCRB RA CRB
KB = −
C R1
C RB
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KL = −
CR2
CRA
RA '
R2
Example: SC BPF
Continuous-time (Active-RC) circuit:
f
ω0 = s
Q = 10
50
KB = 5
We can make a continuous-time approximation since ω0 << f s
All capacitors will be sized relative to an arbitrary integrator
capacitor CA
C RA
Cω
C
ω0 = f s
→ CRA = A 0 = A
CA
fs
50
CR
CR
CA
C
Q = A → C RB = A =
= A
C RB
Q
50 × Q 500
KB =
CR1
C RB
→ CR1 = K B CRB =
5C A C A
=
500 100
Observation: High-Q SC biquads can result in large capacitance
spread. Would be better if we could decouple the ω0 & Q
interdependency.
T. Dickson © 2019
Tow-Thomas Biquad: High-Q
Alternative Architecture (BPF)
Signal injected one integrator earlier
RA
RB
Z B → RB ×
vi
ω0
Z B = QRA ×
CA
1
Q
=
RAC A s C A s
CA
s
R1
CB
-
-
+
RA
vo
 1 
ω

s 
KB 0 s
V
Q
 R1C A 
H (s ) = O = −
=
ω0
1 CB
1
2
VI
2
s2 + s
+
s
+
s
+ ω0
2
RAC A C A (RAC A )
Q
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-1
+
− v1
v1
Q=
CA
CB
CB =
CA
Q
Example: SC BPF w/ High-Q
Architecture
Use the high-Q biquad architecture to realize the same BP
transfer function
f
ω0 = s
KB = 5
Q = 10
50
ω0 = f s
CRA
CA
Q=
KB =
→ CRA =
C Aω0 C A
=
fs
50
CA
C
C
→ CB = A = A
CB
Q 10
CR1
C RB
(unchanged)
(much lower
capacitance spread)
→ CR1 = K B CRB = ????
How do we get center frequency gain without RB?
RA C A RA 1 CR1 1
C
KB =
=
=
→ C R1 = Q K B CRA = 50 A = C A
R1 CB R1 Q CRA Q
50
Not optimal – better to have KB independent of Q.
T. Dickson © 2019
Tow-Thomas Biquad: High-Q
Alternative Architecture (BPF)
Previously:
KB =
RB
R1
Z 2 → R1 ×
vi
RB
ω0
RA
CA
CA
s
R1
CB
-
-
+
RA
vo
C2
 C2 
ω

s
KB 0 s
V
Q
 C AC A RA 
=
H (s ) = O = −
ω0
1 CB
1
2
VI
2
+
+
+ ω0
s2 + s
s
s
2
RAC A C A (RAC A )
Q
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-1
+
− v1
v1
KB = −
C2
CB
Example: SC BPF w/ High-Q
Architecture
Use the high-Q biquad architecture to realize the same BP
transfer function
f
ω0 = s
KB = 5
Q = 10
50
ω0 = f s
CRA
CA
Q=
KB =
→ CRA =
C Aω0 C A
=
fs
50
CA
C
C
→ CB = A = A
CB
Q 10
C2
C
5C
→ C2 = K B C B = A = A
CB
10
2
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(unchanged)
(much lower
capacitance spread)
Complete Active-RC Biquad
Starting point for SC biquad
‘Negative resistors’ can be
realized by changing polarity of
switching clock phases
Allows for changing gain
polarity and/or implementing
RHP zeros
H (s ) =
V2
=−
Vin
s2
[C (G − G12 ) + C4G9 ] + G9 (G6 − G7 )
C5
+ s 1 11
C2
C1C2
C1C2
[C G + C3G9 ] + G8G9
s 2 + s 1 10
C1C2
C1C2
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SC Implementation
For SC ‘resistors’:
Gx = f sC x
‘Negative resistors’
implemented with ‘delayed’
switches
‘Positive resistors’
implemented with ‘delay-free’
switches
T. Dickson © 2019
SC Implementation
H (s ) =
V2
=−
Vin
s2
[C (G − G12 ) + C4G9 ] + G9 (G6 − G7 )
C5
+ s 1 11
C2
C1C2
C1C2
[C G + C3G9 ] + G8G9
s 2 + s 1 10
C1C2
C1C2
Gx = f sC x
H (s ) =
V2
=−
Vin
s2
[C (C − C12 ) + C4C9 ] + f 2 C9 (C6 − C7 )
C5
+ sf s 1 11
s
C2
C1C2
C1C2
[C C + C3C9 ] + f 2 C8C9
s 2 + sf s 1 10
s
C1C2
C1C2
(Switch sharing not shown –
see textbook)
T. Dickson © 2019
SC: Sampled Data Operation
Recall signal flow graph techniques for SC circuits:
Signals entering the 1st integrator:
[
]
[
]
[
]
V1 (z ) C1 (1 − z −1 ) = Vin (z ) − C6 + C7 z −1 − C4 (1 − z −1 ) + V2 (z ) − C8 − C3 (1 − z −1 )
1 1 
1 1 
−1
−1
(
)
(
)
V1 (z ) = Vin (z )
−
C
+
C
z
−
C
1
−
z
+
V
z
− C8 − C3 (1 − z −1 )
6
7
4
2

−1 
−1 
 C1 1 − z 
 C1 1 − z 
[
]
T. Dickson © 2019
[
]
SC: Sampled Data Operation
Recall signal flow graph techniques for SC circuits:
Signals entering the 2nd integrator:
[
]
[
]
[
]
V2 (z ) C2 (1 − z −1 ) = Vin (z ) − C11 + C12 z −1 − C5 (1 − z −1 ) + V1 (z ) C9 z −1 − V2 (z )C10
T. Dickson © 2019
SC: Sampled Data Operation
V2 (z )
C1C5 (1 − z −1 ) + (C1 (C11 − C12 z −1 ) + C4C9 z −1 )(1 − z −1 ) + C9 z −1 (C6 − C7 z −1 )
=−
2
Vin (z )
C1C2 (1 − z −1 ) + (C1C10 + C3C9 z −1 )(1 − z −1 ) + C8C9 z −1
2
To check this, let’s compare with our ‘CT approximation’
z ≡ e sT
For
z = e jωT ≈ 1
ωT << 1
1 − z −1 = 1 − e − jωT ≈ 1 − [1 − jωT ] = jωT
2
 jω 

 + (C1 (C11 − C12 ) + C4C9 )
C1C5 
V2
 fs 

=−
2
Vin
 jω 

 + (C1C10 + C3C9 )
C1C2 
 fs 

(e
x
≈ 1 + x)
jω 
 + C9 (C6 − C7 )
f s 
jω 
 + C8C9
f s 
As expected, this is identical to our ‘CT approximation’ derived
earlier (for jω = s)
T. Dickson © 2019
Biquad Z-Domain Transfer Function
V2 (z )
C1C5 (1 − z −1 ) + (C1 (C11 − C12 z −1 ) + C4C9 z −1 )(1 − z −1 ) + C9 z −1 (C6 − C7 z −1 )
=−
2
Vin (z )
C1C2 (1 − z −1 ) + (C1C10 + C3C9 z −1 )(1 − z −1 ) + C8C9 z −1
2
While this form is convenient for comparing to CT approximation, it is
not helpful if in implementing a z-domain TF in polynomial form.
Instead, we group coefficients for z-1 and z-2 terms (or z2 and z
terms)
V2 (z )
z 2C1 (C5 + C11 ) + z[C9 (C4 + C6 ) − C1 (2C5 + C11 + C12 )] + C1 (C5 + C12 ) − C9 (C7 + C4 )
=−
Vin (z )
z 2C1 (C2 + C10 ) + z [C9 (C3 + C8 ) − C1 (C10 + 2C2 )] + (C1C2 − C3C9 )
Too many degrees of freedom to develop a design methodology – let’s
see how we can simplify.
T. Dickson © 2019
Z-Domain TF Simplification (1)
V2 (z )
z 2C1 (C5 + C11 ) + z [C9 (C4 + C6 ) − C1 (2C5 + C11 + C12 )] + C1 (C5 + C12 ) − C9 (C7 + C4 )
=−
Vin (z )
z 2C1 (C2 + C10 ) + z [C9 (C3 + C8 ) − C1 (C10 + 2C2 )] + (C1C2 − C3C9 )
C4 & C5 are not required. The same contributions to the TF could
have been made by C6 and C7 (for C4), and C11 and C12 (for C5).
This could have been noted from the signal flow graph analysis:
C4 & C5 serve as discrete-time differentiators. Same functionality is
achieved through appropriate sizings of C6, C7, C11, and C12.
T. Dickson © 2019
Z-Domain TF Simplification (2)
V2 (z )
z 2C1 (C11 ) + z [C9C6 − C1 (C11 + C12 )] + C1C12 − C9C7
=− 2
Vin (z )
z C1 (C2 + C10 ) + z [C9 (C3 + C8 ) − C1 (C10 + 2C2 )] + (C1C2 − C3C9 )
C1 or C9 are a coefficient
in every term. We can set
C1 = C9 = C.
Recall that C1 & C2 are the
integrator capacitors.
Hence it makes sense to
set C1 = C2 = C.
Enough degrees of
V2 (z )
z 2C11 + z [C6 − C11 − C12 ] + (C12 − C7 )
freedom to independently
=− 2
Vin (z )
z (C + C10 ) + z [C3 + C8 − C10 − 2C ] + (C − C3 ) set all TF coefficients
T. Dickson © 2019
Example
 Design a 2nd order switched-capacitor high-pass filter
with 6dB high-frequency gain, 42 kHz natural frequency,
and Q = 3. The sampling frequency is 512 kHz.
The continuous-time transfer function that meets these
requirements is
2
2
KH s
H (s ) =
s2 +
ω0
Q
s + ω02
=
2s
(2π × 42kHz ) s + (2π × 42kHz )2
s2 +
3
We start by pre-warping the pole natural frequency
ωct ,0 =
 πf 
2
ω T 
 π × 42kHz 
tan  0  = 2 f s tan  0  = 2 × 512kHz × tan 
 = 2π × 42.955kHz
T
 2 
 512kHz 
 fs 
(Hasn’t changed significantly as there isn’t much warping at
this frequency relative to the sampling frequency)
T. Dickson © 2019
Example
We modified the CT transfer function based on the prewarped pole natural frequency:
K H sct2
H (sct ) =
sct2 +
ωct ,0
Q
s + ωct2 ,0
2 sct2
=
(2π × 42.955kHz ) s + (2π × 42.955kHz )2
sct2 +
3
Next, we apply the bilinear transformation to develop a zdomain transfer function
sct ≈
2 z −1
z −1
= 2 fs
T z +1
z +1
2
z −1

KH  2 fs

2
z −1
K H (2 f s (z − 1))
z + 1


H  2 fs
=
=
2
ωct ,0
z
+
1
2
2
ω
2

 
z −1
z −1
2
ct , 0 
(
(
)
)
(
(
)(
)
)
(
)
2
f
z
−
1
+
2
f
z
−
1
z
+
1
+
ω
z
+
1
ω
2
f
2
f
+
+
s
s
ct
,
0
 s

 s

ct , 0
Q
z + 1
Q 
z + 1

T. Dickson © 2019
Example
Re-write the transfer function as a ratio of polynomials:
z 2 (4QK H f s2 ) − z (8QK H f s2 ) + (4QK H f s2 )
H (z ) = 2
z (4Qf s2 + 2ω0 f s + Qω02 ) + z (2Qω02 − 8Qf s2 ) + (4Qf s2 + Qω02 − 2ω0 f s )
Normalize by dividing all coefficients by
4Qf s2 + 2ω0 f s + Qω02
After evaluating, the transfer function is:
1.7281z 2 − (2 × 1.7281)z + 1.7281
H (z ) =
z 2 − 1.6081z + 0.8482
T. Dickson © 2019
Example: Implementation
z C11 + z [C6 − C11 − C12 ] + (C12 − C7 )
1.7281z 2 − (2 × 1.7281)z + 1.7281
=
−
H (z ) =
z 2 − 1.6081z + 0.8482
z 2 (C + C10 ) + z [C3 + C8 − C10 − 2C ] + (C − C3 )
2
By inspection, we set C10 = 0,
and all capacitors can be
expressed as a ratio of C,
e.g.:
C11
= 1.7281
C
To obtain the appropriate
numerator, we can set
C6 = C7 = 0, and then
C11 = C12 = 1.7281C
T. Dickson © 2019
Example: Implementation
z C11 + z [C6 − C11 − C12 ] + (C12 − C7 )
1.7281z 2 − (2 × 1.7281)z + 1.7281
=
−
H (z ) =
z 2 − 1.6081z + 0.8482
z 2 (C + C10 ) + z [C3 + C8 − C10 − 2C ] + (C − C3 )
2
To obtain the appropriate
denominator, we must size
C10 = 0
C − C3
= 0.8482
C
C3 = (1 − 0.8482 )C = 0.1518C
C3 + C8 − 2C = −1.6081C
(1 − 0.8482 )C + C8 − 2C = −1.6081C
C8 = 0.2401C
T. Dickson © 2019
Example: Implementation
z C11 + z [C6 − C11 − C12 ] + (C12 − C7 )
1.7281z 2 − (2 × 1.7281)z + 1.7281
=
−
H (z ) =
z 2 − 1.6081z + 0.8482
z 2 (C + C10 ) + z [C3 + C8 − C10 − 2C ] + (C − C3 )
2
Final design values:
C = 10 pF
C11 = C12 = 17.28 pF
C8 = 2.40 pF
C3 = 1.52 pF
C6 = C7 = C10 = 0
T. Dickson © 2019
© 2019 T. Dickson
For student use in ELEN E4215
Unauthorized distribution is prohibited
T. Dickson © 2019