EE 751 (Nanomagnetism
and Spintronics)
Introduction, Module 1
Debanjan Bhowmik
Assistant Professor
Department of Electrical Engineering
Indian Institute of Technology Bombay
Nanomagnetism and Spintronics
(for traditional and neuromorphic computing)
Emphasis areas for this course:
1. Physics of nanomagnetism
2. Spin-transport physics
3. Spintronic devices for memory (traditional
computing)
4. Spintronics-based in-memory computing/
neuromorphic computing/ edge-device AI
5. Spintronics-based probabilistic computing
Modules
•
Module 1 (Introduction): Overview of different spintronic
devices in the context of traditional and neuromorphic
computing
•
Module 2 (Nanomagnetism): Brief introduction to theory
of ferromagnetism, Single-domain model (Landau
Lifschitz Gilbert equation), Micromagnetics
•
Module 3 (Spin transport): Magnetic Tunnel Junction
(MTJ), Spin-transfer torque (STT), Spin-orbit torque (SOT),
Landau Lifschitz Gilbert Slonczweski equation, Magnetic
Switching, Domain-Wall Dynamics
Modules
•
Module 4 (Spintronics-Based Memory Devices): Magnetic Hard
Drives, MRAM, STTMRAM, SOTMRAM, Domain-wall-based
Racetrack memory
•
Module 5 (Domain-wall-device-based Neuromorphic Computing):
Brief introduction to neural-network algorithms, Crossbar array
design, Domain-wall synapse device, On-chip learning
•
Module 6 (Spintronic-oscillator-based Neuromorphic
Computing): Oscillator-based learning algorithms, Spintronic
oscillators, Auto-oscillation and Synchronization Dynamics, On-chip
Learning
•
Module 7 (Stochastic-MTJ-based Probabilistic Computing):
Stochastic MTJ, Probabilistic bit (p-bit), p-bit-based computing,
equivalence with quantum computing (annealing based)
Evaluation Policy
•
Mid-sem exam: 30%
•
Major exam: 40 %
•
Assignment 1 on Device-Level Simulations (Module 2–3): 10 %
•
Assignment 2 on Device-Level Simulations (Module 5–7): 10 %
•
Assignment 3 on System-Level Simulations (Module 5–7): 10
%
(Assignment reports to be submitted individually)
Module 1 (Introduction)
Module 1 (Introduction)
•
•
•
•
•
•
•
Traditional Computing (from Turing machine to
von Neumann architecture)
Memory hierarchy in von Neumann
architecture
Role of spintronic devices in the memory
hierarchy
Magnetic hard drives
MRAM, Spin Transfer Torque MRAM, Spin
Orbit Torque MRAM
Non von Neumann computing/ Neuromorphic
Computing
Suitability of spintronics in neuromorphic
computing
Schematic of a Turing Machine (TM)
Current state
of the TM
Current state, Current symbol
(read by tape head)
-> New state, New symbol,
L or R (tape-head motion)
Instructions which
can be implemented
in hardware through
flip-flop circuits
(like in a DFA)
Church Turing thesis: This Turing Machine can implement a specific algorithm, and not a
generic algorithm. For every new algorithm, you need a new dedicated TM.
Reference and Figure-Source: ‘Computer Organization and
Architecture’ by Prof. Smruti Sarangi (Chapter 1)
A Universal Turing machine exists which can simulate any
other Turing machine M on any input w fed to the machine M
Single or
Multi-Tape:
Instructions for M
are written here
The input to M (w)
is stored and manipulated here
Instructions for UTM which
can be implemented
in hardware through
flip-flop circuits
(like in a DFA)
Universal Turing Machine (UTM)
an extra tape for
doing
arithmetic
Memory
Memory
ALU
+
control
unit
Description of the Turing machine (M) that the UTM is simulating
and the input w, which M manipulates, are both stored in the tape/ memory
as Instruction/ Program Memory and Data Memory respectively.
Translating UTM to
Computer Architecture
Description of the Turing machine (M) that the UTM is simulating
and the input w, which M manipulates, are both stored in the tape/ memory
as Instruction/ Program Memory and Data Memory respectively.
Harvard architecture and
Von Neumann archiecture
/ computing
/ computing
A program is stored
in the memory just
like data: stored-program
concept
Module 1 (Introduction)
•
•
•
•
•
•
•
Traditional Computing (from Turing machine to
von Neumann architecture)
Memory hierarchy in von Neumann
architecture
Role of spintronic devices in the memory
hierarchy
Magnetic hard drives
MRAM, Spin Transfer Torque MRAM, Spin
Orbit Torque MRAM
Non von Neumann computing/ Neuromorphic
Computing
Suitability of spintronics in neuromorphic
computing
Memory Hierarchy in
Von Neumann architecture
computing
memory
Wong, P.H.S. et al. Nature Nano. 10 (2015)
Module 1 (Introduction)
•
•
•
•
•
•
•
Traditional Computing (from Turing machine to
von Neumann architecture)
Memory hierarchy in von Neumann
architecture
Role of spintronic devices in the memory
hierarchy
Magnetic hard drives
MRAM, Spin Transfer Torque MRAM, Spin
Orbit Torque MRAM
Non von Neumann computing/ Neuromorphic
Computing
Suitability of spintronics in neuromorphic
computing
Data storage (Hard disk)
Dramatic increase in storage density and reduction in price, due to
advent of magnetoresistive read head (sensor to read data) in early 90s
Fullerton et al. Proceedings of the IEEE 104 (10), 2016
Data storage (Hard disk)
Before 1991, a coil that could generate and detect magnetic field was used simultaneously
as write head and read head.
After 1991, magnetoresistive heads started being used as read heads. Magnetoresistive heads
use magnetoresistance (spin transport effect) to detect magnetic field.
Fullerton et al. Proceedings of the IEEE 104 (10), 2016
Magnetoresistive Head
Anisotropic Magneto-Resistance (AMR):
Resistance difference is proportional to
M cos2(θ), where M is the magnetization
and θ is the angle
between magnetization direction
and the current.
Giant Magneto-Resistance (GMR):
Spin valve
Resistance difference is proportional
to M cos(θ),
where θ is the angle between the
magnetization of the free layer and
the pinned layer.
Fullerton et al. Proceedings of the IEEE 104 (10), 2016
Magnetoresistive Head
Tunnel junction
Origin of TMR
TMR can be 100% or higher.
Tunneling Magneto-Resistance (TMR)
based read head
TMR> GMR> AMR
Fullerton et al. Proceedings of the IEEE 104 (10), 2016
Module 1 (Introduction)
•
•
•
•
•
•
•
Traditional Computing (from Turing machine to
von Neumann architecture)
Memory hierarchy in von Neumann
architecture
Role of spintronic devices in the memory
hierarchy
Magnetic hard drives
MRAM, Spin Transfer Torque MRAM, Spin
Orbit Torque MRAM
Non von Neumann computing/ Neuromorphic
Computing
Suitability of spintronics in neuromorphic
computing
Cache and Main Memory (MRAM)
Alternative technologies:
SRAM
DRAM
Flash
Floating gate is charged
Flip flop circuit with 4
Transistor charges a
Transistors; Leftmost and rightmost Capacitor, every time capacitorup, based on charge in
transistors are for reading
Is read it has to be refreshed. floating gate, transistor is
on or off when a voltage
and writing
is applied on control gate
High density, cheap
Access time is low.
Very high speed,
Cheap
Access time very low
Non-volatile
High power
Write time is high
Consumption (refresh
Low density, expensive
Power for writing is high
cycle)
Low endurance
Wong, P.H.S. et al. Nature Nano. 10 (2015)
Memory (MRAM)
Organization of Magnetic Random
Access Memory (MRAM)
Switching due to Oersted field driven by current is not attractive due to Joule heati
and unscalability.
Apalkov et al. Proceedings of the IEEE 104 (10), 2016
Efficient way to switch the magnet:
Spin Transfer Torque (STT)
As conduction electrons pass through the polarizer (fixed magnetic layer) they become
spin polarized. Then in the free layer (FL), they transfer spin angular momentum to
the magnetization (M).
Apalkov et al. Proceedings of the IEEE 104 (10), 2016
Efficient way to switch the magnet:
Spin Transfer Torque (STT)
First generation MRAM:
Switching driven by Oersted
field due to current
Second generation MRAM:
Spin Transfer Torque MRAM
(STTMRAM)
Apalkov et al. Proceedings of the IEEE 104 (10), 2016
Alternative way to switch the magnet: Spin Orbit Torque
(SOT)
Instead of two ferromagnetic layers
separated by a spacer layer,
in this case, ferromagnetic metal
layer - heavy metal layer interface
is needed.
Miron, I. M. et al. Nature 476 (2011)
Liu, L. et al. Phys. Rev. Lett. 109 (2012)
Device structure (STTMRAM
and SOTMRAM)
Advantages of SOTMRAM:
i. Tunnel junction not damaged
while writing.
ii. Magnet is not switched while
reading
iii. Faster switching
iv. More choice of materials
Disadvantage of SOTMRAM:
i. 2 transistors are needed per
cell, hence more area occupied
ii.
Larger switching current density
Kim et al. IEEE Transactions on
Electron Devices 62, 2015.
Lee et al. Proceedings of IEEE
26
104 (10), 2016
Module 1 (Introduction)
•
•
•
•
•
•
•
Traditional Computing (from Turing machine to
von Neumann architecture)
Memory hierarchy in von Neumann
architecture
Role of spintronic devices in the memory
hierarchy
Magnetic hard drives
MRAM, Spin Transfer Torque MRAM, Spin
Orbit Torque MRAM
Non von Neumann computing/ Neuromorphic
Computing
Suitability of spintronics in neuromorphic
computing
Artificial Intelligence: Where modern
computer mimics human brain
Deep neural network,
implemented on
traditional computer
hardware, defeated
European champion in
the ancient game of
Go. Hardware- 170
GPUs and 1200 CPUs
needed.
IBM Blue Gene supercomputer simulates
cat’s cerebral cortex, but is 100 times slower!
Hardware- 147000 CPU-s, 144 TB memory
Artificial Intelligence: Where modern
computer mimics human brain
Virtual Assistant
Self driving car
Widely used Artificial Intelligence algorithm :
Neural Network
Object recognition using
convolutional NN A. Krizhvesky, I. Sutskever, G. Hinton, NIPS 25, 1090 (2012)
Y. LeCun et al., Nature 521, 436-444, 2015
Data classification using Neural Network (NN) algorithms
Supervised Learning
GIVEN!!
N Training
Inputs
{X1, X2, …
…..XN}
Wx calculation:
computing
f(Wx) calculation:
computing
Storing/ Reading W:
memory
GIVEN!!
Function
h (X)
NEEDS TO
BE ESTIMATED
(has to also work
on Test Dataset)
MODEL
h(X)= f(Wx)
Parameters/
Weight matrix
W
N Training
Outputs
{Y1, Y2, …
…..YN}
Algorithm/
Learning Rule
computing
Neural network algorithms need parallel computation
and frequent memory- computing interaction.
31
NN implemented on traditional von-Neumann architecture
Computation
happens here
Weight (w) matrix
stored here
Von Neumann bottleneck: Memory and computing are completely separate,
leads to slow speed and high energy dissipation.
Merolla et al. Science 345, 6197 (2014)
Diamond et al. Frontiers in
Neuroscience vol. 9, 491 (2016)
Artificial Intelligence (AI)
using Emerging Devices
and Architectures
Takes inspiration from both
The modern day computer
The human brain
Attempts to eliminate Von Neumann bottleneck
Increases speed and reduces power consumption
A Popular NN Algorithm:
Fully Connected Neural Network (FCNN)
Forward computation:
Vector Matrix Multiplication
(VMM) , activation (tanh)
w1,0
x1
w1,1
x2
Input
nodes
w1,2 y1 ∑
x2
xm
.
.
.
y2
∑
w1,784
w1n
y3
y3
y4
x784
Synapse
(memory)
∑
∑
Neuron (computation)
.
.
z1 .
f
z2
f
x2
zn
x784
z10
y1
y1 .
f .
y3 . .
.
.
.
.
y1 .
y2
x2
yn
y10
f
Output
nodes
Yn : desired output
x784
Feedback computation- Stochastic
Gradient Descent (SGD) learning rule :
: learning rate
Analog Crossbar array for Neuromorphic
Implemenetation of FCNN
MATRIX
VECTOR
Very fast Vector- Matrix multiplication
- O(1) complexity
In-memory computing architecture
helps frequent weight update
Weight
update
But is this architecture equivalent to UTM?
Possible Solution if it’s not
(Using Hybrid Architecture)
Analog crossbar array
goes in here. The rest
of the system is digital.
Reference: A. Ankit et al, PUMA: A Programmable Ultra-efficient Memristor-based
Accelerator for Machine Learning Inference, ACM 2019
Module 1 (Introduction)
•
•
•
•
•
•
•
Traditional Computing (from Turing machine to
von Neumann architecture)
Memory hierarchy in von Neumann
architecture
Role of spintronic devices in the memory
hierarchy
Magnetic hard drives
MRAM, Spin Transfer Torque MRAM, Spin
Orbit Torque MRAM
Non von Neumann computing/ Neuromorphic
Computing
Suitability of spintronics in neuromorphic
computing
Synapse: Non-Volatility, Electrical
Access and Control
Inference only in the crossbar:
Non-volatility of synaptic weights
Frequent electrical readout of synaptic weights
On-chip Learning in the crossbar:
Non-volatility of synaptic weights
Frequent electrical readout of synaptic weights
Frequent electrical control/ writing of
synaptic weights
Synapse: Non-Volatility, Electrical
Access and Control
Spin Transfer Torque
Magnetic RAM (STTMRAM)
Spin Orbit Torque
Magnetic RAM (SOTMRAM)
Non-volatility: Ferromagnetic system
Electrical Read Out: Tunneling Magneto-Resistance Effect (TMR)
Electrical Writing: Spin Transfer Torque (STT), Spin Orbit Torque (SOT)
Synapse: Near-Analog Weight Storage
Synapses: Near-analog,
electrically controllable
non-volatile weights
Synapse: Near-Analog Weight Storage
Domain-Wall (DW)
synapse
Near-analog,
electrically controllable
conductance values
D. Kaushik et al.
AIP Advances 10,
025111, 2020
Neuron: Integration Property
Neuron
Leaky Integrate
Fire (LIF) model
Time between two spiking events
(v(t) reaching a threshold)
depends on the input current I(t)
Neuron: Integration Property
Time between two spiking events matches between the LIF model and
that of domain-wall-based neuron device
U. Sahu et al., AIP Advances 9, 125339 , 2019
Neuron: Oscillation and Synchronization
Spin Hall Nano
Oscillator (SHNO)
Auto-Oscillation Property
of Spintronic Oscillator
Synchronization of Spintronic Oscillators
(through dipole or spin-wave coupling)
N. Garg et al., IOP Neuromorphic Computing and Engineering, 2021