R18
HALL TICKET NO.:
. P. Code 18 ECE313
I I B.TECH I SEMESTER (R18) REGULAR EXAMINATIONS -
MARCH-2021
VLSI DESIGN
(ELECTRONICS AND COMMUNICATION ENGINEERING)
Max. Marks: 70
Time: 3 hours
PART A
10 x 2 20 Marks
Answer all the Questions
COi
List the various IC Packaging Techniques.
Define diffusion and write diffusion equation.
2
CO1
Define Threshold Voltage ofMOSFET and Write an Expression relating to Body
3
CO2
Sketch the Transfer Characteristics ofn-channel MOSFET.
CO3
What arethe uses of Stick diagram?
CO3
What are the Limitations of Scaling?
Is it possible to share the product terms between different outputs in a PAL?
7
C04
What is the full custom ASIC design?
CO5
What is atest bench?
10
5
C04
Justify.
9
1
C02
Effect.
CO5
Write abrief note on functionalitytest?
PART B
5x 10 50 Marks
Answer the following by choosing one Question from each unit
Marks
UNIT-I
11 Ilustrate and describe in detail about Ion implantation process.
CO
10
CO1
10
CO1
10
C02
10
CO2
10
CO3
10
C03
10
CO4
10
C04
10
Co5
BT
(Or)
What is meant by oxidation process. Classify the oxidation technique and
describein detail aboutthermal oxidation process
12
2
UNIT-II
13 Derive the Pull-Up to Pull-Down Ratio for CMOSInverter.
6
(Or)
6
Derive the Drain to source current Ids versus voltage Vds relationship for a
NMOS transistor when the transistor is in i) cut-off, i) Linear and ii)
14
Saturation.
UNIT-III
15 Define scaling ?what are all the factors to be considered for transistor scaling.
1
-
a)What
16
is
a
stick
diagram
?sketch the stick
(Or)
diagram
and
layout
for
a
CMOS
inverter
b)what are the effects of scaling on Vt.
UNIT-IV
17
Describe about placement algorithm with neat sketch.
2
(Or)
What is clock routing. Explain it and enumerate the difference with power
18
19
routing.
Explain the
UNIT-V
scan
path design technique using suitable example and also
describe Level-sensitive scan design (LSSD)
(Or)
20 Define a test bench. Explain in detail about test bench techniques.
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