Solid-State Electronics 54 (2010) 855–860
Contents lists available at ScienceDirect
Solid-State Electronics
journal homepage: www.elsevier.com/locate/sse
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS
scaling succession
T. Chiarella *, L. Witters, A. Mercha, C. Kerner, M. Rakowski, C. Ortolland, L.-Å. Ragnarsson, B. Parvais,
A. De Keersgieter, S. Kubicek, A. Redolfi, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, T. Hoffmann
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
a r t i c l e
i n f o
Article history:
Available online 20 May 2010
The review of this paper was arranged by
Prof. S. Cristoloveanu
Keywords:
Bulk FinFET
SOI FinFET
Parasitic capacitance/resistance
Ring-oscillator
SRAM
Variability
a b s t r a c t
The multi-gate architecture is considered as a key enabler for further CMOS scaling thanks to its
improved electrostatics and short-channel effect control. FinFETs represent one of the architectures of
interest within that family together with X-gates, P-gates, gate-all-around. . . They can readily be manufactured starting from SOI or bulk substrates even though more efforts have been dedicated to the SOI
option so far. We report in this work an extensive benchmark of their critical electrical figures of merit
(FOM) and their limitations. Both alternatives show better scalability (threshold voltage – Vt vs. L) than
PLANAR CMOS and exhibit similar intrinsic device performance (Ioff vs. Ion). Introducing SOI substrates
and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced
threshold voltage mismatch. Using an optimized integration to minimize parasitic capacitances and resistances we demonstrate high-performing FinFET ring-oscillators with delays down to 10 ps/stage for both
SOI and bulk FinFETs. SRAM cells are also reported to work, scaling similarly with the supply voltage
(VDD) for the two FinFET integration schemes.
Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction
FinFET is an attractive alternative to the conventional high-k
metal gate planar devices [1–3] to meet the challenging targets
set by the industry [4]. The processing sequences of both PLANAR
and FinFET architectures mainly differ in the isolation and gate
stack modules. The increasing complexity of CMOS gate stack engineering (multiple gate electrode, capping layers. . .) may be relaxed
by using multiple-gate devices for regular Vt applications (RVT)
[5,6]. This advantage is depicted in Fig. 1, which is also revealing
the geometry of the devices and the gate stack details for PLANAR
and FinFET built on both SOI and bulk substrates. The downscaling
of bulk FinFETs to meet the 22-nm technology node has been addressed in previous work [7] where a calibrated model and 3-D
mixed mode simulations have been performed. These results show
that, with careful optimization, bulk FinFETs give a promising
alternative to SOI FinFETS.
Additionally, FinFETs offer better short-channel effects (SCE)
control achieving similar long-channel Vt with delayed short-channel degradation for nFET and pFET. This is clearly depicted in
Fig. 2a where two PLANAR references are used, with the ‘no cap’
one being very high in the threshold voltage range. Using a
* Corresponding author. Tel.: +32 16 28 86 05; fax: +32 16 281844.
E-mail address: thomas.chiarella@imec.be (T. Chiarella).
0038-1101/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2010.04.010
La-based capping layer in the nFET case [AlO for pFET] results in
complete shift of the roll-off characteristics towards 300 mV or
even lower Vt. This has already been reported in previous work
[1,5]. The (1 0 0)/h1 1 0i crystal orientation at the fin’s sidewall results in a better pFET to nFET drive currents ratio as depicted on
Ioff–Ion characteristics in Fig. 3a with 680 lA/lm and 725 lA/lm
Id_sat at target Ioff of 100 nA/lm for n&pFET isolated devices. These
results are summarized together with complete Id–Vg the characteristics in Table 1 for nFET and pFET devices close to the target Ioff
for both PLANAR and SOI FinFET.
This can be exploited at the layout level for circuit area optimization [8]. Parasitic capacitances and access resistances must also
be closely monitored since both are strongly linked to the device
architectures and isolation schemes (SOI BOX vs. STI) [9]. In addition, these are also expected to play an important role in the ESD
robustness. Recent work [10] showed that the combination of
not fully used landing pads for current conduction, with complete
junction capacitance contribution in narrow fins, reduced the initial bulk FinFET ESD advantage over SOI FinFET. Both find their
place side by side in the overall benchmark with similar ESD-RF
performance.
In this study, most of these effects are benchmarked, first at the
device level, secondly focusing on parasitics and analog performances and finally at the circuit level for ring-oscillators (RO)
and SRAM cells. These will help determining the major advantages,
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T. Chiarella et al. / Solid-State Electronics 54 (2010) 855–860
Fig. 1. PLANAR and FinFET gate stacks schematics with definition of the critical dimensions. The complexity of calibrating the latter is depicted in the x-TEM pictures,
especially for bulk FinFET.
limitations and trade-offs between both bulk (BFF) and SOI FinFET
(SOI_FF) technologies in the migration process from PLANAR to
FinFET for further scaling CMOS devices.
2. Device fabrication
A 1.5 nm EOT high-k metal gate PLANAR CMOS process using
0.7/0.9 nm LaO/AlO cap (nFET/pFET) was considered as reference.
The nFET well implant used 15 keV 2e12 cm2 B. The 1.5 nm EOT
gate stack of the FinFET devices used in this work consisted of
5 nm PVD TiN metal electrode on 2.6 nm HfSiO high-k dielectric
in addition to 1 nm thermal interfacial oxide. A 15 keV
9e12 cm2 B implant and a 90 keV 2e12 cm2 As implant were
used for BFF well doping. The relevant device geometries are indicated in the X-SEMs as depicted in Fig. 1. Achieving such device
geometries in a controlled way is of prime importance in the FinFET process flow.
As expected from the X-SEMs in Fig. 1, BFF and SOI_FF require
careful calibration of the device dimensions, namely the fin width
(finW) and the fin height (finH), mainly. The first, common to both
SOI_FF and BFF, varies along the fin length because source/drain (S/
D) pads are used for contacting the fins themselves. Also, non-ideal
optical proximity effects required the use of multi-fin (N > 5) devices to cope for narrower outer fins at the structure’s periphery.
Previous work [11,12] studied the influence of asymmetry in finW
or gate misalignment on the electrical characteristics of multi-gate
MOSFETs. Greater degradation of the drain-induced barrier lowering (DIBL) and Vt for wider finW at the drain side was measured.
The second, contributing twice to the total gate width, involves
close process follow-up and is much more challenging for the
BFF option. Some of these sources of non-uniformity will be addressed in the scope of this work but overall, BFFs add one degree
of complexity to the device geometry where SOI_FFs make use of
tightly controlled, but more expensive, substrates. The magnitude
of the global cost gain in case of BFF has been shown to be limited
after full processing. The overall cost-to-variability tradeoff still
tends to pull the balance towards SOI_FF, at least from the simulations and first level assumptions of the study, especially for predictions based on large manufacturing volumes [13].
All wafers went up to one level of metal processing, additionally
protected by a passivation layer insuring correct electrical probing.
3. Results and discussion
3.1. Device performance and Vt roll-off
Bulk FinFETs are benchmarked against their SOI FinFET counterparts. The Vt roll-off (Vt_sat vs. gate length) and Ioff–Ion characteristics of both substrates types are plotted in Figs. 2b and 3b. Similar
SCE improvement over PLANAR devices reference is reported on
non-aggressively scaled FinFETs (showing a 5 nm smaller required minimum gate length for supporting the target Ioff Lg_min
in SOI_FF). The intrinsic device performance, ranging from 700 to
750 lA/lm (at Ioff 1e7 A/lm), are measured with slightly degraded pFET BFF Ioff–Ion closer to 650 lA/lm. These results are confirmed in essence by the summary table in Table 1 comparing
SOI_FF and BFF performances for devices close to the target Ioff. It
should be noted that tuning the threshold voltage in SOI_FF shifts
the scope towards adapted gate stack engineering options, where
BFF can still propose a more conventional approach by using ion
implantation for fin doping. Costs aspects related to these very different fields of research are not tackled here but this difference
could shift the overall complexity vs. cost balance in favor of BFF.
Mobility-wise, comparable behavior is reported for long channel
with, as expected, a strong doping dependency (Fig. 4). BFF indeed
include well doping, which is not present in the SOI_FF case.
Reducing this well doping level improves the low-field mobility
characteristics, shifting them towards SOI_FF.
T. Chiarella et al. / Solid-State Electronics 54 (2010) 855–860
Fig. 2. (a) Better SCE for FinFET compared to ‘‘capped” PLANAR makes this device
architecture appealing. (b) Similar nFET and pFET SCE for SOI_FF or BFF devices (Vt
in saturation regime as a function of gate length).
3.2. Parasitic resistances and capacitances
The comparison can be extended to the parasitic components of
the transistors of interest. First of all, FinFET devices are more
prone to external resistance problems because of their more complex 3-D geometry. To account for this, the active areas received an
additional 30 nm Si SEG layer (Selective Epitaxial Growth). In addition, as already discussed in the device fabrication in Section 2, it
should be noted that the calibration of every device dimension also
requires a lot of attention in this case. The extraction of the external resistance (Rext) is performed by measuring the device resistance (scaled to the total device width ? actual finH and finW
contributions) at low drain and high gate biases as function of
the effective gate length. A higher Rext for n-type BFF compared
to PLANAR is expected as seen in Table 2 as function of fin doping.
(undoped SOI vs. doped BFF) The extracted Rext values in case of
SOI_FF or BFF are inline with the expectations (Table 2) with
200/300 X lm for nFET/pFET devices.
Further, the parasitic capacitances of FinFET devices are considered. The overlap capacitance (Cov) was first measured at 100 kHz
on a perimeter intensive structure in accumulation between the
gate and the S/D terminals. Similar range of Cov indicates correct
extension to gate overlap. Identical low-doped drain (LDD) extension implants were used for SOI_FF and BFF with an additional halo
(pocket) implant for the latter.
857
Fig. 3. (a) Achieving almost 1:1 pFET/nFET performance ratio in SOI FinFET
compared to PLANAR. (b) Comparable nFET performance and moderately degraded
pFET for bulk FinFET wrt SOI_FF.
The comparison was made with a SOI_FF reference showing
slightly degraded (too high) pFET overlap capacitance, which could
explain why the pFET Ioff–Ion characteristic (Fig. 3b) is partly outperforming the BFF counterpart. Indeed, higher Cov indicates deeper extensions under the gate, improving the drive capabilities
possibly at the expense of worse SCE but Fig. 2b shows that the
roll-off curves are comparable and that no short-channel degradation is measured for BFF. NFETs are, on the other hand, at the low
side of the expected range but nevertheless do not suffer from
underlap (little or negative gate to S/D overlap).
Junction capacitance (Cj) is another concern in such devices
since recovering the access to the bulk terminal adds some additional parasitic capacitance from source and drain to bulk as in a
PLANAR architecture. As expected, SOI_FFs show negligible parasitics benefiting from the isolated substrate in a thick BOX configuration while BFFs show moderate Cj in the range or even below that
of planar devices (Table 2), which is not unexpected seeing the
‘‘pseudo-planar” junctions involved in a BFF architecture. On the
other hand SOI_FFs can make use of a relatively thin BOX isolation.
With such architectures, the advantage coming from the almost
non-existent junction capacitance component is reduced as the
field lines, crowding through the BOX isolation, lead to an additional parasitic capacitance. However, the possibility to tune the
threshold voltage at the price of a limited added process complexity was shown in [14] for thin BOX with ground plane.
Bulk FinFETs can benefit from the body effect, by recovering
the access to the bulk terminal of the transistors, as expected
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T. Chiarella et al. / Solid-State Electronics 54 (2010) 855–860
Table 1
PLANAR and FinFET performance for N and P-type devices – inset: Id_Vg characteristics in linear and saturation regimes.
Fig. 4. Mobility curves confirm the doping dependent degradation for bulk FinFET.
Table 2
PLANAR and FinFET parasitics for N and P-type devices. BFF parasitics are close to
SOI_FF with slightly degraded nFET Rext, both higher than PLANAR.
nFET
Cov (fF/lm)
Rext (X lm)
Cj (fF/lm2)
pFET
SOI_FF
BFF
PLANAR
SOI_FF
BFF
PLANAR
0.31
236
0.10
0.33
192
0.72
0.54
151
1.06
0.42
279
0.28
289
0.41
256
for PLANAR-like devices. Up to 150 mV/V delta Vt was achieved
for wide fins (Fig. 5). This was measured as the Vt shift as function
of fin width for 1 lm down to 30 nm wide devices extracted between VB = 0 V and |VB|=1 V. Significant differences are measured
Fig. 5. BFF fin height dependent body bias matches PLANAR-like sensitivity with up
to 150 mV/V delta Vt for wide fins.
up to fin heights of 100 nm but this effect almost disappears for
small fin widths. The isolated thin or thick BOX SOI FinFETs, in
addition, suffer however from being on their substrate without
direct contact to the silicon, which can result in self heating
and Floating Body Effect (FBE) [15]. This primarily impacts the
on-state current of the devices but little degradation was demonstrated by simulation for varying fin length and pitch [16].
All these observations confirm that BFF are ‘mid-way’ between the PLANAR and SOI FinFET architectures. They do not
suffer from any specific problem but show higher junction
capacitance and similar Rext wrt SOI_FF, as expected (higher
than PLANAR).
T. Chiarella et al. / Solid-State Electronics 54 (2010) 855–860
859
3.3. Vt mismatch and analog performance
On the other hand, introducing doped fins in BFF is expected to
worsen the matching capabilities in addition to the previously cited sources of variability. The impact of fin doping can easily be
measured as depicted in Fig. 6. SOI_FF doped devices show matching characteristics >25% worse than the undoped reference for both
nFET and pFET transistors. This was measured comparing the
threshold voltages of adjacent transistor pairs. The moderately
higher slopespffiffiffiffiffiffiffiffiffiffiffi
extracted from the Pelgrom plots (Avt’s in the
r(DVt) vs. 1= ðWLÞ trends) in the case of BFF (Fig. 6) confirm this
trend. Avt’s in the range of the PLANAR reference are reported,
around 3–4 mV lm.
Looking at it from a more analog perspective, the gm/gds BFF
to SOI_FF comparison (measured at |Vg| = |Vds| = 0.6 V) in Fig. 7
shows the expected trend with BFF being slightly better than
PLANAR with the optimum for SOI_FF still benefiting from undoped fins.
Fig. 7. Better gm/gds vs. gm characteristics (dominated by fin doping) for SOI_FF.
BFF perform between PLANAR and SOI_FF, as expected.
3.4. Circuit performance and SRAM
Finally, ring-oscillators and SRAM cells have been measured to
get a combined view of all the described effects in a circuit-like
environment. Two sets of RO’s have been considered, both made
up of 41 inverter stages followed by an 8-stage divider and buffer.
The first, using a single-gate layout, although slower, shows similar
power-delay characteristics down to 20 ps/stage at an acceptable
Pstatic at Vdd = 1.0 V (Fig. 8a). Both SOI_FF and BFF characteristics
follow the same trend; only the effective device geometry differentiates the two RO power-delay curves as seen from the excursion
on the x-axis for both Pstat and Pact. The second, allowing a more
extensive benchmarking vs. SOI_FF but also vs. PLANAR HiK/MG or
Poly/SiON confirms the trend down to 10 ps/stage (Fig. 8b) thanks
to an optimized layout (multiple-gate access, nFET to pFET ratio
improvement, shared contacts on the drain side, reduction of the
parasitic capacitances, etc.).
The 6-T SRAM cells of interest in this work make use of singlefin devices with 20 nm wide fins and gate length (Lg) of 45 nm
(drawn). Their layout is shown in the insert of Fig. 9 in which half
of a single cell is detailed both schematically and on the corresponding SEM picture. These indicate the position of the wiredout pass-gate (PG), pull-up (PU) and pull-down (PD) transistors
that are the building blocks of the entire cell. They all can be measured independently to capture the device characteristics for the
left and the right side inside the SRAM cell.
Fig. 8. (a) One to one single gate RO benchmark showing matching BFF and SOI_FF
performances, both active and static power. Detail: non-optimized RO layout and
SEM picture. (b) Optimized layout BFF RO inline with SOI_FF reference reaching
10 ps/stage inverter delay, comparable to the PLANAR counterpart. Detail: optimized RO layout.
Fig. 6. The Pelgrom plot confirms the degradation in BFF mismatch compared to
SOI_FF but inline with PLANAR (Avt 3–4 mV lm).
The butterfly curves (Vout vs. Vin) in Fig. 9 show comparable
characteristics at Vdd = 1.0 V for SOI_FF and BFF with Static Noise
Margins (SNM) around 240 mV for SOI and 170–180 mV for BFF.
Further, measuring the SNM for different bias conditions showed
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T. Chiarella et al. / Solid-State Electronics 54 (2010) 855–860
and similar scaling for both BFF and SOI_FF as function of the supply voltage.
Acknowledgments
The authors would like to thank the IMEC P-line for processing
the wafers and the Amsimec group for performing successful parametric measurements.
References
Fig. 9. The 6-T FinFET SRAM butterfly curves for SOI_FF and BFF show similar VDD
scaling. Detail: single-fin SRAM cell layout and SEM (b-ratio 1).
similar VDD scaling for both BFF and SOI_FF. From the wired out
devices a similar FOM can be extracted as for the matching transistor pairs, here reduced to one device dimension. For all three device flavors (PG, PU and PD) the rVt for BFF was three times that
of SOI_FF, as could be expected from the previous remarks made
on the device dimensions (Fig. 1). This gives a hint about the positioning of BFF towards PLANAR or SOI_FF in terms of variability,
which has been already characterized in more details in [17] and
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4. Conclusions
Bulk FinFETs offer a strong alternative to PLANAR CMOS for
down scaling along the More Moore path. Their comparable intrinsic performances combined with the expected parasitic capacitances and resistances offer, at the circuit level, similar power
delay trade-offs to SOI FinFETs. The opportunities and challenges
linked to both options in order to keep good short-channel control
and drive capabilities reside in the ability to minimize parasitics
and offer reasonable threshold voltage tuning for each application.
The calibration to the device dimensions, which is of prime importance in scaling the measured figures of merit, was shown to be
more critical in case of BFF. Recent work indicates their similar
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mismatch. These results were confirmed at the SRAM level with
three times lower Vt mismatch for SOI_FF in a ‘dense’ environment.
SRAM stability results confirm this trend with reasonable SNM extracted from the butterfly curves at Vdd = 1.0 V (better for SOI_FF)
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