Assignment 2
Question 1
(a) An instruction is stored at location 300 with its address field at location 301. The address field at location 301
has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the
addressing mode of the instruction is
i.
Direct
[3]
i.
Indirect
[3]
(b) The CPU time of a program is defined as the product of the CPI (cycles per instruction) for the processor on
which it runs, the total number of instructions executed (I), and processor clock period (ϕ). List any five major
factors, which influence CPU time.
[5]
(c) In the context of pipelined processor design, explain the meaning of the following terms and give examples
of each:
i. Structural dependency.
ii. Control dependency.
iii. Data dependency.
[9]
Question 2
(a) Distinguish between a two bus data path from a three bus data path.
[4]
(b) Describe the basic elements of a memory hierarchy.
[5]
(c) Describe with the aid of diagram three types of pipeline hazards.
[9]
(d) Describe what happens when Cache Hit occurs?
[2]
Question
3
(a) What is the output of this MIPS code
(explain each step)
[8]
addi $s0, $0, 4
addi $s1, $0, 1
sll $s1, $s1, 2
beq $s0, $s1,
addi $s1, $s1,
sub $s1, $s1, $s0
(b) CISC continues to outpace RISC. Discuss.
[6]
(c) Copy and complete the table below to show how the instruction will flow through the pipeline.
[6]
1
lw $10, 0($11)
add $9 ,$11,$11
sub $8 ,$10, $9
lw $7 , 0($8)
sw $7 , 4($8)
2
3
4
5
6
7
8
9
10
11
12